1/* 2 * IBM Automatic Server Restart driver. 3 * 4 * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru> 5 * 6 * Based on driver written by Pete Reynolds. 7 * Copyright (c) IBM Corporation, 1998-2004. 8 * 9 * This software may be used and distributed according to the terms 10 * of the GNU Public License, incorporated herein by reference. 11 */ 12 13#include <linux/fs.h> 14#include <linux/kernel.h> 15#include <linux/module.h> 16#include <linux/pci.h> 17#include <linux/timer.h> 18#include <linux/miscdevice.h> 19#include <linux/watchdog.h> 20#include <linux/dmi.h> 21#include <linux/io.h> 22#include <linux/uaccess.h> 23 24 25enum { 26 ASMTYPE_UNKNOWN, 27 ASMTYPE_TOPAZ, 28 ASMTYPE_JASPER, 29 ASMTYPE_PEARL, 30 ASMTYPE_JUNIPER, 31 ASMTYPE_SPRUCE, 32}; 33 34#define PFX "ibmasr: " 35 36#define TOPAZ_ASR_REG_OFFSET 4 37#define TOPAZ_ASR_TOGGLE 0x40 38#define TOPAZ_ASR_DISABLE 0x80 39 40/* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */ 41#define PEARL_BASE 0xe04 42#define PEARL_WRITE 0xe06 43#define PEARL_READ 0xe07 44 45#define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */ 46#define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */ 47 48/* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */ 49#define JASPER_ASR_REG_OFFSET 0x38 50 51#define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */ 52#define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */ 53 54#define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */ 55#define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */ 56#define JUNIPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */ 57 58#define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */ 59#define SPRUCE_ASR_DISABLE_MASK 0x01 /* bit 1: disable = 1 enable = 0 */ 60#define SPRUCE_ASR_TOGGLE_MASK 0x02 /* bit 0: 0, then 1, then 0 */ 61 62 63static int nowayout = WATCHDOG_NOWAYOUT; 64 65static unsigned long asr_is_open; 66static char asr_expect_close; 67 68static unsigned int asr_type, asr_base, asr_length; 69static unsigned int asr_read_addr, asr_write_addr; 70static unsigned char asr_toggle_mask, asr_disable_mask; 71static spinlock_t asr_lock; 72 73static void __asr_toggle(void) 74{ 75 unsigned char reg; 76 77 reg = inb(asr_read_addr); 78 79 outb(reg & ~asr_toggle_mask, asr_write_addr); 80 reg = inb(asr_read_addr); 81 82 outb(reg | asr_toggle_mask, asr_write_addr); 83 reg = inb(asr_read_addr); 84 85 outb(reg & ~asr_toggle_mask, asr_write_addr); 86 reg = inb(asr_read_addr); 87} 88 89static void asr_toggle(void) 90{ 91 spin_lock(&asr_lock); 92 __asr_toggle(); 93 spin_unlock(&asr_lock); 94} 95 96static void asr_enable(void) 97{ 98 unsigned char reg; 99 100 spin_lock(&asr_lock); 101 if (asr_type == ASMTYPE_TOPAZ) { 102 /* asr_write_addr == asr_read_addr */ 103 reg = inb(asr_read_addr); 104 outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE), 105 asr_read_addr); 106 } else { 107 /* 108 * First make sure the hardware timer is reset by toggling 109 * ASR hardware timer line. 110 */ 111 __asr_toggle(); 112 113 reg = inb(asr_read_addr); 114 outb(reg & ~asr_disable_mask, asr_write_addr); 115 } 116 reg = inb(asr_read_addr); 117 spin_unlock(&asr_lock); 118} 119 120static void asr_disable(void) 121{ 122 unsigned char reg; 123 124 spin_lock(&asr_lock); 125 reg = inb(asr_read_addr); 126 127 if (asr_type == ASMTYPE_TOPAZ) 128 /* asr_write_addr == asr_read_addr */ 129 outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE, 130 asr_read_addr); 131 else { 132 outb(reg | asr_toggle_mask, asr_write_addr); 133 reg = inb(asr_read_addr); 134 135 outb(reg | asr_disable_mask, asr_write_addr); 136 } 137 reg = inb(asr_read_addr); 138 spin_unlock(&asr_lock); 139} 140 141static int __init asr_get_base_address(void) 142{ 143 unsigned char low, high; 144 const char *type = ""; 145 146 asr_length = 1; 147 148 switch (asr_type) { 149 case ASMTYPE_TOPAZ: 150 /* SELECT SuperIO CHIP FOR QUERYING 151 (WRITE 0x07 TO BOTH 0x2E and 0x2F) */ 152 outb(0x07, 0x2e); 153 outb(0x07, 0x2f); 154 155 /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */ 156 outb(0x60, 0x2e); 157 high = inb(0x2f); 158 159 /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */ 160 outb(0x61, 0x2e); 161 low = inb(0x2f); 162 163 asr_base = (high << 16) | low; 164 asr_read_addr = asr_write_addr = 165 asr_base + TOPAZ_ASR_REG_OFFSET; 166 asr_length = 5; 167 168 break; 169 170 case ASMTYPE_JASPER: 171 type = "Jaspers "; 172 173/* spin_lock_irqsave(&pci_config_lock, flags);*/ 174 175 /* Select the SuperIO chip in the PCI I/O port register */ 176 outl(0x8000f858, 0xcf8); 177 178 /* BUS 0, Slot 1F, fnc 0, offset 58 */ 179 180 /* 181 * Read the base address for the SuperIO chip. 182 * Only the lower 16 bits are valid, but the address is word 183 * aligned so the last bit must be masked off. 184 */ 185 asr_base = inl(0xcfc) & 0xfffe; 186 187/* spin_unlock_irqrestore(&pci_config_lock, flags);*/ 188 asr_read_addr = asr_write_addr = 189 asr_base + JASPER_ASR_REG_OFFSET; 190 asr_toggle_mask = JASPER_ASR_TOGGLE_MASK; 191 asr_disable_mask = JASPER_ASR_DISABLE_MASK; 192 asr_length = JASPER_ASR_REG_OFFSET + 1; 193 194 break; 195 196 case ASMTYPE_PEARL: 197 type = "Pearls "; 198 asr_base = PEARL_BASE; 199 asr_read_addr = PEARL_READ; 200 asr_write_addr = PEARL_WRITE; 201 asr_toggle_mask = PEARL_ASR_TOGGLE_MASK; 202 asr_disable_mask = PEARL_ASR_DISABLE_MASK; 203 asr_length = 4; 204 break; 205 206 case ASMTYPE_JUNIPER: 207 type = "Junipers "; 208 asr_base = JUNIPER_BASE_ADDRESS; 209 asr_read_addr = asr_write_addr = asr_base; 210 asr_toggle_mask = JUNIPER_ASR_TOGGLE_MASK; 211 asr_disable_mask = JUNIPER_ASR_DISABLE_MASK; 212 break; 213 214 case ASMTYPE_SPRUCE: 215 type = "Spruce's "; 216 asr_base = SPRUCE_BASE_ADDRESS; 217 asr_read_addr = asr_write_addr = asr_base; 218 asr_toggle_mask = SPRUCE_ASR_TOGGLE_MASK; 219 asr_disable_mask = SPRUCE_ASR_DISABLE_MASK; 220 break; 221 } 222 223 if (!request_region(asr_base, asr_length, "ibmasr")) { 224 printk(KERN_ERR PFX "address %#x already in use\n", 225 asr_base); 226 return -EBUSY; 227 } 228 229 printk(KERN_INFO PFX "found %sASR @ addr %#x\n", type, asr_base); 230 231 return 0; 232} 233 234 235static ssize_t asr_write(struct file *file, const char __user *buf, 236 size_t count, loff_t *ppos) 237{ 238 if (count) { 239 if (!nowayout) { 240 size_t i; 241 242 /* In case it was set long ago */ 243 asr_expect_close = 0; 244 245 for (i = 0; i != count; i++) { 246 char c; 247 if (get_user(c, buf + i)) 248 return -EFAULT; 249 if (c == 'V') 250 asr_expect_close = 42; 251 } 252 } 253 asr_toggle(); 254 } 255 return count; 256} 257 258static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 259{ 260 static const struct watchdog_info ident = { 261 .options = WDIOF_KEEPALIVEPING | 262 WDIOF_MAGICCLOSE, 263 .identity = "IBM ASR", 264 }; 265 void __user *argp = (void __user *)arg; 266 int __user *p = argp; 267 int heartbeat; 268 269 switch (cmd) { 270 case WDIOC_GETSUPPORT: 271 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; 272 case WDIOC_GETSTATUS: 273 case WDIOC_GETBOOTSTATUS: 274 return put_user(0, p); 275 case WDIOC_SETOPTIONS: 276 { 277 int new_options, retval = -EINVAL; 278 if (get_user(new_options, p)) 279 return -EFAULT; 280 if (new_options & WDIOS_DISABLECARD) { 281 asr_disable(); 282 retval = 0; 283 } 284 if (new_options & WDIOS_ENABLECARD) { 285 asr_enable(); 286 asr_toggle(); 287 retval = 0; 288 } 289 return retval; 290 } 291 case WDIOC_KEEPALIVE: 292 asr_toggle(); 293 return 0; 294 /* 295 * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT 296 * and WDIOC_GETTIMEOUT always returns 256. 297 */ 298 case WDIOC_GETTIMEOUT: 299 heartbeat = 256; 300 return put_user(heartbeat, p); 301 default: 302 return -ENOTTY; 303 } 304} 305 306static int asr_open(struct inode *inode, struct file *file) 307{ 308 if (test_and_set_bit(0, &asr_is_open)) 309 return -EBUSY; 310 311 asr_toggle(); 312 asr_enable(); 313 314 return nonseekable_open(inode, file); 315} 316 317static int asr_release(struct inode *inode, struct file *file) 318{ 319 if (asr_expect_close == 42) 320 asr_disable(); 321 else { 322 printk(KERN_CRIT PFX 323 "unexpected close, not stopping watchdog!\n"); 324 asr_toggle(); 325 } 326 clear_bit(0, &asr_is_open); 327 asr_expect_close = 0; 328 return 0; 329} 330 331static const struct file_operations asr_fops = { 332 .owner = THIS_MODULE, 333 .llseek = no_llseek, 334 .write = asr_write, 335 .unlocked_ioctl = asr_ioctl, 336 .open = asr_open, 337 .release = asr_release, 338}; 339 340static struct miscdevice asr_miscdev = { 341 .minor = WATCHDOG_MINOR, 342 .name = "watchdog", 343 .fops = &asr_fops, 344}; 345 346 347struct ibmasr_id { 348 const char *desc; 349 int type; 350}; 351 352static struct ibmasr_id __initdata ibmasr_id_table[] = { 353 { "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ }, 354 { "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL }, 355 { "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER }, 356 { "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER }, 357 { "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE }, 358 { NULL } 359}; 360 361static int __init ibmasr_init(void) 362{ 363 struct ibmasr_id *id; 364 int rc; 365 366 for (id = ibmasr_id_table; id->desc; id++) { 367 if (dmi_find_device(DMI_DEV_TYPE_OTHER, id->desc, NULL)) { 368 asr_type = id->type; 369 break; 370 } 371 } 372 373 if (!asr_type) 374 return -ENODEV; 375 376 spin_lock_init(&asr_lock); 377 378 rc = asr_get_base_address(); 379 if (rc) 380 return rc; 381 382 rc = misc_register(&asr_miscdev); 383 if (rc < 0) { 384 release_region(asr_base, asr_length); 385 printk(KERN_ERR PFX "failed to register misc device\n"); 386 return rc; 387 } 388 389 return 0; 390} 391 392static void __exit ibmasr_exit(void) 393{ 394 if (!nowayout) 395 asr_disable(); 396 397 misc_deregister(&asr_miscdev); 398 399 release_region(asr_base, asr_length); 400} 401 402module_init(ibmasr_init); 403module_exit(ibmasr_exit); 404 405module_param(nowayout, int, 0); 406MODULE_PARM_DESC(nowayout, 407 "Watchdog cannot be stopped once started (default=" 408 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 409 410MODULE_DESCRIPTION("IBM Automatic Server Restart driver"); 411MODULE_AUTHOR("Andrey Panin"); 412MODULE_LICENSE("GPL"); 413MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); 414