1/* 2 * Common utility functions for VGA-based graphics cards. 3 * 4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive for 8 * more details. 9 * 10 * Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) 11 */ 12 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/string.h> 16#include <linux/fb.h> 17#include <linux/svga.h> 18#include <asm/types.h> 19#include <asm/io.h> 20 21 22/* Write a CRT register value spread across multiple registers */ 23void svga_wcrt_multi(const struct vga_regset *regset, u32 value) { 24 25 u8 regval, bitval, bitnum; 26 27 while (regset->regnum != VGA_REGSET_END_VAL) { 28 regval = vga_rcrt(NULL, regset->regnum); 29 bitnum = regset->lowbit; 30 while (bitnum <= regset->highbit) { 31 bitval = 1 << bitnum; 32 regval = regval & ~bitval; 33 if (value & 1) regval = regval | bitval; 34 bitnum ++; 35 value = value >> 1; 36 } 37 vga_wcrt(NULL, regset->regnum, regval); 38 regset ++; 39 } 40} 41 42/* Write a sequencer register value spread across multiple registers */ 43void svga_wseq_multi(const struct vga_regset *regset, u32 value) { 44 45 u8 regval, bitval, bitnum; 46 47 while (regset->regnum != VGA_REGSET_END_VAL) { 48 regval = vga_rseq(NULL, regset->regnum); 49 bitnum = regset->lowbit; 50 while (bitnum <= regset->highbit) { 51 bitval = 1 << bitnum; 52 regval = regval & ~bitval; 53 if (value & 1) regval = regval | bitval; 54 bitnum ++; 55 value = value >> 1; 56 } 57 vga_wseq(NULL, regset->regnum, regval); 58 regset ++; 59 } 60} 61 62static unsigned int svga_regset_size(const struct vga_regset *regset) 63{ 64 u8 count = 0; 65 66 while (regset->regnum != VGA_REGSET_END_VAL) { 67 count += regset->highbit - regset->lowbit + 1; 68 regset ++; 69 } 70 return 1 << count; 71} 72 73 74/* ------------------------------------------------------------------------- */ 75 76 77/* Set graphics controller registers to sane values */ 78void svga_set_default_gfx_regs(void) 79{ 80 /* All standard GFX registers (GR00 - GR08) */ 81 vga_wgfx(NULL, VGA_GFX_SR_VALUE, 0x00); 82 vga_wgfx(NULL, VGA_GFX_SR_ENABLE, 0x00); 83 vga_wgfx(NULL, VGA_GFX_COMPARE_VALUE, 0x00); 84 vga_wgfx(NULL, VGA_GFX_DATA_ROTATE, 0x00); 85 vga_wgfx(NULL, VGA_GFX_PLANE_READ, 0x00); 86 vga_wgfx(NULL, VGA_GFX_MODE, 0x00); 87/* vga_wgfx(NULL, VGA_GFX_MODE, 0x20); */ 88/* vga_wgfx(NULL, VGA_GFX_MODE, 0x40); */ 89 vga_wgfx(NULL, VGA_GFX_MISC, 0x05); 90/* vga_wgfx(NULL, VGA_GFX_MISC, 0x01); */ 91 vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x0F); 92 vga_wgfx(NULL, VGA_GFX_BIT_MASK, 0xFF); 93} 94 95/* Set attribute controller registers to sane values */ 96void svga_set_default_atc_regs(void) 97{ 98 u8 count; 99 100 vga_r(NULL, 0x3DA); 101 vga_w(NULL, VGA_ATT_W, 0x00); 102 103 /* All standard ATC registers (AR00 - AR14) */ 104 for (count = 0; count <= 0xF; count ++) 105 svga_wattr(count, count); 106 107 svga_wattr(VGA_ATC_MODE, 0x01); 108/* svga_wattr(VGA_ATC_MODE, 0x41); */ 109 svga_wattr(VGA_ATC_OVERSCAN, 0x00); 110 svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F); 111 svga_wattr(VGA_ATC_PEL, 0x00); 112 svga_wattr(VGA_ATC_COLOR_PAGE, 0x00); 113 114 vga_r(NULL, 0x3DA); 115 vga_w(NULL, VGA_ATT_W, 0x20); 116} 117 118/* Set sequencer registers to sane values */ 119void svga_set_default_seq_regs(void) 120{ 121 /* Standard sequencer registers (SR01 - SR04), SR00 is not set */ 122 vga_wseq(NULL, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS); 123 vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES); 124 vga_wseq(NULL, VGA_SEQ_CHARACTER_MAP, 0x00); 125/* vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */ 126 vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE); 127} 128 129/* Set CRTC registers to sane values */ 130void svga_set_default_crt_regs(void) 131{ 132 /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */ 133 svga_wcrt_mask(0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */ 134 vga_wcrt(NULL, VGA_CRTC_PRESET_ROW, 0); 135 svga_wcrt_mask(VGA_CRTC_MAX_SCAN, 0, 0x1F); 136 vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0); 137 vga_wcrt(NULL, VGA_CRTC_MODE, 0xE3); 138} 139 140void svga_set_textmode_vga_regs(void) 141{ 142 /* svga_wseq_mask(0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */ 143 vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM); 144 vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, 0x03); 145 146 vga_wcrt(NULL, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */ 147 vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0x1f); 148 svga_wcrt_mask(VGA_CRTC_MODE, 0x23, 0x7f); 149 150 vga_wcrt(NULL, VGA_CRTC_CURSOR_START, 0x0d); 151 vga_wcrt(NULL, VGA_CRTC_CURSOR_END, 0x0e); 152 vga_wcrt(NULL, VGA_CRTC_CURSOR_HI, 0x00); 153 vga_wcrt(NULL, VGA_CRTC_CURSOR_LO, 0x00); 154 155 vga_wgfx(NULL, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */ 156 vga_wgfx(NULL, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */ 157 vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x00); 158 159 vga_r(NULL, 0x3DA); 160 vga_w(NULL, VGA_ATT_W, 0x00); 161 162 svga_wattr(0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */ 163 svga_wattr(0x13, 0x08); /* Horizontal Pixel Panning Register */ 164 165 vga_r(NULL, 0x3DA); 166 vga_w(NULL, VGA_ATT_W, 0x20); 167} 168 169 170 171/* ------------------------------------------------------------------------- */ 172 173 174void svga_settile(struct fb_info *info, struct fb_tilemap *map) 175{ 176 const u8 *font = map->data; 177 u8 __iomem *fb = (u8 __iomem *)info->screen_base; 178 int i, c; 179 180 if ((map->width != 8) || (map->height != 16) || 181 (map->depth != 1) || (map->length != 256)) { 182 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", 183 info->node, map->width, map->height, map->depth, map->length); 184 return; 185 } 186 187 fb += 2; 188 for (c = 0; c < map->length; c++) { 189 for (i = 0; i < map->height; i++) { 190 fb_writeb(font[i], fb + i * 4); 191// fb[i * 4] = font[i]; 192 } 193 fb += 128; 194 font += map->height; 195 } 196} 197 198/* Copy area in text (tileblit) mode */ 199void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area) 200{ 201 int dx, dy; 202 /* colstride is halved in this function because u16 are used */ 203 int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); 204 int rowstride = colstride * (info->var.xres_virtual / 8); 205 u16 __iomem *fb = (u16 __iomem *) info->screen_base; 206 u16 __iomem *src, *dst; 207 208 if ((area->sy > area->dy) || 209 ((area->sy == area->dy) && (area->sx > area->dx))) { 210 src = fb + area->sx * colstride + area->sy * rowstride; 211 dst = fb + area->dx * colstride + area->dy * rowstride; 212 } else { 213 src = fb + (area->sx + area->width - 1) * colstride 214 + (area->sy + area->height - 1) * rowstride; 215 dst = fb + (area->dx + area->width - 1) * colstride 216 + (area->dy + area->height - 1) * rowstride; 217 218 colstride = -colstride; 219 rowstride = -rowstride; 220 } 221 222 for (dy = 0; dy < area->height; dy++) { 223 u16 __iomem *src2 = src; 224 u16 __iomem *dst2 = dst; 225 for (dx = 0; dx < area->width; dx++) { 226 fb_writew(fb_readw(src2), dst2); 227// *dst2 = *src2; 228 src2 += colstride; 229 dst2 += colstride; 230 } 231 src += rowstride; 232 dst += rowstride; 233 } 234} 235 236/* Fill area in text (tileblit) mode */ 237void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect) 238{ 239 int dx, dy; 240 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); 241 int rowstride = colstride * (info->var.xres_virtual / 8); 242 int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg); 243 u8 __iomem *fb = (u8 __iomem *)info->screen_base; 244 fb += rect->sx * colstride + rect->sy * rowstride; 245 246 for (dy = 0; dy < rect->height; dy++) { 247 u8 __iomem *fb2 = fb; 248 for (dx = 0; dx < rect->width; dx++) { 249 fb_writeb(rect->index, fb2); 250 fb_writeb(attr, fb2 + 1); 251 fb2 += colstride; 252 } 253 fb += rowstride; 254 } 255} 256 257/* Write text in text (tileblit) mode */ 258void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit) 259{ 260 int dx, dy, i; 261 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK); 262 int rowstride = colstride * (info->var.xres_virtual / 8); 263 int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg); 264 u8 __iomem *fb = (u8 __iomem *)info->screen_base; 265 fb += blit->sx * colstride + blit->sy * rowstride; 266 267 i=0; 268 for (dy=0; dy < blit->height; dy ++) { 269 u8 __iomem *fb2 = fb; 270 for (dx = 0; dx < blit->width; dx ++) { 271 fb_writeb(blit->indices[i], fb2); 272 fb_writeb(attr, fb2 + 1); 273 fb2 += colstride; 274 i ++; 275 if (i == blit->length) return; 276 } 277 fb += rowstride; 278 } 279 280} 281 282/* Set cursor in text (tileblit) mode */ 283void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) 284{ 285 u8 cs = 0x0d; 286 u8 ce = 0x0e; 287 u16 pos = cursor->sx + (info->var.xoffset / 8) 288 + (cursor->sy + (info->var.yoffset / 16)) 289 * (info->var.xres_virtual / 8); 290 291 if (! cursor -> mode) 292 return; 293 294 svga_wcrt_mask(0x0A, 0x20, 0x20); /* disable cursor */ 295 296 if (cursor -> shape == FB_TILE_CURSOR_NONE) 297 return; 298 299 switch (cursor -> shape) { 300 case FB_TILE_CURSOR_UNDERLINE: 301 cs = 0x0d; 302 break; 303 case FB_TILE_CURSOR_LOWER_THIRD: 304 cs = 0x09; 305 break; 306 case FB_TILE_CURSOR_LOWER_HALF: 307 cs = 0x07; 308 break; 309 case FB_TILE_CURSOR_TWO_THIRDS: 310 cs = 0x05; 311 break; 312 case FB_TILE_CURSOR_BLOCK: 313 cs = 0x01; 314 break; 315 } 316 317 /* set cursor position */ 318 vga_wcrt(NULL, 0x0E, pos >> 8); 319 vga_wcrt(NULL, 0x0F, pos & 0xFF); 320 321 vga_wcrt(NULL, 0x0B, ce); /* set cursor end */ 322 vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */ 323} 324 325int svga_get_tilemax(struct fb_info *info) 326{ 327 return 256; 328} 329 330/* Get capabilities of accelerator based on the mode */ 331 332void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps, 333 struct fb_var_screeninfo *var) 334{ 335 if (var->bits_per_pixel == 0) { 336 /* can only support 256 8x16 bitmap */ 337 caps->x = 1 << (8 - 1); 338 caps->y = 1 << (16 - 1); 339 caps->len = 256; 340 } else { 341 caps->x = (var->bits_per_pixel == 4) ? 1 << (8 - 1) : ~(u32)0; 342 caps->y = ~(u32)0; 343 caps->len = ~(u32)0; 344 } 345} 346EXPORT_SYMBOL(svga_get_caps); 347 348/* ------------------------------------------------------------------------- */ 349 350 351/* 352 * Compute PLL settings (M, N, R) 353 * F_VCO = (F_BASE * M) / N 354 * F_OUT = F_VCO / (2^R) 355 */ 356 357static inline u32 abs_diff(u32 a, u32 b) 358{ 359 return (a > b) ? (a - b) : (b - a); 360} 361 362int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) 363{ 364 u16 am, an, ar; 365 u32 f_vco, f_current, delta_current, delta_best; 366 367 pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted); 368 369 ar = pll->r_max; 370 f_vco = f_wanted << ar; 371 372 /* overflow check */ 373 if ((f_vco >> ar) != f_wanted) 374 return -EINVAL; 375 376 /* It is usually better to have greater VCO clock 377 because of better frequency stability. 378 So first try r_max, then r smaller. */ 379 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { 380 ar--; 381 f_vco = f_vco >> 1; 382 } 383 384 /* VCO bounds check */ 385 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) 386 return -EINVAL; 387 388 delta_best = 0xFFFFFFFF; 389 *m = 0; 390 *n = 0; 391 *r = ar; 392 393 am = pll->m_min; 394 an = pll->n_min; 395 396 while ((am <= pll->m_max) && (an <= pll->n_max)) { 397 f_current = (pll->f_base * am) / an; 398 delta_current = abs_diff (f_current, f_vco); 399 400 if (delta_current < delta_best) { 401 delta_best = delta_current; 402 *m = am; 403 *n = an; 404 } 405 406 if (f_current <= f_vco) { 407 am ++; 408 } else { 409 an ++; 410 } 411 } 412 413 f_current = (pll->f_base * *m) / *n; 414 pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current); 415 pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r); 416 return 0; 417} 418 419 420/* ------------------------------------------------------------------------- */ 421 422 423/* Check CRT timing values */ 424int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node) 425{ 426 u32 value; 427 428 var->xres = (var->xres+7)&~7; 429 var->left_margin = (var->left_margin+7)&~7; 430 var->right_margin = (var->right_margin+7)&~7; 431 var->hsync_len = (var->hsync_len+7)&~7; 432 433 /* Check horizontal total */ 434 value = var->xres + var->left_margin + var->right_margin + var->hsync_len; 435 if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs)) 436 return -EINVAL; 437 438 /* Check horizontal display and blank start */ 439 value = var->xres; 440 if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs)) 441 return -EINVAL; 442 if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs)) 443 return -EINVAL; 444 445 /* Check horizontal sync start */ 446 value = var->xres + var->right_margin; 447 if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs)) 448 return -EINVAL; 449 450 /* Check horizontal blank end (or length) */ 451 value = var->left_margin + var->right_margin + var->hsync_len; 452 if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs))) 453 return -EINVAL; 454 455 /* Check horizontal sync end (or length) */ 456 value = var->hsync_len; 457 if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs))) 458 return -EINVAL; 459 460 /* Check vertical total */ 461 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; 462 if ((value - 1) >= svga_regset_size(tm->v_total_regs)) 463 return -EINVAL; 464 465 /* Check vertical display and blank start */ 466 value = var->yres; 467 if ((value - 1) >= svga_regset_size(tm->v_display_regs)) 468 return -EINVAL; 469 if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs)) 470 return -EINVAL; 471 472 /* Check vertical sync start */ 473 value = var->yres + var->lower_margin; 474 if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs)) 475 return -EINVAL; 476 477 /* Check vertical blank end (or length) */ 478 value = var->upper_margin + var->lower_margin + var->vsync_len; 479 if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs))) 480 return -EINVAL; 481 482 /* Check vertical sync end (or length) */ 483 value = var->vsync_len; 484 if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs))) 485 return -EINVAL; 486 487 return 0; 488} 489 490/* Set CRT timing registers */ 491void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, 492 u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node) 493{ 494 u8 regval; 495 u32 value; 496 497 value = var->xres + var->left_margin + var->right_margin + var->hsync_len; 498 value = (value * hmul) / hdiv; 499 pr_debug("fb%d: horizontal total : %d\n", node, value); 500 svga_wcrt_multi(tm->h_total_regs, (value / 8) - 5); 501 502 value = var->xres; 503 value = (value * hmul) / hdiv; 504 pr_debug("fb%d: horizontal display : %d\n", node, value); 505 svga_wcrt_multi(tm->h_display_regs, (value / 8) - 1); 506 507 value = var->xres; 508 value = (value * hmul) / hdiv; 509 pr_debug("fb%d: horizontal blank start: %d\n", node, value); 510 svga_wcrt_multi(tm->h_blank_start_regs, (value / 8) - 1 + hborder); 511 512 value = var->xres + var->left_margin + var->right_margin + var->hsync_len; 513 value = (value * hmul) / hdiv; 514 pr_debug("fb%d: horizontal blank end : %d\n", node, value); 515 svga_wcrt_multi(tm->h_blank_end_regs, (value / 8) - 1 - hborder); 516 517 value = var->xres + var->right_margin; 518 value = (value * hmul) / hdiv; 519 pr_debug("fb%d: horizontal sync start : %d\n", node, value); 520 svga_wcrt_multi(tm->h_sync_start_regs, (value / 8)); 521 522 value = var->xres + var->right_margin + var->hsync_len; 523 value = (value * hmul) / hdiv; 524 pr_debug("fb%d: horizontal sync end : %d\n", node, value); 525 svga_wcrt_multi(tm->h_sync_end_regs, (value / 8)); 526 527 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; 528 value = (value * vmul) / vdiv; 529 pr_debug("fb%d: vertical total : %d\n", node, value); 530 svga_wcrt_multi(tm->v_total_regs, value - 2); 531 532 value = var->yres; 533 value = (value * vmul) / vdiv; 534 pr_debug("fb%d: vertical display : %d\n", node, value); 535 svga_wcrt_multi(tm->v_display_regs, value - 1); 536 537 value = var->yres; 538 value = (value * vmul) / vdiv; 539 pr_debug("fb%d: vertical blank start : %d\n", node, value); 540 svga_wcrt_multi(tm->v_blank_start_regs, value); 541 542 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; 543 value = (value * vmul) / vdiv; 544 pr_debug("fb%d: vertical blank end : %d\n", node, value); 545 svga_wcrt_multi(tm->v_blank_end_regs, value - 2); 546 547 value = var->yres + var->lower_margin; 548 value = (value * vmul) / vdiv; 549 pr_debug("fb%d: vertical sync start : %d\n", node, value); 550 svga_wcrt_multi(tm->v_sync_start_regs, value); 551 552 value = var->yres + var->lower_margin + var->vsync_len; 553 value = (value * vmul) / vdiv; 554 pr_debug("fb%d: vertical sync end : %d\n", node, value); 555 svga_wcrt_multi(tm->v_sync_end_regs, value); 556 557 /* Set horizontal and vertical sync pulse polarity in misc register */ 558 559 regval = vga_r(NULL, VGA_MIS_R); 560 if (var->sync & FB_SYNC_HOR_HIGH_ACT) { 561 pr_debug("fb%d: positive horizontal sync\n", node); 562 regval = regval & ~0x80; 563 } else { 564 pr_debug("fb%d: negative horizontal sync\n", node); 565 regval = regval | 0x80; 566 } 567 if (var->sync & FB_SYNC_VERT_HIGH_ACT) { 568 pr_debug("fb%d: positive vertical sync\n", node); 569 regval = regval & ~0x40; 570 } else { 571 pr_debug("fb%d: negative vertical sync\n\n", node); 572 regval = regval | 0x40; 573 } 574 vga_w(NULL, VGA_MIS_W, regval); 575} 576 577 578/* ------------------------------------------------------------------------- */ 579 580 581static inline int match_format(const struct svga_fb_format *frm, 582 struct fb_var_screeninfo *var) 583{ 584 int i = 0; 585 int stored = -EINVAL; 586 587 while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL) 588 { 589 if ((var->bits_per_pixel == frm->bits_per_pixel) && 590 (var->red.length <= frm->red.length) && 591 (var->green.length <= frm->green.length) && 592 (var->blue.length <= frm->blue.length) && 593 (var->transp.length <= frm->transp.length) && 594 (var->nonstd == frm->nonstd)) 595 return i; 596 if (var->bits_per_pixel == frm->bits_per_pixel) 597 stored = i; 598 i++; 599 frm++; 600 } 601 return stored; 602} 603 604int svga_match_format(const struct svga_fb_format *frm, 605 struct fb_var_screeninfo *var, 606 struct fb_fix_screeninfo *fix) 607{ 608 int i = match_format(frm, var); 609 610 if (i >= 0) { 611 var->bits_per_pixel = frm[i].bits_per_pixel; 612 var->red = frm[i].red; 613 var->green = frm[i].green; 614 var->blue = frm[i].blue; 615 var->transp = frm[i].transp; 616 var->nonstd = frm[i].nonstd; 617 if (fix != NULL) { 618 fix->type = frm[i].type; 619 fix->type_aux = frm[i].type_aux; 620 fix->visual = frm[i].visual; 621 fix->xpanstep = frm[i].xpanstep; 622 } 623 } 624 625 return i; 626} 627 628 629EXPORT_SYMBOL(svga_wcrt_multi); 630EXPORT_SYMBOL(svga_wseq_multi); 631 632EXPORT_SYMBOL(svga_set_default_gfx_regs); 633EXPORT_SYMBOL(svga_set_default_atc_regs); 634EXPORT_SYMBOL(svga_set_default_seq_regs); 635EXPORT_SYMBOL(svga_set_default_crt_regs); 636EXPORT_SYMBOL(svga_set_textmode_vga_regs); 637 638EXPORT_SYMBOL(svga_settile); 639EXPORT_SYMBOL(svga_tilecopy); 640EXPORT_SYMBOL(svga_tilefill); 641EXPORT_SYMBOL(svga_tileblit); 642EXPORT_SYMBOL(svga_tilecursor); 643EXPORT_SYMBOL(svga_get_tilemax); 644 645EXPORT_SYMBOL(svga_compute_pll); 646EXPORT_SYMBOL(svga_check_timings); 647EXPORT_SYMBOL(svga_set_timings); 648EXPORT_SYMBOL(svga_match_format); 649 650MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>"); 651MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards"); 652MODULE_LICENSE("GPL"); 653