1 /***************************************************************************\ 2|* *| 3|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *| 4|* *| 5|* NOTICE TO USER: The source code is copyrighted under U.S. and *| 6|* international laws. Users and possessors of this source code are *| 7|* hereby granted a nonexclusive, royalty-free copyright license to *| 8|* use this code in individual and commercial software. *| 9|* *| 10|* Any use of this source code must include, in the user documenta- *| 11|* tion and internal comments to the code, notices to the end user *| 12|* as follows: *| 13|* *| 14|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *| 15|* *| 16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| 17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| 18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| 19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| 20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| 21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| 22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| 23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| 24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| 25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| 26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| 27|* *| 28|* U.S. Government End Users. This source code is a "commercial *| 29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| 30|* consisting of "commercial computer software" and "commercial *| 31|* computer software documentation," as such terms are used in *| 32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| 33|* ment only as a commercial end item. Consistent with 48 C.F.R. *| 34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| 35|* all U.S. Government End Users acquire the source code with only *| 36|* those rights set forth herein. *| 37|* *| 38 \***************************************************************************/ 39 40/* 41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ 42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing 43 * where the source code is provided "as is" without warranty of any kind. 44 * The only usage restriction is for the copyright notices to be retained 45 * whenever code is used. 46 * 47 * Antonino Daplas <adaplas@pol.net> 2005-03-11 48 */ 49 50#include <video/vga.h> 51#include <linux/delay.h> 52#include <linux/pci.h> 53#include <linux/slab.h> 54#include "nv_type.h" 55#include "nv_local.h" 56#include "nv_proto.h" 57/* 58 * Override VGA I/O routines. 59 */ 60void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value) 61{ 62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); 63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); 64} 65u8 NVReadCrtc(struct nvidia_par *par, u8 index) 66{ 67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); 68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); 69} 70void NVWriteGr(struct nvidia_par *par, u8 index, u8 value) 71{ 72 VGA_WR08(par->PVIO, VGA_GFX_I, index); 73 VGA_WR08(par->PVIO, VGA_GFX_D, value); 74} 75u8 NVReadGr(struct nvidia_par *par, u8 index) 76{ 77 VGA_WR08(par->PVIO, VGA_GFX_I, index); 78 return (VGA_RD08(par->PVIO, VGA_GFX_D)); 79} 80void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value) 81{ 82 VGA_WR08(par->PVIO, VGA_SEQ_I, index); 83 VGA_WR08(par->PVIO, VGA_SEQ_D, value); 84} 85u8 NVReadSeq(struct nvidia_par *par, u8 index) 86{ 87 VGA_WR08(par->PVIO, VGA_SEQ_I, index); 88 return (VGA_RD08(par->PVIO, VGA_SEQ_D)); 89} 90void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value) 91{ 92 volatile u8 tmp; 93 94 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); 95 if (par->paletteEnabled) 96 index &= ~0x20; 97 else 98 index |= 0x20; 99 VGA_WR08(par->PCIO, VGA_ATT_IW, index); 100 VGA_WR08(par->PCIO, VGA_ATT_W, value); 101} 102u8 NVReadAttr(struct nvidia_par *par, u8 index) 103{ 104 volatile u8 tmp; 105 106 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); 107 if (par->paletteEnabled) 108 index &= ~0x20; 109 else 110 index |= 0x20; 111 VGA_WR08(par->PCIO, VGA_ATT_IW, index); 112 return (VGA_RD08(par->PCIO, VGA_ATT_R)); 113} 114void NVWriteMiscOut(struct nvidia_par *par, u8 value) 115{ 116 VGA_WR08(par->PVIO, VGA_MIS_W, value); 117} 118u8 NVReadMiscOut(struct nvidia_par *par) 119{ 120 return (VGA_RD08(par->PVIO, VGA_MIS_R)); 121} 122void NVWriteDacMask(struct nvidia_par *par, u8 value) 123{ 124 VGA_WR08(par->PDIO, VGA_PEL_MSK, value); 125} 126void NVWriteDacReadAddr(struct nvidia_par *par, u8 value) 127{ 128 VGA_WR08(par->PDIO, VGA_PEL_IR, value); 129} 130void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value) 131{ 132 VGA_WR08(par->PDIO, VGA_PEL_IW, value); 133} 134void NVWriteDacData(struct nvidia_par *par, u8 value) 135{ 136 VGA_WR08(par->PDIO, VGA_PEL_D, value); 137} 138u8 NVReadDacData(struct nvidia_par *par) 139{ 140 return (VGA_RD08(par->PDIO, VGA_PEL_D)); 141} 142 143static int NVIsConnected(struct nvidia_par *par, int output) 144{ 145 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0; 146 u32 reg52C, reg608, dac0_reg608 = 0; 147 int present; 148 149 if (output) { 150 dac0_reg608 = NV_RD32(PRAMDAC, 0x0608); 151 PRAMDAC += 0x800; 152 } 153 154 reg52C = NV_RD32(PRAMDAC, 0x052C); 155 reg608 = NV_RD32(PRAMDAC, 0x0608); 156 157 NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000); 158 159 NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE); 160 msleep(1); 161 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1); 162 163 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140); 164 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) | 165 0x00001000); 166 167 msleep(1); 168 169 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0; 170 171 if (present) 172 printk("nvidiafb: CRTC%i analog found\n", output); 173 else 174 printk("nvidiafb: CRTC%i analog not found\n", output); 175 176 if (output) 177 NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608); 178 179 NV_WR32(PRAMDAC, 0x052C, reg52C); 180 NV_WR32(PRAMDAC, 0x0608, reg608); 181 182 return present; 183} 184 185static void NVSelectHeadRegisters(struct nvidia_par *par, int head) 186{ 187 if (head) { 188 par->PCIO = par->PCIO0 + 0x2000; 189 par->PCRTC = par->PCRTC0 + 0x800; 190 par->PRAMDAC = par->PRAMDAC0 + 0x800; 191 par->PDIO = par->PDIO0 + 0x2000; 192 } else { 193 par->PCIO = par->PCIO0; 194 par->PCRTC = par->PCRTC0; 195 par->PRAMDAC = par->PRAMDAC0; 196 par->PDIO = par->PDIO0; 197 } 198} 199 200static void nv4GetConfig(struct nvidia_par *par) 201{ 202 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) { 203 par->RamAmountKBytes = 204 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 + 205 1024 * 2; 206 } else { 207 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) { 208 case 0: 209 par->RamAmountKBytes = 1024 * 32; 210 break; 211 case 1: 212 par->RamAmountKBytes = 1024 * 4; 213 break; 214 case 2: 215 par->RamAmountKBytes = 1024 * 8; 216 break; 217 case 3: 218 default: 219 par->RamAmountKBytes = 1024 * 16; 220 break; 221 } 222 } 223 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ? 224 14318 : 13500; 225 par->CURSOR = &par->PRAMIN[0x1E00]; 226 par->MinVClockFreqKHz = 12000; 227 par->MaxVClockFreqKHz = 350000; 228} 229 230static void nv10GetConfig(struct nvidia_par *par) 231{ 232 struct pci_dev *dev; 233 u32 implementation = par->Chipset & 0x0ff0; 234 235#ifdef __BIG_ENDIAN 236 /* turn on big endian register access */ 237 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { 238 NV_WR32(par->PMC, 0x0004, 0x01000001); 239 mb(); 240 } 241#endif 242 243 dev = pci_get_bus_and_slot(0, 1); 244 if ((par->Chipset & 0xffff) == 0x01a0) { 245 u32 amt; 246 247 pci_read_config_dword(dev, 0x7c, &amt); 248 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; 249 } else if ((par->Chipset & 0xffff) == 0x01f0) { 250 u32 amt; 251 252 pci_read_config_dword(dev, 0x84, &amt); 253 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; 254 } else { 255 par->RamAmountKBytes = 256 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; 257 } 258 pci_dev_put(dev); 259 260 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? 261 14318 : 13500; 262 263 if (par->twoHeads && (implementation != 0x0110)) { 264 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22)) 265 par->CrystalFreqKHz = 27000; 266 } 267 268 par->CURSOR = NULL; /* can't set this here */ 269 par->MinVClockFreqKHz = 12000; 270 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000; 271} 272 273int NVCommonSetup(struct fb_info *info) 274{ 275 struct nvidia_par *par = info->par; 276 struct fb_var_screeninfo *var; 277 u16 implementation = par->Chipset & 0x0ff0; 278 u8 *edidA = NULL, *edidB = NULL; 279 struct fb_monspecs *monitorA, *monitorB; 280 struct fb_monspecs *monA = NULL, *monB = NULL; 281 int mobile = 0; 282 int tvA = 0; 283 int tvB = 0; 284 int FlatPanel = -1; /* really means the CRTC is slaved */ 285 int Television = 0; 286 int err = 0; 287 288 var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL); 289 monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL); 290 monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL); 291 292 if (!var || !monitorA || !monitorB) { 293 err = -ENOMEM; 294 goto done; 295 } 296 297 par->PRAMIN = par->REGS + (0x00710000 / 4); 298 par->PCRTC0 = par->REGS + (0x00600000 / 4); 299 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); 300 par->PFB = par->REGS + (0x00100000 / 4); 301 par->PFIFO = par->REGS + (0x00002000 / 4); 302 par->PGRAPH = par->REGS + (0x00400000 / 4); 303 par->PEXTDEV = par->REGS + (0x00101000 / 4); 304 par->PTIMER = par->REGS + (0x00009000 / 4); 305 par->PMC = par->REGS + (0x00000000 / 4); 306 par->FIFO = par->REGS + (0x00800000 / 4); 307 308 /* 8 bit registers */ 309 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000; 310 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000; 311 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000; 312 313 par->twoHeads = (par->Architecture >= NV_ARCH_10) && 314 (implementation != 0x0100) && 315 (implementation != 0x0150) && 316 (implementation != 0x01A0) && (implementation != 0x0200); 317 318 par->fpScaler = (par->FpScale && par->twoHeads && 319 (implementation != 0x0110)); 320 321 par->twoStagePLL = (implementation == 0x0310) || 322 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40); 323 324 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) && 325 (implementation != 0x0100); 326 327 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020); 328 329 /* look for known laptop chips */ 330 switch (par->Chipset & 0xffff) { 331 case 0x0112: 332 case 0x0174: 333 case 0x0175: 334 case 0x0176: 335 case 0x0177: 336 case 0x0179: 337 case 0x017C: 338 case 0x017D: 339 case 0x0186: 340 case 0x0187: 341 case 0x018D: 342 case 0x01D7: 343 case 0x0228: 344 case 0x0286: 345 case 0x028C: 346 case 0x0316: 347 case 0x0317: 348 case 0x031A: 349 case 0x031B: 350 case 0x031C: 351 case 0x031D: 352 case 0x031E: 353 case 0x031F: 354 case 0x0324: 355 case 0x0325: 356 case 0x0328: 357 case 0x0329: 358 case 0x032C: 359 case 0x032D: 360 case 0x0347: 361 case 0x0348: 362 case 0x0349: 363 case 0x034B: 364 case 0x034C: 365 case 0x0160: 366 case 0x0166: 367 case 0x0169: 368 case 0x016B: 369 case 0x016C: 370 case 0x016D: 371 case 0x00C8: 372 case 0x00CC: 373 case 0x0144: 374 case 0x0146: 375 case 0x0147: 376 case 0x0148: 377 case 0x0098: 378 case 0x0099: 379 mobile = 1; 380 break; 381 default: 382 break; 383 } 384 385 if (par->Architecture == NV_ARCH_04) 386 nv4GetConfig(par); 387 else 388 nv10GetConfig(par); 389 390 NVSelectHeadRegisters(par, 0); 391 392 NVLockUnlock(par, 0); 393 394 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0; 395 396 par->Television = 0; 397 398 nvidia_create_i2c_busses(par); 399 if (!par->twoHeads) { 400 par->CRTCnumber = 0; 401 if (nvidia_probe_i2c_connector(info, 1, &edidA)) 402 nvidia_probe_of_connector(info, 1, &edidA); 403 if (edidA && !fb_parse_edid(edidA, var)) { 404 printk("nvidiafb: EDID found from BUS1\n"); 405 monA = monitorA; 406 fb_edid_to_monspecs(edidA, monA); 407 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0; 408 409 /* NV4 doesn't support FlatPanels */ 410 if ((par->Chipset & 0x0fff) <= 0x0020) 411 FlatPanel = 0; 412 } else { 413 VGA_WR08(par->PCIO, 0x03D4, 0x28); 414 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) { 415 VGA_WR08(par->PCIO, 0x03D4, 0x33); 416 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01)) 417 Television = 1; 418 FlatPanel = 1; 419 } else { 420 FlatPanel = 0; 421 } 422 printk("nvidiafb: HW is currently programmed for %s\n", 423 FlatPanel ? (Television ? "TV" : "DFP") : 424 "CRT"); 425 } 426 427 if (par->FlatPanel == -1) { 428 par->FlatPanel = FlatPanel; 429 par->Television = Television; 430 } else { 431 printk("nvidiafb: Forcing display type to %s as " 432 "specified\n", par->FlatPanel ? "DFP" : "CRT"); 433 } 434 } else { 435 u8 outputAfromCRTC, outputBfromCRTC; 436 int CRTCnumber = -1; 437 u8 slaved_on_A, slaved_on_B; 438 int analog_on_A, analog_on_B; 439 u32 oldhead; 440 u8 cr44; 441 442 if (implementation != 0x0110) { 443 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100) 444 outputAfromCRTC = 1; 445 else 446 outputAfromCRTC = 0; 447 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100) 448 outputBfromCRTC = 1; 449 else 450 outputBfromCRTC = 0; 451 analog_on_A = NVIsConnected(par, 0); 452 analog_on_B = NVIsConnected(par, 1); 453 } else { 454 outputAfromCRTC = 0; 455 outputBfromCRTC = 1; 456 analog_on_A = 0; 457 analog_on_B = 0; 458 } 459 460 VGA_WR08(par->PCIO, 0x03D4, 0x44); 461 cr44 = VGA_RD08(par->PCIO, 0x03D5); 462 463 VGA_WR08(par->PCIO, 0x03D5, 3); 464 NVSelectHeadRegisters(par, 1); 465 NVLockUnlock(par, 0); 466 467 VGA_WR08(par->PCIO, 0x03D4, 0x28); 468 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80; 469 if (slaved_on_B) { 470 VGA_WR08(par->PCIO, 0x03D4, 0x33); 471 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); 472 } 473 474 VGA_WR08(par->PCIO, 0x03D4, 0x44); 475 VGA_WR08(par->PCIO, 0x03D5, 0); 476 NVSelectHeadRegisters(par, 0); 477 NVLockUnlock(par, 0); 478 479 VGA_WR08(par->PCIO, 0x03D4, 0x28); 480 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80; 481 if (slaved_on_A) { 482 VGA_WR08(par->PCIO, 0x03D4, 0x33); 483 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01); 484 } 485 486 oldhead = NV_RD32(par->PCRTC0, 0x00000860); 487 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010); 488 489 if (nvidia_probe_i2c_connector(info, 1, &edidA)) 490 nvidia_probe_of_connector(info, 1, &edidA); 491 if (edidA && !fb_parse_edid(edidA, var)) { 492 printk("nvidiafb: EDID found from BUS1\n"); 493 monA = monitorA; 494 fb_edid_to_monspecs(edidA, monA); 495 } 496 497 if (nvidia_probe_i2c_connector(info, 2, &edidB)) 498 nvidia_probe_of_connector(info, 2, &edidB); 499 if (edidB && !fb_parse_edid(edidB, var)) { 500 printk("nvidiafb: EDID found from BUS2\n"); 501 monB = monitorB; 502 fb_edid_to_monspecs(edidB, monB); 503 } 504 505 if (slaved_on_A && !tvA) { 506 CRTCnumber = 0; 507 FlatPanel = 1; 508 printk("nvidiafb: CRTC 0 is currently programmed for " 509 "DFP\n"); 510 } else if (slaved_on_B && !tvB) { 511 CRTCnumber = 1; 512 FlatPanel = 1; 513 printk("nvidiafb: CRTC 1 is currently programmed " 514 "for DFP\n"); 515 } else if (analog_on_A) { 516 CRTCnumber = outputAfromCRTC; 517 FlatPanel = 0; 518 printk("nvidiafb: CRTC %i appears to have a " 519 "CRT attached\n", CRTCnumber); 520 } else if (analog_on_B) { 521 CRTCnumber = outputBfromCRTC; 522 FlatPanel = 0; 523 printk("nvidiafb: CRTC %i appears to have a " 524 "CRT attached\n", CRTCnumber); 525 } else if (slaved_on_A) { 526 CRTCnumber = 0; 527 FlatPanel = 1; 528 Television = 1; 529 printk("nvidiafb: CRTC 0 is currently programmed " 530 "for TV\n"); 531 } else if (slaved_on_B) { 532 CRTCnumber = 1; 533 FlatPanel = 1; 534 Television = 1; 535 printk("nvidiafb: CRTC 1 is currently programmed for " 536 "TV\n"); 537 } else if (monA) { 538 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0; 539 } else if (monB) { 540 FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0; 541 } 542 543 if (par->FlatPanel == -1) { 544 if (FlatPanel != -1) { 545 par->FlatPanel = FlatPanel; 546 par->Television = Television; 547 } else { 548 printk("nvidiafb: Unable to detect display " 549 "type...\n"); 550 if (mobile) { 551 printk("...On a laptop, assuming " 552 "DFP\n"); 553 par->FlatPanel = 1; 554 } else { 555 printk("...Using default of CRT\n"); 556 par->FlatPanel = 0; 557 } 558 } 559 } else { 560 printk("nvidiafb: Forcing display type to %s as " 561 "specified\n", par->FlatPanel ? "DFP" : "CRT"); 562 } 563 564 if (par->CRTCnumber == -1) { 565 if (CRTCnumber != -1) 566 par->CRTCnumber = CRTCnumber; 567 else { 568 printk("nvidiafb: Unable to detect which " 569 "CRTCNumber...\n"); 570 if (par->FlatPanel) 571 par->CRTCnumber = 1; 572 else 573 par->CRTCnumber = 0; 574 printk("...Defaulting to CRTCNumber %i\n", 575 par->CRTCnumber); 576 } 577 } else { 578 printk("nvidiafb: Forcing CRTCNumber %i as " 579 "specified\n", par->CRTCnumber); 580 } 581 582 if (monA) { 583 if (((monA->input & FB_DISP_DDI) && 584 par->FlatPanel) || 585 ((!(monA->input & FB_DISP_DDI)) && 586 !par->FlatPanel)) { 587 if (monB) { 588 fb_destroy_modedb(monB->modedb); 589 monB = NULL; 590 } 591 } else { 592 fb_destroy_modedb(monA->modedb); 593 monA = NULL; 594 } 595 } 596 597 if (monB) { 598 if (((monB->input & FB_DISP_DDI) && 599 !par->FlatPanel) || 600 ((!(monB->input & FB_DISP_DDI)) && 601 par->FlatPanel)) { 602 fb_destroy_modedb(monB->modedb); 603 monB = NULL; 604 } else 605 monA = monB; 606 } 607 608 if (implementation == 0x0110) 609 cr44 = par->CRTCnumber * 0x3; 610 611 NV_WR32(par->PCRTC0, 0x00000860, oldhead); 612 613 VGA_WR08(par->PCIO, 0x03D4, 0x44); 614 VGA_WR08(par->PCIO, 0x03D5, cr44); 615 NVSelectHeadRegisters(par, par->CRTCnumber); 616 } 617 618 printk("nvidiafb: Using %s on CRTC %i\n", 619 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT", 620 par->CRTCnumber); 621 622 if (par->FlatPanel && !par->Television) { 623 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1; 624 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1; 625 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033; 626 627 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight); 628 } 629 630 if (monA) 631 info->monspecs = *monA; 632 633 if (!par->FlatPanel || !par->twoHeads) 634 par->FPDither = 0; 635 636 par->LVDS = 0; 637 if (par->FlatPanel && par->twoHeads) { 638 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004); 639 if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1) 640 par->LVDS = 1; 641 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS"); 642 } 643 644 kfree(edidA); 645 kfree(edidB); 646done: 647 kfree(var); 648 kfree(monitorA); 649 kfree(monitorB); 650 return err; 651} 652