1#include "vgatypes.h" 2 3#include <linux/version.h> 4#include <linux/types.h> 5#include <linux/delay.h> /* udelay */ 6#include "XGIfb.h" 7 8#include "vb_def.h" 9#include "vb_struct.h" 10#include "vb_util.h" 11#include "vb_setmode.h" 12#include "vb_init.h" 13#include "vb_ext.h" 14 15 16#include <asm/io.h> 17 18 19 20 21unsigned char XGINew_ChannelAB, XGINew_DataBusWidth; 22 23unsigned short XGINew_DRAMType[17][5] = { 24 {0x0C, 0x0A, 0x02, 0x40, 0x39}, {0x0D, 0x0A, 0x01, 0x40, 0x48}, 25 {0x0C, 0x09, 0x02, 0x20, 0x35}, {0x0D, 0x09, 0x01, 0x20, 0x44}, 26 {0x0C, 0x08, 0x02, 0x10, 0x31}, {0x0D, 0x08, 0x01, 0x10, 0x40}, 27 {0x0C, 0x0A, 0x01, 0x20, 0x34}, {0x0C, 0x09, 0x01, 0x08, 0x32}, 28 {0x0B, 0x08, 0x02, 0x08, 0x21}, {0x0C, 0x08, 0x01, 0x08, 0x30}, 29 {0x0A, 0x08, 0x02, 0x04, 0x11}, {0x0B, 0x0A, 0x01, 0x10, 0x28}, 30 {0x09, 0x08, 0x02, 0x02, 0x01}, {0x0B, 0x09, 0x01, 0x08, 0x24}, 31 {0x0B, 0x08, 0x01, 0x04, 0x20}, {0x0A, 0x08, 0x01, 0x02, 0x10}, 32 {0x09, 0x08, 0x01, 0x01, 0x00} }; 33 34unsigned short XGINew_SDRDRAM_TYPE[13][5] = { 35 { 2, 12, 9, 64, 0x35}, 36 { 1, 13, 9, 64, 0x44}, 37 { 2, 12, 8, 32, 0x31}, 38 { 2, 11, 9, 32, 0x25}, 39 { 1, 12, 9, 32, 0x34}, 40 { 1, 13, 8, 32, 0x40}, 41 { 2, 11, 8, 16, 0x21}, 42 { 1, 12, 8, 16, 0x30}, 43 { 1, 11, 9, 16, 0x24}, 44 { 1, 11, 8, 8, 0x20}, 45 { 2, 9, 8, 4, 0x01}, 46 { 1, 10, 8, 4, 0x10}, 47 { 1, 9, 8, 2, 0x00} }; 48 49unsigned short XGINew_DDRDRAM_TYPE[4][5] = { 50 { 2, 12, 9, 64, 0x35}, 51 { 2, 12, 8, 32, 0x31}, 52 { 2, 11, 8, 16, 0x21}, 53 { 2, 9, 8, 4, 0x01} }; 54 55unsigned short XGINew_DDRDRAM_TYPE340[4][5] = { 56 { 2, 13, 9, 64, 0x45}, 57 { 2, 12, 9, 32, 0x35}, 58 { 2, 12, 8, 16, 0x31}, 59 { 2, 11, 8, 8, 0x21} }; 60 61unsigned short XGINew_DDRDRAM_TYPE20[12][5] = { 62 { 2, 14, 11, 128, 0x5D}, 63 { 2, 14, 10, 64, 0x59}, 64 { 2, 13, 11, 64, 0x4D}, 65 { 2, 14, 9, 32, 0x55}, 66 { 2, 13, 10, 32, 0x49}, 67 { 2, 12, 11, 32, 0x3D}, 68 { 2, 14, 8, 16, 0x51}, 69 { 2, 13, 9, 16, 0x45}, 70 { 2, 12, 10, 16, 0x39}, 71 { 2, 13, 8, 8, 0x41}, 72 { 2, 12, 9, 8, 0x35}, 73 { 2, 12, 8, 4, 0x31} }; 74 75void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *, struct vb_device_info *); 76void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *, struct vb_device_info *); 77void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *); 78void XGINew_SetDRAMModeRegister(struct vb_device_info *); 79void XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension); 80void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension, 81 unsigned long, struct vb_device_info *); 82unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension, 83 struct vb_device_info *pVBInfo); 84unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension); 85 86int XGINew_DDRSizing340(struct xgi_hw_device_info *, struct vb_device_info *); 87void XGINew_DisableRefresh(struct xgi_hw_device_info *, struct vb_device_info *) ; 88void XGINew_CheckBusWidth_310(struct vb_device_info *) ; 89int XGINew_SDRSizing(struct vb_device_info *); 90int XGINew_DDRSizing(struct vb_device_info *); 91void XGINew_EnableRefresh(struct xgi_hw_device_info *, struct vb_device_info *); 92int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/ 93unsigned long UNIROM; /* UNIROM */ 94unsigned char ChkLFB(struct vb_device_info *); 95void XGINew_Delay15us(unsigned long); 96void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension, 97 unsigned long XGI_P3d4Port); 98void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo); 99void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo); 100void XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension); 101void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension); 102void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ; 103void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ; 104void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ; 105unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo); 106void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ; 107unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo); 108 109void DelayUS(unsigned long MicroSeconds) 110{ 111 udelay(MicroSeconds); 112} 113 114 115/* --------------------------------------------------------------------- */ 116/* Function : XGIInitNew */ 117/* Input : */ 118/* Output : */ 119/* Description : */ 120/* --------------------------------------------------------------------- */ 121unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension) 122{ 123 124 struct vb_device_info VBINF; 125 struct vb_device_info *pVBInfo = &VBINF; 126 unsigned char i, temp = 0, temp1 ; 127 // VBIOSVersion[ 5 ] ; 128 volatile unsigned char *pVideoMemory; 129 130 /* unsigned long j, k ; */ 131 132 struct XGI_DSReg *pSR ; 133 134 unsigned long Temp ; 135 136 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 137 138 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 139 140 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ; 141 142 pVideoMemory = (unsigned char *)pVBInfo->ROMAddr; 143 144 145// Newdebugcode( 0x99 ) ; 146 147 148 /* if ( pVBInfo->ROMAddr == 0 ) */ 149 /* return( 0 ) ; */ 150 151 if (pVBInfo->FBAddr == 0) { 152 printk("\n pVBInfo->FBAddr == 0 "); 153 return 0; 154 } 155printk("1"); 156if (pVBInfo->BaseAddr == 0) { 157 printk("\npVBInfo->BaseAddr == 0 "); 158 return 0; 159} 160printk("2"); 161 162 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */ 163 164 pVBInfo->ISXPDOS = 0 ; 165printk("3"); 166 167if ( !HwDeviceExtension->bIntegratedMMEnabled ) 168 return 0; /* alan */ 169 170printk("4"); 171 172 // VBIOSVersion[ 4 ] = 0x0 ; 173 174 /* 09/07/99 modify by domao */ 175 176 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 177 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 178 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 179 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 180 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 181 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 182 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 183 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 184 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 185 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 186 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 187 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 188 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 189 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 190 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 191 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 192 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 193printk("5"); 194 195 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */ 196 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */ 197 198 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ; 199 200 /* ReadVBIOSData */ 201 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 202 203 /* 1.Openkey */ 204 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ; 205printk("6"); 206 207 /* GetXG21Sense (GPIO) */ 208 if ( HwDeviceExtension->jChipType == XG21 ) 209 { 210 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ; 211 } 212 if ( HwDeviceExtension->jChipType == XG27 ) 213 { 214 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ; 215 } 216printk("7"); 217 218 /* 2.Reset Extended register */ 219 220 for( i = 0x06 ; i < 0x20 ; i++ ) 221 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; 222 223 for( i = 0x21 ; i <= 0x27 ; i++ ) 224 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; 225 226 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */ 227 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */ 228 229printk("8"); 230 231 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40)) 232 { 233 for( i = 0x31 ; i <= 0x3B ; i++ ) 234 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; 235 } 236 else 237 { 238 for( i = 0x31 ; i <= 0x3D ; i++ ) 239 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; 240 } 241printk("9"); 242 243 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */ 244 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ; 245 246 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */ 247 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */ 248 249 for( i = 0x79 ; i <= 0x7C ; i++ ) 250 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */ 251 252printk("10"); 253 254 if ( HwDeviceExtension->jChipType >= XG20 ) 255 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; 256 257 /* 3.SetMemoryClock 258 259 if ( HwDeviceExtension->jChipType >= XG40 ) 260 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ; 261 262 if ( HwDeviceExtension->jChipType < XG40 ) 263 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */ 264 265printk("11"); 266 267 /* 4.SetDefExt1Regs begin */ 268 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ; 269 if ( HwDeviceExtension->jChipType == XG27 ) 270 { 271 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ; 272 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ; 273 } 274 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ; 275 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ; 276 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */ 277 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */ 278 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */ 279 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */ 280 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ; 281 282 /* SR11 = 0x0F ; */ 283 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */ 284 285printk("12"); 286 287 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */ 288 { 289// /* Set AGP Rate */ 290// temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ; 291// temp1 &= 0x02 ; 292// if ( temp1 == 0x02 ) 293// { 294// XGINew_SetReg4( 0xcf8 , 0x80000000 ) ; 295// ChipsetID = XGINew_GetReg3( 0x0cfc ) ; 296// XGINew_SetReg4( 0xcf8 , 0x8000002C ) ; 297// VendorID = XGINew_GetReg3( 0x0cfc ) ; 298// VendorID &= 0x0000FFFF ; 299// XGINew_SetReg4( 0xcf8 , 0x8001002C ) ; 300// GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ; 301// GraphicVendorID &= 0x0000FFFF; 302// 303// if ( ChipsetID == 0x7301039 ) 304/// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ; 305// 306// ChipsetID &= 0x0000FFFF ; 307/// 308// if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) ) 309// { 310// if ( ChipsetID == 0x1106 ) 311// { 312// if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) ) 313// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ; 314// else 315// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ; 316// } 317// else 318// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ; 319// } 320// } 321 322printk("13"); 323 324 if ( HwDeviceExtension->jChipType >= XG40 ) 325 { 326 /* Set AGP customize registers (in SetDefAGPRegs) Start */ 327 for( i = 0x47 ; i <= 0x4C ; i++ ) 328 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ; 329 330 for( i = 0x70 ; i <= 0x71 ; i++ ) 331 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ; 332 333 for( i = 0x74 ; i <= 0x77 ; i++ ) 334 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ; 335 /* Set AGP customize registers (in SetDefAGPRegs) End */ 336 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */ 337// XGINew_SetReg4( 0xcf8 , 0x80000000 ) ; 338// ChipsetID = XGINew_GetReg3( 0x0cfc ) ; 339// if ( ChipsetID == 0x25308086 ) 340// XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ; 341 342 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */ 343 Temp >>= 20 ; 344 Temp &= 0xF ; 345 346 if ( Temp == 1 ) 347 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */ 348 } 349printk("14"); 350 351 if ( HwDeviceExtension->jChipType < XG40 ) 352 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ; 353 } /* != XG20 */ 354 355 /* Set PCI */ 356 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ; 357 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ; 358 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ; 359printk("15"); 360 361 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */ 362 { 363 /* Set VB */ 364 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ; 365 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */ 366 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ; 367 temp1 = (unsigned char)XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */ 368 temp = (unsigned char)((temp1 >> 4) & 0x0F); 369 370 371 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ; 372 373printk("16"); 374 375 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */ 376 } /* != XG20 */ 377 378 379 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ; 380 381 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */ 382 { 383 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ; 384 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ; 385 } 386 else 387 { 388 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ; 389 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ; 390 } 391 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ; 392printk("17"); 393 394/* 395 if ( HwDeviceExtension->jChipType >= XG40 ) 396 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */ 397 398 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */ 399 { 400 if ( XGI_BridgeIsOn( pVBInfo ) == 1 ) 401 { 402 if ( pVBInfo->IF_DEF_LVDS == 0 ) 403 { 404 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ; 405 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ; 406 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ; 407 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ; 408 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ; 409 } 410 411 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ; 412 } 413 } /* != XG20 */ 414printk("18"); 415 416 if ( HwDeviceExtension->jChipType < XG40 ) 417 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ; 418printk("181"); 419 420if (HwDeviceExtension->bSkipSense == 0) { 421 printk("182"); 422 423 XGI_SenseCRT1(pVBInfo) ; 424 425 printk("183"); 426 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */ 427 pVBInfo->IF_DEF_CH7007 = 0; 428 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) ) 429 { 430printk("184"); 431 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */ 432printk("185"); 433 434 } 435 if ( HwDeviceExtension->jChipType == XG21 ) 436 { 437printk("186"); 438 439 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */ 440 temp = GetXG21FPBits( pVBInfo ) ; 441 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ; 442printk("187"); 443 444 } 445 if ( HwDeviceExtension->jChipType == XG27 ) 446 { 447 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */ 448 temp = GetXG27FPBits( pVBInfo ) ; 449 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ; 450 } 451 } 452printk("19"); 453 454 if ( HwDeviceExtension->jChipType >= XG40 ) 455 { 456 if ( HwDeviceExtension->jChipType >= XG40 ) 457 { 458 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 459 } 460 461 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ; 462 463 if (HwDeviceExtension->bSkipDramSizing == 1) { 464 pSR = HwDeviceExtension->pSR ; 465 if ( pSR!=NULL ) 466 { 467 while( pSR->jIdx != 0xFF ) 468 { 469 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ; 470 pSR++ ; 471 } 472 } 473 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 474 } /* SkipDramSizing */ 475 else 476 { 477{ 478printk("20"); 479 480 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ; 481} 482printk("21"); 483 484 } 485 } /* XG40 */ 486 487printk("22"); 488 489 490 /* SetDefExt2Regs begin */ 491/* 492 AGP = 1 ; 493 temp =(unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x3A) ; 494 temp &= 0x30 ; 495 if ( temp == 0x30 ) 496 AGP = 0 ; 497 498 if ( AGP == 0 ) 499 *pVBInfo->pSR21 &= 0xEF ; 500 501 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ; 502 if ( AGP == 1 ) 503 *pVBInfo->pSR22 &= 0x20 ; 504 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ; 505*/ 506 507// base = 0x80000000 ; 508// OutPortLong( 0xcf8 , base ) ; 509// Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ; 510// if ( Temp == 0x1039 ) 511// { 512 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char)((*pVBInfo->pSR22) & 0xFE)); 513// } 514// else 515// { 516// XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ; 517// } 518 519 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ; 520 521printk("23"); 522 523 524 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ; 525 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ; 526 527printk("24"); 528 529 530XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87); 531XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31); 532printk("25"); 533 534return 1; 535} /* end of init */ 536 537 538 539 540 541/* ============== alan ====================== */ 542 543/* --------------------------------------------------------------------- */ 544/* Function : XGINew_GetXG20DRAMType */ 545/* Input : */ 546/* Output : */ 547/* Description : */ 548/* --------------------------------------------------------------------- */ 549unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension, 550 struct vb_device_info *pVBInfo) 551{ 552 unsigned char data, temp; 553 554 if ( HwDeviceExtension->jChipType < XG20 ) 555 { 556 if ( *pVBInfo->pSoftSetting & SoftDRAMType ) 557 { 558 data = *pVBInfo->pSoftSetting & 0x07 ; 559 return( data ) ; 560 } 561 else 562 { 563 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ; 564 565 if ( data == 0 ) 566 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ; 567 568 return( data ) ; 569 } 570 } 571 else if ( HwDeviceExtension->jChipType == XG27 ) 572 { 573 if ( *pVBInfo->pSoftSetting & SoftDRAMType ) 574 { 575 data = *pVBInfo->pSoftSetting & 0x07 ; 576 return( data ) ; 577 } 578 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ; 579 580 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */ 581 data = 0 ; /*DDR*/ 582 else 583 data = 1 ; /*DDRII*/ 584 return( data ) ; 585 } 586 else if ( HwDeviceExtension->jChipType == XG21 ) 587 { 588 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */ 589 DelayUS(800); 590 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */ 591 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */ 592// HOTPLUG_SUPPORT 593// for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily 594 if ( temp & 0x01 ) /* DVI read GPIOH */ 595 data = 1 ; /*DDRII*/ 596 else 597 data = 0 ; /*DDR*/ 598//~HOTPLUG_SUPPORT 599 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ; 600 return( data ) ; 601 } 602 else 603 { 604 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ; 605 606 if ( data == 1 ) 607 data ++ ; 608 609 return( data ); 610 } 611} 612 613 614/* --------------------------------------------------------------------- */ 615/* Function : XGINew_Get310DRAMType */ 616/* Input : */ 617/* Output : */ 618/* Description : */ 619/* --------------------------------------------------------------------- */ 620unsigned char XGINew_Get310DRAMType(struct vb_device_info *pVBInfo) 621{ 622 unsigned char data ; 623 624 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */ 625 /* index &= 07 ; */ 626 627 if ( *pVBInfo->pSoftSetting & SoftDRAMType ) 628 data = *pVBInfo->pSoftSetting & 0x03 ; 629 else 630 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ; 631 632 return( data ) ; 633} 634 635 636 637/* --------------------------------------------------------------------- */ 638/* Function : XGINew_Delay15us */ 639/* Input : */ 640/* Output : */ 641/* Description : */ 642/* --------------------------------------------------------------------- */ 643/* 644void XGINew_Delay15us(unsigned long ulMicrsoSec) 645{ 646} 647*/ 648 649 650/* --------------------------------------------------------------------- */ 651/* Function : XGINew_SDR_MRS */ 652/* Input : */ 653/* Output : */ 654/* Description : */ 655/* --------------------------------------------------------------------- */ 656void XGINew_SDR_MRS(struct vb_device_info *pVBInfo) 657{ 658 unsigned short data ; 659 660 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; 661 data &= 0x3F ; /* SR16 D7=0,D6=0 */ 662 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */ 663 /* XGINew_Delay15us( 0x100 ) ; */ 664 data |= 0x80 ; /* SR16 D7=1,D6=0 */ 665 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */ 666 /* XGINew_Delay15us( 0x100 ) ; */ 667} 668 669 670/* --------------------------------------------------------------------- */ 671/* Function : XGINew_DDR1x_MRS_340 */ 672/* Input : */ 673/* Output : */ 674/* Description : */ 675/* --------------------------------------------------------------------- */ 676void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo) 677{ 678 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ; 679 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ; 680 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 681 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 682 683 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */ 684 { 685 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */ 686 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; 687 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ; 688 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 689 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 690 } 691 692 DelayUS( 60 ) ; 693 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 694 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ; 695 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ; 696 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ; 697 DelayUS( 1000 ) ; 698 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; 699 DelayUS( 500 ) ; 700 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 701 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ; 702 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ; 703 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ; 704 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; 705} 706 707 708/* --------------------------------------------------------------------- */ 709/* Function : XGINew_DDR2x_MRS_340 */ 710/* Input : */ 711/* Output : */ 712/* Description : */ 713/* --------------------------------------------------------------------- */ 714void XGINew_DDR2x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo) 715{ 716 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; 717 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ; 718 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 719 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 720 DelayUS( 60 ) ; 721 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 722 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */ 723 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ; 724 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ; 725 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ; 726 DelayUS( 1000 ) ; 727 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; 728 DelayUS( 500 ) ; 729 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */ 730 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 731 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ; 732 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ; 733 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ; 734 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; 735} 736 737/* --------------------------------------------------------------------- */ 738/* Function : XGINew_DDRII_Bootup_XG27 */ 739/* Input : */ 740/* Output : */ 741/* Description : */ 742/* --------------------------------------------------------------------- */ 743void XGINew_DDRII_Bootup_XG27(struct xgi_hw_device_info *HwDeviceExtension, 744 unsigned long P3c4, struct vb_device_info *pVBInfo) 745{ 746 unsigned long P3d4 = P3c4 + 0x10 ; 747 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 748 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 749 750 /* Set Double Frequency */ 751 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */ 752 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */ 753 754 DelayUS( 200 ) ; 755 756 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2 757 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */ 758 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 759 DelayUS( 15 ) ; 760 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 761 DelayUS( 15 ) ; 762 763 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3 764 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */ 765 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 766 DelayUS( 15 ) ; 767 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 768 DelayUS( 15) ; 769 770 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1 771 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */ 772 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 773 DelayUS( 30 ) ; 774 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 775 DelayUS( 15 ) ; 776 777 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable 778 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */ 779 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 780 DelayUS( 30 ) ; 781 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 782 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */ 783 /* DelayUS( 15 ) ; */ 784 785 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */ 786 DelayUS( 60 ) ; 787 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */ 788 789 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset 790 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */ 791 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 792 793 DelayUS( 30 ) ; 794 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */ 795 DelayUS( 15 ) ; 796 797 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT 798 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */ 799 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 800 DelayUS( 30 ) ; 801 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 802 DelayUS( 15 ) ; 803 804 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS 805 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */ 806 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 807 DelayUS( 30 ) ; 808 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 809 DelayUS( 15 ) ; 810 811 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */ 812 DelayUS( 200 ) ; 813 814 815} 816/* --------------------------------------------------------------------- */ 817/* Function : XGINew_DDR2_MRS_XG20 */ 818/* Input : */ 819/* Output : */ 820/* Description : */ 821/* --------------------------------------------------------------------- */ 822void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension, 823 unsigned long P3c4, struct vb_device_info *pVBInfo) 824{ 825 unsigned long P3d4 = P3c4 + 0x10 ; 826 827 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 828 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 829 830 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */ 831 832 DelayUS( 200 ) ; 833 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */ 834 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; 835 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ; 836 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ; 837 838 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */ 839 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; 840 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ; 841 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ; 842 843 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */ 844 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; 845 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ; 846 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ; 847 848 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */ 849 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 850 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ; 851 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ; 852 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ; 853 854 DelayUS( 15 ) ; 855 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 856 DelayUS( 30 ) ; 857 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */ 858 DelayUS( 100 ) ; 859 860 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */ 861 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 862 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ; 863 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ; 864 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ; 865 866 DelayUS( 200 ) ; 867} 868 869/* --------------------------------------------------------------------- */ 870/* Function : XGINew_DDR2_MRS_XG20 */ 871/* Input : */ 872/* Output : */ 873/* Description : */ 874/* --------------------------------------------------------------------- */ 875void XGINew_DDR2_MRS_XG27(struct xgi_hw_device_info *HwDeviceExtension, 876 unsigned long P3c4, struct vb_device_info *pVBInfo) 877{ 878 unsigned long P3d4 = P3c4 + 0x10 ; 879 880 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 881 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 882 883 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */ 884 DelayUS( 200 ) ; 885 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */ 886 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; 887 888 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ; 889 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable 890 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ; 891 892 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */ 893 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; 894 895 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 896 DelayUS( 15 ) ; ////06/11/22 XG27 A0 897 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 898 899 900 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */ 901 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; 902 903 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 904 DelayUS( 15 ) ; ////06/11/22 XG27 A0 905 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 906 907 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 908 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM 909 910 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 911 DelayUS( 15 ) ; ////06/11/23 XG27 A0 912 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 913 914 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge 915 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 916 DelayUS( 60 ) ; 917 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */ 918 919 920 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 921 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM 922 923 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 924 DelayUS( 30 ) ; 925 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 926 927 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON 928 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ); 929 930 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 931 DelayUS( 30 ) ; 932 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 933 934 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ); 935 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ); 936 937 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 938 DelayUS( 30 ) ; 939 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 940 941 DelayUS( 15 ) ; ////Start Auto-PreCharge 942 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 943 DelayUS( 200 ) ; 944 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */ 945 946} 947 948/* --------------------------------------------------------------------- */ 949/* Function : XGINew_DDR1x_DefaultRegister */ 950/* Input : */ 951/* Output : */ 952/* Description : */ 953/* --------------------------------------------------------------------- */ 954void XGINew_DDR1x_DefaultRegister(struct xgi_hw_device_info *HwDeviceExtension, 955 unsigned long Port, struct vb_device_info *pVBInfo) 956{ 957 unsigned long P3d4 = Port , 958 P3c4 = Port - 0x10 ; 959 960 if ( HwDeviceExtension->jChipType >= XG20 ) 961 { 962 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 963 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 964 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 965 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 966 967 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ; 968 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ; 969 970 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ; 971 } 972 else 973 { 974 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 975 976 switch( HwDeviceExtension->jChipType ) 977 { 978 case XG41: 979 case XG42: 980 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 981 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 982 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 983 break ; 984 default: 985 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ; 986 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ; 987 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */ 988 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ; 989 XGINew_GetReg1( P3d4 , 0x86 ) ; 990 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; 991 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ; 992 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ; 993 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */ 994 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ; 995 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */ 996 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 997 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 998 break ; 999 } 1000 1001 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ; 1002 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ; 1003 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ; 1004 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ; 1005 } 1006} 1007 1008 1009/* --------------------------------------------------------------------- */ 1010/* Function : XGINew_DDR2x_DefaultRegister */ 1011/* Input : */ 1012/* Output : */ 1013/* Description : */ 1014/* --------------------------------------------------------------------- */ 1015void XGINew_DDR2x_DefaultRegister(struct xgi_hw_device_info *HwDeviceExtension, 1016 unsigned long Port, struct vb_device_info *pVBInfo) 1017{ 1018 unsigned long P3d4 = Port , 1019 P3c4 = Port - 0x10 ; 1020 1021 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1022 1023 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */ 1024 switch( HwDeviceExtension->jChipType ) 1025 { 1026 case XG41: 1027 case XG42: 1028 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1029 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1030 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1031 break ; 1032 default: 1033 /* keep following setting sequence, each setting in the same reg insert idle */ 1034 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ; 1035 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ; 1036 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */ 1037 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ; 1038 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ; 1039 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ; 1040 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */ 1041 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ; 1042 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */ 1043 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1044 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1045 } 1046 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; 1047 if ( HwDeviceExtension->jChipType == XG42 ) 1048 { 1049 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ; 1050 } 1051 else 1052 { 1053 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ; 1054 } 1055 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ; 1056 1057 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ; 1058} 1059 1060 1061/* --------------------------------------------------------------------- */ 1062/* Function : XGINew_DDR2_DefaultRegister */ 1063/* Input : */ 1064/* Output : */ 1065/* Description : */ 1066/* --------------------------------------------------------------------- */ 1067void XGINew_DDR2_DefaultRegister(struct xgi_hw_device_info *HwDeviceExtension, 1068 unsigned long Port, struct vb_device_info *pVBInfo) 1069{ 1070 unsigned long P3d4 = Port , 1071 P3c4 = Port - 0x10 ; 1072 1073 /* keep following setting sequence, each setting in the same reg insert idle */ 1074 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ; 1075 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ; 1076 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */ 1077 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ; 1078 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */ 1079 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1080 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ; 1081 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ; 1082 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */ 1083 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ; 1084 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */ 1085 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1086 if ( HwDeviceExtension->jChipType == XG27 ) 1087 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1088 else 1089 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */ 1090 1091 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ; 1092 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ; 1093 if ( HwDeviceExtension->jChipType == XG27 ) 1094 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ; 1095 else 1096 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ; 1097} 1098 1099 1100/* --------------------------------------------------------------------- */ 1101/* Function : XGINew_SetDRAMDefaultRegister340 */ 1102/* Input : */ 1103/* Output : */ 1104/* Description : */ 1105/* --------------------------------------------------------------------- */ 1106void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension, 1107 unsigned long Port, struct vb_device_info *pVBInfo) 1108{ 1109 unsigned char temp, temp1, temp2, temp3 , 1110 i , j , k ; 1111 1112 unsigned long P3d4 = Port , 1113 P3c4 = Port - 0x10 ; 1114 1115 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ; 1116 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ; 1117 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ; 1118 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ; 1119 1120 temp2 = 0 ; 1121 for( i = 0 ; i < 4 ; i++ ) 1122 { 1123 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */ 1124 for( j = 0 ; j < 4 ; j++ ) 1125 { 1126 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ; 1127 temp2 |= temp1 ; 1128 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ; 1129 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */ 1130 temp2 &= 0xF0 ; 1131 temp2 += 0x10 ; 1132 } 1133 } 1134 1135 temp2 = 0 ; 1136 for( i = 0 ; i < 4 ; i++ ) 1137 { 1138 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */ 1139 for( j = 0 ; j < 4 ; j++ ) 1140 { 1141 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ; 1142 temp2 |= temp1 ; 1143 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ; 1144 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */ 1145 temp2 &= 0xF0 ; 1146 temp2 += 0x10 ; 1147 } 1148 } 1149 1150 temp3 = 0 ; 1151 for( k = 0 ; k < 4 ; k++ ) 1152 { 1153 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */ 1154 temp2 = 0 ; 1155 for( i = 0 ; i < 8 ; i++ ) 1156 { 1157 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */ 1158 for( j = 0 ; j < 4 ; j++ ) 1159 { 1160 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ; 1161 temp2 |= temp1 ; 1162 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ; 1163 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */ 1164 temp2 &= 0xF8 ; 1165 temp2 += 0x08 ; 1166 } 1167 } 1168 temp3 += 0x01 ; 1169 } 1170 1171 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */ 1172 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */ 1173 1174 temp2 = 0x80 ; 1175 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */ 1176 for( j = 0 ; j < 4 ; j++ ) 1177 { 1178 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ; 1179 temp2 |= temp1 ; 1180 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ; 1181 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */ 1182 temp2 &= 0xF0 ; 1183 temp2 += 0x10 ; 1184 } 1185 1186 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ; 1187 temp1 = temp & 0x03 ; 1188 temp2 |= temp1 ; 1189 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ; 1190 1191 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ; 1192 temp1 = temp & 0x0F ; 1193 temp2 = ( temp >> 4 ) & 0x07 ; 1194 temp3 = temp & 0x80 ; 1195 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */ 1196 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */ 1197 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */ 1198 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */ 1199 1200 if ( HwDeviceExtension->jChipType == XG27 ) 1201 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */ 1202 1203 for( j = 0 ; j <= 6 ; j++ ) 1204 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */ 1205 1206 for( j = 0 ; j <= 2 ; j++ ) 1207 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */ 1208 1209 for( j = 0 ; j < 2 ; j++ ) 1210 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */ 1211 1212 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) ) 1213 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ; 1214 1215 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */ 1216 1217 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */ 1218 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */ 1219 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */ 1220 if ( XGINew_RAMType ) 1221 { 1222 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */ 1223 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */ 1224 if ( HwDeviceExtension->jChipType == XG27 ) 1225 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */ 1226 1227 } 1228 else 1229 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */ 1230 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */ 1231 1232 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ; 1233 if( temp == 0 ) 1234 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1235 else 1236 { 1237 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */ 1238 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1239 } 1240 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 1241} 1242 1243 1244/* --------------------------------------------------------------------- */ 1245/* Function : XGINew_DDR_MRS */ 1246/* Input : */ 1247/* Output : */ 1248/* Description : */ 1249/* --------------------------------------------------------------------- */ 1250void XGINew_DDR_MRS(struct vb_device_info *pVBInfo) 1251{ 1252 unsigned short data ; 1253 1254 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr; 1255 1256 /* SR16 <- 1F,DF,2F,AF */ 1257 /* yriver modified SR16 <- 0F,DF,0F,AF */ 1258 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */ 1259 data = pVideoMemory[ 0xFB ] ; 1260 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */ 1261 1262 data &= 0x0F ; 1263 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; 1264 data |= 0xC0 ; 1265 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; 1266 data &= 0x0F ; 1267 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; 1268 data |= 0x80 ; 1269 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; 1270 data &= 0x0F ; 1271 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; 1272 data |= 0xD0 ; 1273 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; 1274 data &= 0x0F ; 1275 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; 1276 data |= 0xA0 ; 1277 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; 1278/* 1279 else { 1280 data &= 0x0F; 1281 data |= 0x10; 1282 XGINew_SetReg1(pVBInfo->P3c4,0x16,data); 1283 1284 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) 1285 { 1286 data &= 0x0F; 1287 } 1288 1289 data |= 0xC0; 1290 XGINew_SetReg1(pVBInfo->P3c4,0x16,data); 1291 1292 1293 data &= 0x0F; 1294 data |= 0x20; 1295 XGINew_SetReg1(pVBInfo->P3c4,0x16,data); 1296 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) 1297 { 1298 data &= 0x0F; 1299 } 1300 1301 data |= 0x80; 1302 XGINew_SetReg1(pVBInfo->P3c4,0x16,data); 1303 } 1304*/ 1305} 1306 1307 1308/* check if read cache pointer is correct */ 1309 1310 1311 1312/* --------------------------------------------------------------------- */ 1313/* Function : XGINew_VerifyMclk */ 1314/* Input : */ 1315/* Output : */ 1316/* Description : */ 1317/* --------------------------------------------------------------------- */ 1318void XGINew_VerifyMclk(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 1319{ 1320 unsigned char *pVideoMemory = pVBInfo->FBAddr ; 1321 unsigned char i, j ; 1322 unsigned short Temp , SR21 ; 1323 1324 pVideoMemory[ 0 ] = 0xaa ; /* alan */ 1325 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */ 1326 1327 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) ) 1328 { 1329 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 ) 1330 { 1331 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ; 1332 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */ 1333 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ; 1334 1335 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ; 1336 Temp |= 0x01 ; /* MCLK reset */ 1337 1338 1339 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ; 1340 Temp &= 0xFE ; /* MCLK normal operation */ 1341 1342 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ; 1343 1344 pVideoMemory[ 16 + j ] = j ; 1345 if ( pVideoMemory[ 16 + j ] == j ) 1346 { 1347 pVideoMemory[ j ] = j ; 1348 break ; 1349 } 1350 } 1351 } 1352} 1353 1354 1355 1356 1357 1358/* --------------------------------------------------------------------- */ 1359/* Function : XGINew_SetDRAMSize_340 */ 1360/* Input : */ 1361/* Output : */ 1362/* Description : */ 1363/* --------------------------------------------------------------------- */ 1364void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 1365{ 1366 unsigned short data ; 1367 1368 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 1369 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 1370 1371 XGISetModeNew( HwDeviceExtension , 0x2e ) ; 1372 1373 1374 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ; 1375 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */ 1376 XGI_DisplayOff( HwDeviceExtension, pVBInfo ); 1377 1378 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/ 1379 /*data |= 0x20 ;*/ 1380 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */ 1381 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ; 1382 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ; 1383 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */ 1384} 1385 1386 1387/* --------------------------------------------------------------------- */ 1388/* Function : */ 1389/* Input : */ 1390/* Output : */ 1391/* Description : */ 1392/* --------------------------------------------------------------------- */ 1393void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 1394{ 1395 unsigned short data ; 1396 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase , 1397 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 1398#ifdef XGI301 1399 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */ 1400#endif 1401 1402#ifdef XGI302 /* alan,should change value */ 1403 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ; 1404 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ; 1405 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ; 1406#endif 1407 1408 XGISetModeNew( HwDeviceExtension , 0x2e ) ; 1409 1410 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ; 1411 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */ 1412 1413 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ; 1414 data |= 0x20 ; 1415 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */ 1416 1417 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; 1418 1419 1420 XGINew_SetReg1(pVBInfo->P3c4, 0x16, (unsigned short)(data | 0x0F)); /* assume lowest speed DRAM */ 1421 1422 XGINew_SetDRAMModeRegister( pVBInfo ) ; 1423 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ; 1424 XGINew_CheckBusWidth_310( pVBInfo) ; 1425 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */ 1426 1427 1428 1429 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 ) 1430 { 1431 XGINew_SDRSizing( pVBInfo ) ; 1432 } 1433 else 1434 { 1435 XGINew_DDRSizing( pVBInfo) ; 1436 } 1437 1438 1439 1440 1441 XGINew_SetReg1(pVBInfo->P3c4, 0x16, pVBInfo->SR15[1][XGINew_RAMType]); /* restore SR16 */ 1442 1443 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ; 1444 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ; 1445 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */ 1446} 1447 1448 1449 1450/* --------------------------------------------------------------------- */ 1451/* Function : XGINew_SetDRAMModeRegister340 */ 1452/* Input : */ 1453/* Output : */ 1454/* Description : */ 1455/* --------------------------------------------------------------------- */ 1456 1457void XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension) 1458{ 1459 unsigned char data ; 1460 struct vb_device_info VBINF; 1461 struct vb_device_info *pVBInfo = &VBINF; 1462 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 1463 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 1464 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ; 1465 pVBInfo->ISXPDOS = 0 ; 1466 1467 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 1468 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 1469 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 1470 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 1471 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 1472 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 1473 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 1474 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 1475 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 1476 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 1477 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 1478 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 1479 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 1480 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 1481 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 1482 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 1483 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 1484 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */ 1485 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */ 1486 1487 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 1488 1489 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 1490 1491 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 1492 { 1493 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ; 1494 if ( data == 0x01 ) 1495 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ; 1496 else 1497 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ; 1498 } 1499 else 1500 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo); 1501 1502 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ; 1503} 1504 1505/* --------------------------------------------------------------------- */ 1506/* Function : XGINew_SetDRAMModeRegister */ 1507/* Input : */ 1508/* Output : */ 1509/* Description : */ 1510/* --------------------------------------------------------------------- */ 1511void XGINew_SetDRAMModeRegister(struct vb_device_info *pVBInfo) 1512{ 1513 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 ) 1514 { 1515 XGINew_SDR_MRS(pVBInfo ) ; 1516 } 1517 else 1518 { 1519 /* SR16 <- 0F,CF,0F,8F */ 1520 XGINew_DDR_MRS( pVBInfo ) ; 1521 } 1522} 1523 1524 1525/* --------------------------------------------------------------------- */ 1526/* Function : XGINew_DisableRefresh */ 1527/* Input : */ 1528/* Output : */ 1529/* Description : */ 1530/* --------------------------------------------------------------------- */ 1531void XGINew_DisableRefresh(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 1532{ 1533 unsigned short data ; 1534 1535 1536 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ; 1537 data &= 0xF8 ; 1538 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ; 1539 1540} 1541 1542 1543/* --------------------------------------------------------------------- */ 1544/* Function : XGINew_EnableRefresh */ 1545/* Input : */ 1546/* Output : */ 1547/* Description : */ 1548/* --------------------------------------------------------------------- */ 1549void XGINew_EnableRefresh(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 1550{ 1551 1552 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 1553 1554 1555} 1556 1557 1558/* --------------------------------------------------------------------- */ 1559/* Function : XGINew_DisableChannelInterleaving */ 1560/* Input : */ 1561/* Output : */ 1562/* Description : */ 1563/* --------------------------------------------------------------------- */ 1564void XGINew_DisableChannelInterleaving(int index, 1565 unsigned short XGINew_DDRDRAM_TYPE[][5], 1566 struct vb_device_info *pVBInfo) 1567{ 1568 unsigned short data ; 1569 1570 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ; 1571 data &= 0x1F ; 1572 1573 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] ) 1574 { 1575 case 64: 1576 data |= 0 ; 1577 break ; 1578 case 32: 1579 data |= 0x20 ; 1580 break ; 1581 case 16: 1582 data |= 0x40 ; 1583 break ; 1584 case 4: 1585 data |= 0x60 ; 1586 break ; 1587 default: 1588 break ; 1589 } 1590 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ; 1591} 1592 1593 1594/* --------------------------------------------------------------------- */ 1595/* Function : XGINew_SetDRAMSizingType */ 1596/* Input : */ 1597/* Output : */ 1598/* Description : */ 1599/* --------------------------------------------------------------------- */ 1600void XGINew_SetDRAMSizingType(int index, 1601 unsigned short DRAMTYPE_TABLE[][5], 1602 struct vb_device_info *pVBInfo) 1603{ 1604 unsigned short data; 1605 1606 data = DRAMTYPE_TABLE[ index ][ 4 ] ; 1607 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ; 1608 DelayUS( 15 ) ; 1609 /* should delay 50 ns */ 1610} 1611 1612 1613/* --------------------------------------------------------------------- */ 1614/* Function : XGINew_CheckBusWidth_310 */ 1615/* Input : */ 1616/* Output : */ 1617/* Description : */ 1618/* --------------------------------------------------------------------- */ 1619void XGINew_CheckBusWidth_310(struct vb_device_info *pVBInfo) 1620{ 1621 unsigned short data ; 1622 volatile unsigned long *pVideoMemory ; 1623 1624 pVideoMemory = (unsigned long *) pVBInfo->FBAddr; 1625 1626 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 ) 1627 { 1628 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ; 1629 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ; 1630 /* should delay */ 1631 XGINew_SDR_MRS( pVBInfo ) ; 1632 1633 XGINew_ChannelAB = 0 ; 1634 XGINew_DataBusWidth = 128 ; 1635 pVideoMemory[ 0 ] = 0x01234567L ; 1636 pVideoMemory[ 1 ] = 0x456789ABL ; 1637 pVideoMemory[ 2 ] = 0x89ABCDEFL ; 1638 pVideoMemory[ 3 ] = 0xCDEF0123L ; 1639 pVideoMemory[ 4 ] = 0x55555555L ; 1640 pVideoMemory[ 5 ] = 0x55555555L ; 1641 pVideoMemory[ 6 ] = 0xFFFFFFFFL ; 1642 pVideoMemory[ 7 ] = 0xFFFFFFFFL ; 1643 1644 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) ) 1645 { 1646 /* ChannelA64Bit */ 1647 XGINew_DataBusWidth = 64 ; 1648 XGINew_ChannelAB = 0 ; 1649 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ; 1650 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (unsigned short)(data & 0xFD)); 1651 } 1652 1653 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) ) 1654 { 1655 /* ChannelB64Bit */ 1656 XGINew_DataBusWidth = 64 ; 1657 XGINew_ChannelAB = 1 ; 1658 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ; 1659 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 1660 (unsigned short)((data & 0xFD) | 0x01)); 1661 } 1662 1663 return ; 1664 } 1665 else 1666 { 1667 /* DDR Dual channel */ 1668 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ; 1669 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */ 1670 /* should delay */ 1671 XGINew_DDR_MRS( pVBInfo ) ; 1672 1673 XGINew_ChannelAB = 0 ; 1674 XGINew_DataBusWidth = 64 ; 1675 pVideoMemory[ 0 ] = 0x01234567L ; 1676 pVideoMemory[ 1 ] = 0x456789ABL ; 1677 pVideoMemory[ 2 ] = 0x89ABCDEFL ; 1678 pVideoMemory[ 3 ] = 0xCDEF0123L ; 1679 pVideoMemory[ 4 ] = 0x55555555L ; 1680 pVideoMemory[ 5 ] = 0x55555555L ; 1681 pVideoMemory[ 6 ] = 0xAAAAAAAAL ; 1682 pVideoMemory[ 7 ] = 0xAAAAAAAAL ; 1683 1684 if ( pVideoMemory[ 1 ] == 0x456789ABL ) 1685 { 1686 if ( pVideoMemory[ 0 ] == 0x01234567L ) 1687 { 1688 /* Channel A 64bit */ 1689 return ; 1690 } 1691 } 1692 else 1693 { 1694 if ( pVideoMemory[ 0 ] == 0x01234567L ) 1695 { 1696 /* Channel A 32bit */ 1697 XGINew_DataBusWidth = 32 ; 1698 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ; 1699 return ; 1700 } 1701 } 1702 1703 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */ 1704 XGINew_DDR_MRS( pVBInfo); 1705 1706 XGINew_ChannelAB = 1 ; 1707 XGINew_DataBusWidth = 64 ; 1708 pVideoMemory[ 0 ] = 0x01234567L ; 1709 pVideoMemory[ 1 ] = 0x456789ABL ; 1710 pVideoMemory[ 2 ] = 0x89ABCDEFL ; 1711 pVideoMemory[ 3 ] = 0xCDEF0123L ; 1712 pVideoMemory[ 4 ] = 0x55555555L ; 1713 pVideoMemory[ 5 ] = 0x55555555L ; 1714 pVideoMemory[ 6 ] = 0xAAAAAAAAL ; 1715 pVideoMemory[ 7 ] = 0xAAAAAAAAL ; 1716 1717 if ( pVideoMemory[ 1 ] == 0x456789ABL ) 1718 { 1719 /* Channel B 64 */ 1720 if ( pVideoMemory[ 0 ] == 0x01234567L ) 1721 { 1722 /* Channel B 64bit */ 1723 return ; 1724 } 1725 else 1726 { 1727 /* error */ 1728 } 1729 } 1730 else 1731 { 1732 if ( pVideoMemory[ 0 ] == 0x01234567L ) 1733 { 1734 /* Channel B 32 */ 1735 XGINew_DataBusWidth = 32 ; 1736 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ; 1737 } 1738 else 1739 { 1740 /* error */ 1741 } 1742 } 1743 } 1744} 1745 1746 1747/* --------------------------------------------------------------------- */ 1748/* Function : XGINew_SetRank */ 1749/* Input : */ 1750/* Output : */ 1751/* Description : */ 1752/* --------------------------------------------------------------------- */ 1753int XGINew_SetRank(int index, 1754 unsigned char RankNo, 1755 unsigned char XGINew_ChannelAB, 1756 unsigned short DRAMTYPE_TABLE[][5], 1757 struct vb_device_info *pVBInfo) 1758{ 1759 unsigned short data; 1760 int RankSize ; 1761 1762 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) ) 1763 return 0 ; 1764 1765 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ; 1766 1767 if ( ( RankNo * RankSize ) <= 128 ) 1768 { 1769 data = 0 ; 1770 1771 while( ( RankSize >>= 1 ) > 0 ) 1772 { 1773 data += 0x10 ; 1774 } 1775 data |= ( RankNo - 1 ) << 2 ; 1776 data |= ( XGINew_DataBusWidth / 64 ) & 2 ; 1777 data |= XGINew_ChannelAB ; 1778 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; 1779 /* should delay */ 1780 XGINew_SDR_MRS( pVBInfo ) ; 1781 return( 1 ) ; 1782 } 1783 else 1784 return( 0 ) ; 1785} 1786 1787 1788/* --------------------------------------------------------------------- */ 1789/* Function : XGINew_SetDDRChannel */ 1790/* Input : */ 1791/* Output : */ 1792/* Description : */ 1793/* --------------------------------------------------------------------- */ 1794int XGINew_SetDDRChannel(int index, 1795 unsigned char ChannelNo, 1796 unsigned char XGINew_ChannelAB, 1797 unsigned short DRAMTYPE_TABLE[][5], 1798 struct vb_device_info *pVBInfo) 1799{ 1800 unsigned short data; 1801 int RankSize ; 1802 1803 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32; 1804 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */ 1805 if ( ChannelNo * RankSize <= 128 ) 1806 { 1807 data = 0 ; 1808 while( ( RankSize >>= 1 ) > 0 ) 1809 { 1810 data += 0x10 ; 1811 } 1812 1813 if ( ChannelNo == 2 ) 1814 data |= 0x0C ; 1815 1816 data |= ( XGINew_DataBusWidth / 32 ) & 2 ; 1817 data |= XGINew_ChannelAB ; 1818 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; 1819 /* should delay */ 1820 XGINew_DDR_MRS( pVBInfo ) ; 1821 return( 1 ) ; 1822 } 1823 else 1824 return( 0 ) ; 1825} 1826 1827 1828/* --------------------------------------------------------------------- */ 1829/* Function : XGINew_CheckColumn */ 1830/* Input : */ 1831/* Output : */ 1832/* Description : */ 1833/* --------------------------------------------------------------------- */ 1834int XGINew_CheckColumn(int index, 1835 unsigned short DRAMTYPE_TABLE[][5], 1836 struct vb_device_info *pVBInfo) 1837{ 1838 int i ; 1839 unsigned long Increment , Position ; 1840 1841 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */ 1842 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ; 1843 1844 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 1845 { 1846 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position; 1847 Position += Increment ; 1848 } 1849 1850 1851 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 1852 { 1853 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */ 1854 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position) 1855 return 0; 1856 Position += Increment; 1857 } 1858 return( 1 ) ; 1859} 1860 1861 1862/* --------------------------------------------------------------------- */ 1863/* Function : XGINew_CheckBanks */ 1864/* Input : */ 1865/* Output : */ 1866/* Description : */ 1867/* --------------------------------------------------------------------- */ 1868int XGINew_CheckBanks(int index, 1869 unsigned short DRAMTYPE_TABLE[][5], 1870 struct vb_device_info *pVBInfo) 1871{ 1872 int i ; 1873 unsigned long Increment , Position ; 1874 1875 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ; 1876 1877 for( i = 0 , Position = 0 ; i < 4 ; i++ ) 1878 { 1879 /* pVBInfo->FBAddr[ Position ] = Position ; */ 1880 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position; 1881 Position += Increment ; 1882 } 1883 1884 for( i = 0 , Position = 0 ; i < 4 ; i++ ) 1885 { 1886 /* if (pVBInfo->FBAddr[ Position ] != Position ) */ 1887 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position) 1888 return 0; 1889 Position += Increment; 1890 } 1891 return( 1 ) ; 1892} 1893 1894 1895/* --------------------------------------------------------------------- */ 1896/* Function : XGINew_CheckRank */ 1897/* Input : */ 1898/* Output : */ 1899/* Description : */ 1900/* --------------------------------------------------------------------- */ 1901int XGINew_CheckRank(int RankNo, int index, 1902 unsigned short DRAMTYPE_TABLE[][5], 1903 struct vb_device_info *pVBInfo) 1904{ 1905 int i ; 1906 unsigned long Increment , Position ; 1907 1908 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] + 1909 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ; 1910 1911 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 1912 { 1913 /* pVBInfo->FBAddr[ Position ] = Position ; */ 1914 /* *( (unsigned long *)( pVBInfo->FBAddr ) ) = Position ; */ 1915 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position; 1916 Position += Increment; 1917 } 1918 1919 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 1920 { 1921 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */ 1922 /* if ( ( *(unsigned long *)( pVBInfo->FBAddr ) ) != Position ) */ 1923 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position) 1924 return 0; 1925 Position += Increment; 1926 } 1927 return( 1 ); 1928} 1929 1930 1931/* --------------------------------------------------------------------- */ 1932/* Function : XGINew_CheckDDRRank */ 1933/* Input : */ 1934/* Output : */ 1935/* Description : */ 1936/* --------------------------------------------------------------------- */ 1937int XGINew_CheckDDRRank(int RankNo, int index, 1938 unsigned short DRAMTYPE_TABLE[][5], 1939 struct vb_device_info *pVBInfo) 1940{ 1941 unsigned long Increment , Position ; 1942 unsigned short data ; 1943 1944 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] + 1945 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ; 1946 1947 Increment += Increment / 2 ; 1948 1949 Position = 0; 1950 *((unsigned long *)(pVBInfo->FBAddr + Position + 0)) = 0x01234567; 1951 *((unsigned long *)(pVBInfo->FBAddr + Position + 1)) = 0x456789AB; 1952 *((unsigned long *)(pVBInfo->FBAddr + Position + 2)) = 0x55555555; 1953 *((unsigned long *)(pVBInfo->FBAddr + Position + 3)) = 0x55555555; 1954 *((unsigned long *)(pVBInfo->FBAddr + Position + 4)) = 0xAAAAAAAA; 1955 *((unsigned long *)(pVBInfo->FBAddr + Position + 5)) = 0xAAAAAAAA; 1956 1957 if ((*(unsigned long *)(pVBInfo->FBAddr + 1)) == 0x456789AB) 1958 return 1; 1959 1960 if ((*(unsigned long *)(pVBInfo->FBAddr + 0)) == 0x01234567) 1961 return 0; 1962 1963 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ; 1964 data &= 0xF3 ; 1965 data |= 0x0E ; 1966 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; 1967 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ; 1968 data += 0x20 ; 1969 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ; 1970 1971 return( 1 ) ; 1972} 1973 1974 1975/* --------------------------------------------------------------------- */ 1976/* Function : XGINew_CheckRanks */ 1977/* Input : */ 1978/* Output : */ 1979/* Description : */ 1980/* --------------------------------------------------------------------- */ 1981int XGINew_CheckRanks(int RankNo, int index, 1982 unsigned short DRAMTYPE_TABLE[][5], 1983 struct vb_device_info *pVBInfo) 1984{ 1985 int r ; 1986 1987 for( r = RankNo ; r >= 1 ; r-- ) 1988 { 1989 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) ) 1990 return( 0 ) ; 1991 } 1992 1993 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) ) 1994 return( 0 ) ; 1995 1996 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) ) 1997 return( 0 ) ; 1998 1999 return( 1 ) ; 2000} 2001 2002 2003/* --------------------------------------------------------------------- */ 2004/* Function : XGINew_CheckDDRRanks */ 2005/* Input : */ 2006/* Output : */ 2007/* Description : */ 2008/* --------------------------------------------------------------------- */ 2009int XGINew_CheckDDRRanks(int RankNo, int index, 2010 unsigned short DRAMTYPE_TABLE[][5], 2011 struct vb_device_info *pVBInfo) 2012{ 2013 int r ; 2014 2015 for( r = RankNo ; r >= 1 ; r-- ) 2016 { 2017 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) ) 2018 return( 0 ) ; 2019 } 2020 2021 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) ) 2022 return( 0 ) ; 2023 2024 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) ) 2025 return( 0 ) ; 2026 2027 return( 1 ) ; 2028} 2029 2030 2031/* --------------------------------------------------------------------- */ 2032/* Function : */ 2033/* Input : */ 2034/* Output : */ 2035/* Description : */ 2036/* --------------------------------------------------------------------- */ 2037int XGINew_SDRSizing(struct vb_device_info *pVBInfo) 2038{ 2039 int i ; 2040 unsigned char j ; 2041 2042 for( i = 0 ; i < 13 ; i++ ) 2043 { 2044 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ; 2045 2046 for( j = 2 ; j > 0 ; j-- ) 2047 { 2048 if (!XGINew_SetRank(i, (unsigned char)j, XGINew_ChannelAB, 2049 XGINew_SDRDRAM_TYPE, pVBInfo)) 2050 continue ; 2051 else 2052 { 2053 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) ) 2054 return( 1 ) ; 2055 } 2056 } 2057 } 2058 return( 0 ) ; 2059} 2060 2061 2062/* --------------------------------------------------------------------- */ 2063/* Function : XGINew_SetDRAMSizeReg */ 2064/* Input : */ 2065/* Output : */ 2066/* Description : */ 2067/* --------------------------------------------------------------------- */ 2068unsigned short XGINew_SetDRAMSizeReg(int index, 2069 unsigned short DRAMTYPE_TABLE[][5], 2070 struct vb_device_info *pVBInfo) 2071{ 2072 unsigned short data = 0 , memsize = 0; 2073 int RankSize ; 2074 unsigned char ChannelNo ; 2075 2076 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ; 2077 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ; 2078 data &= 0x80 ; 2079 2080 if ( data == 0x80 ) 2081 RankSize *= 2 ; 2082 2083 data = 0 ; 2084 2085 if( XGINew_ChannelAB == 3 ) 2086 ChannelNo = 4 ; 2087 else 2088 ChannelNo = XGINew_ChannelAB ; 2089 2090 if ( ChannelNo * RankSize <= 256 ) 2091 { 2092 while( ( RankSize >>= 1 ) > 0 ) 2093 { 2094 data += 0x10 ; 2095 } 2096 2097 memsize = data >> 4 ; 2098 2099 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */ 2100 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ; 2101 2102 /* data |= XGINew_ChannelAB << 2 ; */ 2103 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */ 2104 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */ 2105 2106 /* should delay */ 2107 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 2108 } 2109 return( memsize ) ; 2110} 2111 2112 2113/* --------------------------------------------------------------------- */ 2114/* Function : XGINew_SetDRAMSize20Reg */ 2115/* Input : */ 2116/* Output : */ 2117/* Description : */ 2118/* --------------------------------------------------------------------- */ 2119unsigned short XGINew_SetDRAMSize20Reg(int index, 2120 unsigned short DRAMTYPE_TABLE[][5], 2121 struct vb_device_info *pVBInfo) 2122{ 2123 unsigned short data = 0 , memsize = 0; 2124 int RankSize ; 2125 unsigned char ChannelNo ; 2126 2127 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ; 2128 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ; 2129 data &= 0x80 ; 2130 2131 if ( data == 0x80 ) 2132 RankSize *= 2 ; 2133 2134 data = 0 ; 2135 2136 if( XGINew_ChannelAB == 3 ) 2137 ChannelNo = 4 ; 2138 else 2139 ChannelNo = XGINew_ChannelAB ; 2140 2141 if ( ChannelNo * RankSize <= 256 ) 2142 { 2143 while( ( RankSize >>= 1 ) > 0 ) 2144 { 2145 data += 0x10 ; 2146 } 2147 2148 memsize = data >> 4 ; 2149 2150 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */ 2151 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ; 2152 DelayUS( 15 ) ; 2153 2154 /* data |= XGINew_ChannelAB << 2 ; */ 2155 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */ 2156 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */ 2157 2158 /* should delay */ 2159 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 2160 } 2161 return( memsize ) ; 2162} 2163 2164 2165/* --------------------------------------------------------------------- */ 2166/* Function : XGINew_ReadWriteRest */ 2167/* Input : */ 2168/* Output : */ 2169/* Description : */ 2170/* --------------------------------------------------------------------- */ 2171int XGINew_ReadWriteRest(unsigned short StopAddr, unsigned short StartAddr, 2172 struct vb_device_info *pVBInfo) 2173{ 2174 int i ; 2175 unsigned long Position = 0 ; 2176 2177 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position; 2178 2179 for( i = StartAddr ; i <= StopAddr ; i++ ) 2180 { 2181 Position = 1 << i ; 2182 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position; 2183 } 2184 2185 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */ 2186 2187 Position = 0 ; 2188 2189 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position) 2190 return 0; 2191 2192 for( i = StartAddr ; i <= StopAddr ; i++ ) 2193 { 2194 Position = 1 << i ; 2195 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position) 2196 return 0; 2197 } 2198 return( 1 ) ; 2199} 2200 2201 2202/* --------------------------------------------------------------------- */ 2203/* Function : XGINew_CheckFrequence */ 2204/* Input : */ 2205/* Output : */ 2206/* Description : */ 2207/* --------------------------------------------------------------------- */ 2208unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo) 2209{ 2210 unsigned char data ; 2211 2212 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ; 2213 2214 if ( ( data & 0x10 ) == 0 ) 2215 { 2216 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ; 2217 data = ( data & 0x02 ) >> 1 ; 2218 return( data ) ; 2219 } 2220 else 2221 return( data & 0x01 ) ; 2222} 2223 2224 2225/* --------------------------------------------------------------------- */ 2226/* Function : XGINew_CheckChannel */ 2227/* Input : */ 2228/* Output : */ 2229/* Description : */ 2230/* --------------------------------------------------------------------- */ 2231void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 2232{ 2233 unsigned char data; 2234 2235 switch( HwDeviceExtension->jChipType ) 2236 { 2237 case XG20: 2238 case XG21: 2239 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ; 2240 data = data & 0x01; 2241 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */ 2242 2243 if ( data == 0 ) /* Single_32_16 */ 2244 { 2245 2246 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000) 2247 { 2248 2249 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2250 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */ 2251 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2252 DelayUS( 15 ) ; 2253 2254 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2255 return ; 2256 2257 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2258 { 2259 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */ 2260 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2261 DelayUS( 15 ) ; 2262 2263 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 ) 2264 return ; 2265 } 2266 } 2267 2268 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2269 { 2270 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2271 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */ 2272 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; 2273 DelayUS( 15 ) ; 2274 2275 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2276 return ; 2277 else 2278 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; 2279 DelayUS( 15 ) ; 2280 } 2281 2282 } 2283 else /* Dual_16_8 */ 2284 { 2285 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2286 { 2287 2288 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2289 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */ 2290 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/ 2291 DelayUS( 15 ) ; 2292 2293 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2294 return ; 2295 2296 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000) 2297 { 2298 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */ 2299 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/ 2300 DelayUS( 15 ) ; 2301 2302 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 ) 2303 return ; 2304 } 2305 } 2306 2307 2308 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000) 2309 { 2310 XGINew_DataBusWidth = 8 ; /* 8 bits */ 2311 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */ 2312 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/ 2313 DelayUS( 15 ) ; 2314 2315 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 ) 2316 return ; 2317 else 2318 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */ 2319 DelayUS( 15 ) ; 2320 } 2321 } 2322 break ; 2323 2324 case XG27: 2325 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2326 XGINew_ChannelAB = 1 ; /* Single channel */ 2327 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/ 2328 break ; 2329 case XG41: 2330 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) 2331 { 2332 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2333 XGINew_ChannelAB = 3 ; /* Quad Channel */ 2334 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2335 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ; 2336 2337 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 ) 2338 return ; 2339 2340 XGINew_ChannelAB = 2 ; /* Dual channels */ 2341 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ; 2342 2343 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2344 return ; 2345 2346 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ; 2347 2348 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2349 return ; 2350 2351 XGINew_ChannelAB = 3 ; 2352 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2353 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ; 2354 2355 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2356 return ; 2357 2358 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ; 2359 2360 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 ) 2361 return ; 2362 else 2363 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ; 2364 } 2365 else 2366 { /* DDR */ 2367 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2368 XGINew_ChannelAB = 2 ; /* Dual channels */ 2369 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2370 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ; 2371 2372 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2373 return ; 2374 2375 XGINew_ChannelAB = 1 ; /* Single channels */ 2376 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2377 2378 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2379 return ; 2380 2381 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ; 2382 2383 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2384 return ; 2385 2386 XGINew_ChannelAB = 2 ; /* Dual channels */ 2387 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2388 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ; 2389 2390 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2391 return ; 2392 2393 XGINew_ChannelAB = 1 ; /* Single channels */ 2394 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2395 2396 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 ) 2397 return ; 2398 else 2399 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ; 2400 } 2401 2402 break ; 2403 2404 case XG42: 2405/* 2406 XG42 SR14 D[3] Reserve 2407 D[2] = 1, Dual Channel 2408 = 0, Single Channel 2409 2410 It's Different from Other XG40 Series. 2411*/ 2412 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */ 2413 { 2414 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2415 XGINew_ChannelAB = 2 ; /* 2 Channel */ 2416 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2417 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ; 2418 2419 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2420 return ; 2421 2422 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2423 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ; 2424 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2425 return ; 2426 2427 XGINew_ChannelAB = 1 ; /* Single Channel */ 2428 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2429 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ; 2430 2431 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2432 return ; 2433 else 2434 { 2435 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2436 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; 2437 } 2438 } 2439 else 2440 { /* DDR */ 2441 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2442 XGINew_ChannelAB = 1 ; /* 1 channels */ 2443 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2444 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2445 2446 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2447 return ; 2448 else 2449 { 2450 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2451 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2452 } 2453 } 2454 2455 break ; 2456 2457 default: /* XG40 */ 2458 2459 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */ 2460 { 2461 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2462 XGINew_ChannelAB = 3 ; 2463 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2464 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ; 2465 2466 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 ) 2467 return ; 2468 2469 XGINew_ChannelAB = 2 ; /* 2 channels */ 2470 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ; 2471 2472 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2473 return ; 2474 2475 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2476 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ; 2477 2478 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2479 XGINew_ChannelAB = 3 ; /* 4 channels */ 2480 else 2481 { 2482 XGINew_ChannelAB = 2 ; /* 2 channels */ 2483 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ; 2484 } 2485 } 2486 else 2487 { /* DDR */ 2488 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2489 XGINew_ChannelAB = 2 ; /* 2 channels */ 2490 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2491 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ; 2492 2493 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2494 return ; 2495 else 2496 { 2497 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2498 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ; 2499 } 2500 } 2501 break ; 2502 } 2503} 2504 2505 2506/* --------------------------------------------------------------------- */ 2507/* Function : XGINew_DDRSizing340 */ 2508/* Input : */ 2509/* Output : */ 2510/* Description : */ 2511/* --------------------------------------------------------------------- */ 2512int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 2513{ 2514 int i ; 2515 unsigned short memsize , addr ; 2516 2517 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */ 2518 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */ 2519 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ; 2520 2521 2522 if ( HwDeviceExtension->jChipType >= XG20 ) 2523 { 2524 for( i = 0 ; i < 12 ; i++ ) 2525 { 2526 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ; 2527 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ; 2528 if ( memsize == 0 ) 2529 continue ; 2530 2531 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ; 2532 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long)(1 << addr)) 2533 continue ; 2534 2535 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 ) 2536 return( 1 ) ; 2537 } 2538 } 2539 else 2540 { 2541 for( i = 0 ; i < 4 ; i++ ) 2542 { 2543 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2544 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2545 2546 if ( memsize == 0 ) 2547 continue ; 2548 2549 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ; 2550 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long)(1 << addr)) 2551 continue ; 2552 2553 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 ) 2554 return( 1 ) ; 2555 } 2556 } 2557 return( 0 ) ; 2558} 2559 2560 2561/* --------------------------------------------------------------------- */ 2562/* Function : XGINew_DDRSizing */ 2563/* Input : */ 2564/* Output : */ 2565/* Description : */ 2566/* --------------------------------------------------------------------- */ 2567int XGINew_DDRSizing(struct vb_device_info *pVBInfo) 2568{ 2569 int i ; 2570 unsigned char j ; 2571 2572 for( i = 0 ; i < 4 ; i++ ) 2573 { 2574 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ; 2575 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ; 2576 for( j = 2 ; j > 0 ; j-- ) 2577 { 2578 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ; 2579 if (!XGINew_SetRank(i, (unsigned char)j, XGINew_ChannelAB, 2580 XGINew_DDRDRAM_TYPE, pVBInfo)) 2581 continue ; 2582 else 2583 { 2584 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) ) 2585 return( 1 ) ; 2586 } 2587 } 2588 } 2589 return( 0 ) ; 2590} 2591 2592/* --------------------------------------------------------------------- */ 2593/* Function : XGINew_SetMemoryClock */ 2594/* Input : */ 2595/* Output : */ 2596/* Description : */ 2597/* --------------------------------------------------------------------- */ 2598void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 2599{ 2600 2601 2602 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ; 2603 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ; 2604 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ; 2605 2606 2607 2608 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ; 2609 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ; 2610 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ; 2611 2612 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */ 2613 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */ 2614 if ( HwDeviceExtension->jChipType == XG42 ) 2615 { 2616 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 ) 2617 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) 2618 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) ) 2619 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02); 2620 } 2621} 2622 2623 2624/* --------------------------------------------------------------------- */ 2625/* Function : ChkLFB */ 2626/* Input : */ 2627/* Output : */ 2628/* Description : */ 2629/* --------------------------------------------------------------------- */ 2630unsigned char ChkLFB(struct vb_device_info *pVBInfo) 2631{ 2632 if (LFBDRAMTrap & XGINew_GetReg1(pVBInfo->P3d4 , 0x78)) 2633 return 1; 2634 else 2635 return 0; 2636} 2637 2638 2639/* --------------------------------------------------------------------- */ 2640/* input : dx ,valid value : CR or second chip's CR */ 2641/* */ 2642/* SetPowerConsume : */ 2643/* Description: reduce 40/43 power consumption in first chip or */ 2644/* in second chip, assume CR A1 D[6]="1" in this case */ 2645/* output : none */ 2646/* --------------------------------------------------------------------- */ 2647void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension, 2648 unsigned long XGI_P3d4Port) 2649{ 2650 unsigned long lTemp ; 2651 unsigned char bTemp; 2652 2653 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */ 2654 if ((lTemp&0xFF)==0) 2655 { 2656 /* set CR58 D[5]=0 D[3]=0 */ 2657 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ; 2658 bTemp = (unsigned char) XGINew_GetReg1(XGI_P3d4Port, 0xCB); 2659 if (bTemp&0x20) 2660 { 2661 if (!(bTemp&0x10)) 2662 { 2663 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */ 2664 } 2665 else 2666 { 2667 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */ 2668 } 2669 2670 } 2671 2672 } 2673} 2674 2675 2676void XGINew_InitVBIOSData(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 2677{ 2678 2679 /* unsigned long ROMAddr = (unsigned long)HwDeviceExtension->pjVirtualRomBase; */ 2680 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 2681 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 2682 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ; 2683 pVBInfo->ISXPDOS = 0 ; 2684 2685 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 2686 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 2687 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 2688 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 2689 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 2690 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 2691 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 2692 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 2693 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 2694 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 2695 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 2696 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 2697 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 2698 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 2699 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 2700 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 2701 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 2702 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */ 2703 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */ 2704 2705 switch(HwDeviceExtension->jChipType) 2706 { 2707 case XG40: 2708 case XG41: 2709 case XG42: 2710 case XG20: 2711 case XG21: 2712 default: 2713 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 2714 return ; 2715 } 2716 2717} 2718 2719/* --------------------------------------------------------------------- */ 2720/* Function : ReadVBIOSTablData */ 2721/* Input : */ 2722/* Output : */ 2723/* Description : */ 2724/* --------------------------------------------------------------------- */ 2725void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo) 2726{ 2727 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr; 2728 unsigned long i ; 2729 unsigned char j, k ; 2730 /* Volari customize data area end */ 2731 2732 if ( ChipType == XG21 ) 2733 { 2734 pVBInfo->IF_DEF_LVDS = 0 ; 2735 if (pVideoMemory[ 0x65 ] & 0x1) 2736 { 2737 pVBInfo->IF_DEF_LVDS = 1 ; 2738 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 ); 2739 j = pVideoMemory[ i-1 ] ; 2740 if ( j != 0xff ) 2741 { 2742 k = 0; 2743 do 2744 { 2745 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 2746 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 2747 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 2748 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 2749 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 2750 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 2751 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 2752 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 2753 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 2754 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ; 2755 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ; 2756 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ; 2757 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ; 2758 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ; 2759 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ; 2760 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ; 2761 i += 25; 2762 j--; 2763 k++; 2764 } while ((j > 0) && 2765 (k < (sizeof(XGI21_LCDCapList)/sizeof(struct XGI21_LVDSCapStruct)))); 2766 } 2767 else 2768 { 2769 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 2770 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 2771 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 2772 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 2773 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 2774 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 2775 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 2776 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 2777 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 2778 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ; 2779 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ; 2780 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ; 2781 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ; 2782 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ; 2783 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ; 2784 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ; 2785 } 2786 } 2787 } 2788} 2789 2790/* --------------------------------------------------------------------- */ 2791/* Function : XGINew_DDR1x_MRS_XG20 */ 2792/* Input : */ 2793/* Output : */ 2794/* Description : */ 2795/* --------------------------------------------------------------------- */ 2796void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo) 2797{ 2798 2799 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ; 2800 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; 2801 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 2802 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 2803 DelayUS( 60 ) ; 2804 2805 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; 2806 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; 2807 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; 2808 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; 2809 DelayUS( 60 ) ; 2810 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 2811 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */ 2812 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ; 2813 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ; 2814 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; 2815 DelayUS( 1000 ) ; 2816 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; 2817 DelayUS( 500 ) ; 2818 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */ 2819 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 2820 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ; 2821 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ; 2822 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; 2823 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; 2824} 2825 2826/* --------------------------------------------------------------------- */ 2827/* Function : XGINew_SetDRAMModeRegister_XG20 */ 2828/* Input : */ 2829/* Output : */ 2830/* Description : */ 2831/* --------------------------------------------------------------------- */ 2832void XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension) 2833{ 2834 struct vb_device_info VBINF; 2835 struct vb_device_info *pVBInfo = &VBINF; 2836 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 2837 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 2838 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ; 2839 pVBInfo->ISXPDOS = 0 ; 2840 2841 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 2842 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 2843 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 2844 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 2845 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 2846 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 2847 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 2848 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 2849 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 2850 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 2851 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 2852 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 2853 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 2854 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 2855 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 2856 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 2857 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 2858 2859 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 2860 2861 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 2862 2863 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 2864 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ; 2865 else 2866 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ; 2867 2868 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ; 2869} 2870 2871void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension) 2872{ 2873 struct vb_device_info VBINF; 2874 struct vb_device_info *pVBInfo = &VBINF; 2875 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 2876 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 2877 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ; 2878 pVBInfo->ISXPDOS = 0 ; 2879 2880 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 2881 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 2882 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 2883 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 2884 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 2885 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 2886 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 2887 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 2888 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 2889 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 2890 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 2891 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 2892 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 2893 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 2894 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 2895 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 2896 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 2897 2898 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 2899 2900 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 2901 2902 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 2903 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ; 2904 else 2905 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ; 2906 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ; 2907 2908 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ; 2909 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 2910 2911} 2912/* 2913void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension) 2914{ 2915 2916 unsigned char data ; 2917 struct vb_device_info VBINF; 2918 struct vb_device_info *pVBInfo = &VBINF; 2919 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 2920 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 2921 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ; 2922 pVBInfo->ISXPDOS = 0 ; 2923 2924 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 2925 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 2926 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 2927 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 2928 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 2929 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 2930 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 2931 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 2932 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 2933 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 2934 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 2935 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 2936 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 2937 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 2938 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 2939 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 2940 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 2941 2942 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 2943 2944 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 2945 2946 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 2947 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ; 2948 else 2949 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ; 2950 2951 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ; 2952} 2953*/ 2954/* -------------------------------------------------------- */ 2955/* Function : XGINew_ChkSenseStatus */ 2956/* Input : */ 2957/* Output : */ 2958/* Description : */ 2959/* -------------------------------------------------------- */ 2960void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 2961{ 2962 unsigned short tempbx = 0, temp, tempcx, CR3CData; 2963 2964 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ; 2965 2966 if ( temp & Monitor1Sense ) 2967 tempbx |= ActiveCRT1 ; 2968 if ( temp & LCDSense ) 2969 tempbx |= ActiveLCD ; 2970 if ( temp & Monitor2Sense ) 2971 tempbx |= ActiveCRT2 ; 2972 if ( temp & TVSense ) 2973 { 2974 tempbx |= ActiveTV ; 2975 if ( temp & AVIDEOSense ) 2976 tempbx |= ( ActiveAVideo << 8 ); 2977 if ( temp & SVIDEOSense ) 2978 tempbx |= ( ActiveSVideo << 8 ); 2979 if ( temp & SCARTSense ) 2980 tempbx |= ( ActiveSCART << 8 ); 2981 if ( temp & HiTVSense ) 2982 tempbx |= ( ActiveHiTV << 8 ); 2983 if ( temp & YPbPrSense ) 2984 tempbx |= ( ActiveYPbPr << 8 ); 2985 } 2986 2987 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ; 2988 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ; 2989 2990 if ( tempbx & tempcx ) 2991 { 2992 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ; 2993 if ( !( CR3CData & DisplayDeviceFromCMOS ) ) 2994 { 2995 tempcx = 0x1FF0 ; 2996 if ( *pVBInfo->pSoftSetting & ModeSoftSetting ) 2997 { 2998 tempbx = 0x1FF0 ; 2999 } 3000 } 3001 } 3002 else 3003 { 3004 tempcx = 0x1FF0 ; 3005 if ( *pVBInfo->pSoftSetting & ModeSoftSetting ) 3006 { 3007 tempbx = 0x1FF0 ; 3008 } 3009 } 3010 3011 tempbx &= tempcx ; 3012 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ; 3013 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ; 3014} 3015/* -------------------------------------------------------- */ 3016/* Function : XGINew_SetModeScratch */ 3017/* Input : */ 3018/* Output : */ 3019/* Description : */ 3020/* -------------------------------------------------------- */ 3021void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 3022{ 3023 unsigned short temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data; 3024 3025 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ; 3026 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ; 3027 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ; 3028 3029 if ( pVBInfo->IF_DEF_CRT2Monitor == 1) 3030 { 3031 if ( temp & ActiveCRT2 ) 3032 tempcl = SetCRT2ToRAMDAC ; 3033 } 3034 3035 if ( temp & ActiveLCD ) 3036 { 3037 tempcl |= SetCRT2ToLCD ; 3038 if ( temp & DriverMode ) 3039 { 3040 if ( temp & ActiveTV ) 3041 { 3042 tempch = SetToLCDA | EnableDualEdge ; 3043 temp ^= SetCRT2ToLCD ; 3044 3045 if ( ( temp >> 8 ) & ActiveAVideo ) 3046 tempcl |= SetCRT2ToAVIDEO ; 3047 if ( ( temp >> 8 ) & ActiveSVideo ) 3048 tempcl |= SetCRT2ToSVIDEO ; 3049 if ( ( temp >> 8 ) & ActiveSCART ) 3050 tempcl |= SetCRT2ToSCART ; 3051 3052 if ( pVBInfo->IF_DEF_HiVision == 1 ) 3053 { 3054 if ( ( temp >> 8 ) & ActiveHiTV ) 3055 tempcl |= SetCRT2ToHiVisionTV ; 3056 } 3057 3058 if ( pVBInfo->IF_DEF_YPbPr == 1 ) 3059 { 3060 if ( ( temp >> 8 ) & ActiveYPbPr ) 3061 tempch |= SetYPbPr ; 3062 } 3063 } 3064 } 3065 } 3066 else 3067 { 3068 if ( ( temp >> 8 ) & ActiveAVideo ) 3069 tempcl |= SetCRT2ToAVIDEO ; 3070 if ( ( temp >> 8 ) & ActiveSVideo ) 3071 tempcl |= SetCRT2ToSVIDEO ; 3072 if ( ( temp >> 8 ) & ActiveSCART ) 3073 tempcl |= SetCRT2ToSCART ; 3074 3075 if ( pVBInfo->IF_DEF_HiVision == 1 ) 3076 { 3077 if ( ( temp >> 8 ) & ActiveHiTV ) 3078 tempcl |= SetCRT2ToHiVisionTV ; 3079 } 3080 3081 if ( pVBInfo->IF_DEF_YPbPr == 1 ) 3082 { 3083 if ( ( temp >> 8 ) & ActiveYPbPr ) 3084 tempch |= SetYPbPr ; 3085 } 3086 } 3087 3088 3089 tempcl |= SetSimuScanMode ; 3090 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) ) 3091 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ; 3092 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) ) 3093 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ; 3094 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ; 3095 3096 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ; 3097 CR31Data &= ~( SetNotSimuMode >> 8 ) ; 3098 if ( !( temp & ActiveCRT1 ) ) 3099 CR31Data |= ( SetNotSimuMode >> 8 ) ; 3100 CR31Data &= ~( DisableCRT2Display >> 8 ) ; 3101 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) ) 3102 CR31Data |= ( DisableCRT2Display >> 8 ) ; 3103 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ; 3104 3105 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ; 3106 CR38Data &= ~SetYPbPr ; 3107 CR38Data |= tempch ; 3108 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ; 3109 3110} 3111 3112/* -------------------------------------------------------- */ 3113/* Function : XGINew_GetXG21Sense */ 3114/* Input : */ 3115/* Output : */ 3116/* Description : */ 3117/* -------------------------------------------------------- */ 3118void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 3119{ 3120 unsigned char Temp; 3121 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr; 3122 3123 pVBInfo->IF_DEF_LVDS = 0 ; 3124 3125 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */ 3126 { 3127 pVBInfo->IF_DEF_LVDS = 1 ; 3128 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3129 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */ 3130 } 3131 else 3132 { 3133 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */ 3134 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0; 3135 if ( Temp == 0xC0 ) 3136 { /* DVI & DVO GPIOA/B pull high */ 3137 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ; 3138 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3139 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */ 3140 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ; 3141 if ( !Temp ) 3142 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */ 3143 else 3144 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */ 3145 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */ 3146 } 3147 } 3148} 3149 3150/* -------------------------------------------------------- */ 3151/* Function : XGINew_GetXG27Sense */ 3152/* Input : */ 3153/* Output : */ 3154/* Description : */ 3155/* -------------------------------------------------------- */ 3156void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) 3157{ 3158 unsigned char Temp, bCR4A; 3159 3160 pVBInfo->IF_DEF_LVDS = 0 ; 3161 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ; 3162 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */ 3163 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07; 3164 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ; 3165 3166 if ( Temp <= 0x02 ) 3167 { 3168 pVBInfo->IF_DEF_LVDS = 1 ; 3169 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */ 3170 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ; 3171 } 3172 else 3173 { 3174 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */ 3175 } 3176 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3177 3178} 3179 3180unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo) 3181{ 3182 unsigned char CR38, CR4A, temp; 3183 3184 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ; 3185 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */ 3186 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ; 3187 temp =0; 3188 if ( ( CR38 & 0xE0 ) > 0x80 ) 3189 { 3190 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; 3191 temp &= 0x08; 3192 temp >>= 3; 3193 } 3194 3195 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ; 3196 3197 return temp; 3198} 3199 3200unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo) 3201{ 3202 unsigned char CR4A, temp; 3203 3204 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ; 3205 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */ 3206 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; 3207 if ( temp <= 2 ) 3208 { 3209 temp &= 0x03; 3210 } 3211 else 3212 { 3213 temp = ((temp&0x04)>>1) || ((~temp)&0x01); 3214 } 3215 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ; 3216 3217 return temp; 3218} 3219