1 2// vim:tw=110:ts=4: 3#ifndef HCFDEFC_H 4#define HCFDEFC_H 1 5 6/************************************************************************************************* 7* 8* FILE : HCFDEF.H 9* 10* DATE : $Date: 2004/08/05 11:47:10 $ $Revision: 1.8 $ 11* Original: 2004/05/28 14:05:35 Revision: 1.59 Tag: hcf7_t20040602_01 12* Original: 2004/05/13 15:31:45 Revision: 1.53 Tag: hcf7_t7_20040513_01 13* Original: 2004/04/15 09:24:42 Revision: 1.44 Tag: hcf7_t7_20040415_01 14* Original: 2004/04/13 14:22:45 Revision: 1.43 Tag: t7_20040413_01 15* Original: 2004/04/01 15:32:55 Revision: 1.40 Tag: t7_20040401_01 16* Original: 2004/03/10 15:39:28 Revision: 1.36 Tag: t20040310_01 17* Original: 2004/03/03 14:10:12 Revision: 1.34 Tag: t20040304_01 18* Original: 2004/03/02 09:27:12 Revision: 1.32 Tag: t20040302_03 19* Original: 2004/02/24 13:00:29 Revision: 1.29 Tag: t20040224_01 20* Original: 2004/02/18 17:13:57 Revision: 1.26 Tag: t20040219_01 21* 22* AUTHOR : Nico Valster 23* 24* SPECIFICATION: ........... 25* 26* DESC : Definitions and Prototypes for HCF only 27* 28************************************************************************************************** 29* 30* 31* SOFTWARE LICENSE 32* 33* This software is provided subject to the following terms and conditions, 34* which you should read carefully before using the software. Using this 35* software indicates your acceptance of these terms and conditions. If you do 36* not agree with these terms and conditions, do not use the software. 37* 38* COPYRIGHT � 1994 - 1995 by AT&T. All Rights Reserved 39* COPYRIGHT � 1996 - 2000 by Lucent Technologies. All Rights Reserved 40* COPYRIGHT � 2001 - 2004 by Agere Systems Inc. All Rights Reserved 41* All rights reserved. 42* 43* Redistribution and use in source or binary forms, with or without 44* modifications, are permitted provided that the following conditions are met: 45* 46* . Redistributions of source code must retain the above copyright notice, this 47* list of conditions and the following Disclaimer as comments in the code as 48* well as in the documentation and/or other materials provided with the 49* distribution. 50* 51* . Redistributions in binary form must reproduce the above copyright notice, 52* this list of conditions and the following Disclaimer in the documentation 53* and/or other materials provided with the distribution. 54* 55* . Neither the name of Agere Systems Inc. nor the names of the contributors 56* may be used to endorse or promote products derived from this software 57* without specific prior written permission. 58* 59* Disclaimer 60* 61* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 62* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF 63* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY 64* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN 65* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY 66* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 67* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 68* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 69* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT 70* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 71* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 72* DAMAGE. 73* 74* 75*************************************************************************************************/ 76 77 78/************************************************************************************************/ 79/********************************* P R E F I X E S ********************************************/ 80/************************************************************************************************/ 81//IFB_ Interface Block 82//HCMD_ Hermes Command 83//HFS_ Hermes (Transmit/Receive) Frame Structure 84//HREG_ Hermes Register 85 86/*************************************************************************************************/ 87 88 89/************************************************************************************************/ 90/********************************* GENERAL EQUATES **********************************************/ 91/************************************************************************************************/ 92 93 94#define HCF_MAGIC 0x7D37 // "}7" Handle validation 95 96#define PLUG_DATA_OFFSET 0x00000800 //needed by some test tool on top of H-II NDIS driver 97 98#define INI_TICK_INI 0x00040000L 99 100#define IO_IN 0 //hcfio_in_string 101#define IO_OUT 1 //hcfio_out_string 102 103//DO_ASSERT, create an artificial FALSE to force an ASSERT without the nasty compiler warning 104#define DO_ASSERT ( assert_ifbp->IFB_Magic != HCF_MAGIC && assert_ifbp->IFB_Magic == HCF_MAGIC ) 105#define NT_ASSERT 0x0000 //, NEVER_TESTED 106#define NEVER_TESTED MERGE_2( 0xEFFE, 0xFEEF ) 107#define SE_ASSERT 0x5EFF /* Side Effect, HCFASSERT invokation which are only called for the 108 * side effect and which should never trigger */ 109#define DHF_FILE_NAME_OFFSET 10000 //to distinguish DHF from HCF asserts by means of line number 110#define MMD_FILE_NAME_OFFSET 20000 //to distinguish MMD from HCF asserts by means of line number 111 112// trace codes used to 113// 1: profile execution times via HCF_TRACE and HCF_TRACE_VALUE 114// 2: hierarchical flow information via HCFLOGENTRY / HCFLOGEXIT 115 116//#define HCF_TRACE_CONNECT useless 117//#define HCF_TRACE_DISCONNECT useless 118#define HCF_TRACE_ACTION 0x0000 // 0x0001 119#define HCF_TRACE_CNTL 0x0001 // 0x0002 120#define HCF_TRACE_DMA_RX_GET 0x0002 // 0x0004 121#define HCF_TRACE_DMA_RX_PUT 0x0003 // 0x0008 122#define HCF_TRACE_DMA_TX_GET 0x0004 // 0x0010 123#define HCF_TRACE_DMA_TX_PUT 0x0005 // 0x0020 124#define HCF_TRACE_GET_INFO 0x0006 // 0x0040 125#define HCF_TRACE_PUT_INFO 0x0007 // 0x0080 126#define HCF_TRACE_RCV_MSG 0x0008 // 0x0100 127#define HCF_TRACE_SEND_MSG 0x0009 // 0x0200 128#define HCF_TRACE_SERVICE_NIC 0x000A // 0x0400 129// #define HCF_TRACE_ 0x000C // 0x1000 130// #define HCF_TRACE_ 0x000D // 0x2000 131// #define HCF_TRACE_ 0x000E // 0x4000 132// #define HCF_TRACE_ 0x000F // 0x8000 133// ============================================ HCF_TRACE_... codes below 0x0010 are asserted on re-entry 134#define HCF_TRACE_ACTION_KLUDGE 0x0010 /* once you start introducing kludges there is no end to it 135 * this is an escape to do not assert on re-entrancy problem caused 136 * by HCF_ACT_INT_FORCE_ON used to get Microsofts NDIS drivers going 137 */ 138#define HCF_TRACE_STRIO 0x0020 139#define HCF_TRACE_ALLOC 0X0021 140#define HCF_TRACE_DL 0X0023 141#define HCF_TRACE_ISR_INFO 0X0024 142#define HCF_TRACE_CALIBRATE 0x0026 143 144#define HCF_TRACE_CMD_CPL 0x0040 145#define HCF_TRACE_CMD_EXE 0x0041 146#define HCF_TRACE_GET_FID 0x0042 147#define HCF_TRACE_GET_FRAG 0x0043 148#define HCF_TRACE_INIT 0x0044 149#define HCF_TRACE_PUT_FRAG 0x0045 150#define HCF_TRACE_SETUP_BAP 0x0046 151 152#define HCF_TRACE_EXIT 0x8000 // Keil C warns "long constant truncated to int" 153 154//#define BAP_0 HREG_DATA_0 //Used by DMA controller to access NIC RAM 155#define BAP_1 HREG_DATA_1 //Used by HCF to access NIC RAM 156 157 158/ 159#if HCF_EXT_INT_TX_EX != HREG_EV_TX_EXC 160err: these values should match; 161#endif // HCF_EXT_INT_TX_EX / HREG_EV_TX_EXC 162 163#if HCF_EXT_INT_TICK != HREG_EV_TICK 164err: these values should match; 165#endif // HCF_EXT_INT_TICK / HREG_EV_TICK 166 167//************************* Host Software 168#define HREG_SW_0 0x28 // 169#define HREG_SW_1 0x2A // 170#define HREG_SW_2 0x2C // 171//rsrvd #define HREG_SW_3 0x2E // 172//************************* Control and Auxiliary Port 173 174#define HREG_IO 0x12 175#define HREG_IO_SRESET 0x0001 176#define HREG_IO_WAKEUP_ASYNC 0x0002 177#define HREG_IO_WOKEN_UP 0x0004 178#define HREG_CNTL 0x14 // 179//#define HREG_CNTL_WAKEUP_SYNC 0x0001 180#define HREG_CNTL_AUX_ENA_STAT 0xC000 181#define HREG_CNTL_AUX_DIS_STAT 0x0000 182#define HREG_CNTL_AUX_ENA_CNTL 0x8000 183#define HREG_CNTL_AUX_DIS_CNTL 0x4000 184#define HREG_CNTL_AUX_DSD 0x2000 185#define HREG_CNTL_AUX_ENA (HREG_CNTL_AUX_ENA_CNTL | HREG_CNTL_AUX_DIS_CNTL ) 186#define HREG_SPARE 0x16 // 187#define HREG_AUX_PAGE 0x3A // 188#define HREG_AUX_OFFSET 0x3C // 189#define HREG_AUX_DATA 0x3E // 190 191#if HCF_DMA 192//************************* DMA (bus mastering) 193 // Be carefull to use these registers only at a genuine 32 bits NIC 194 // On 16 bits NICs, these addresses are mapped into the range 0x00 through 0x3F with all consequences 195 // thereof, e.g. HREG_DMA_CTRL register maps to HREG_CMD. 196#define HREG_DMA_CTRL 0x0040 197#define HREG_TXDMA_PTR32 0x0044 198#define HREG_TXDMA_PRIO_PTR32 0x0048 199#define HREG_TXDMA_HIPRIO_PTR32 0x004C 200#define HREG_RXDMA_PTR32 0x0050 201#define HREG_CARDDETECT_1 0x007C // contains 7D37 202#define HREG_CARDDETECT_2 0x007E // contains 7DE7 203#define HREG_FREETIMER 0x0058 204#define HREG_DMA_RX_CNT 0x0026 205 206/****************************************************************************** 207* Defines for the bits in the DmaControl register (@40h) 208******************************************************************************/ 209#define HREG_DMA_CTRL_RXHWEN 0x80000000 // high word enable bit 210#define HREG_DMA_CTRL_RXRESET 0x40000000 // tx dma init bit 211#define HREG_DMA_CTRL_RXBAP1 BIT29 212#define HREG_DMA_CTRL_RX_STALLED BIT28 213#define HREG_DMA_CTRL_RXAUTOACK_DMADONE BIT27 // no host involvement req. for TDMADONE event 214#define HREG_DMA_CTRL_RXAUTOACK_INFO BIT26 // no host involvement req. for alloc event 215#define HREG_DMA_CTRL_RXAUTOACK_DMAEN 0x02000000 // no host involvement req. for TxDMAen event 216#define HREG_DMA_CTRL_RXAUTOACK_RX 0x01000000 // no host involvement req. for tx event 217#define HREG_DMA_CTRL_RX_BUSY BIT23 // read only bit 218//#define HREG_DMA_CTRL_RX_RBUFCONT_PLAIN 0 // bits 21..20 219//#define HREG_DMA_CTRL_RX_MODE_PLAIN_DMA 0 // mode 0 220#define HREG_DMA_CTRL_RX_MODE_SINGLE_PACKET 0x00010000 // mode 1 221#define HREG_DMA_CTRL_RX_MODE_MULTI_PACKET 0x00020000 // mode 2 222//#define HREG_DMA_CTRL_RX_MODE_DISABLE (0x00020000|0x00010000) // disable tx dma engine 223#define HREG_DMA_CTRL_TXHWEN 0x8000 // low word enable bit 224#define HREG_DMA_CTRL_TXRESET 0x4000 // rx dma init bit 225#define HREG_DMA_CTRL_TXBAP1 BIT13 226#define HREG_DMA_CTRL_TXAUTOACK_DMADONE BIT11 // no host involvement req. for RxDMADONE event 227#define HREG_DMA_CTRL_TXAUTOACK_DMAEN 0x00000400 // no host involvement req. for RxDMAen event 228#define HREG_DMA_CTRL_TXAUTOACK_DMAALLOC 0x00000200 // no host involvement req. for info event 229#define HREG_DMA_CTRL_TXAUTOACK_TX 0x00000100 // no host involvement req. for rx event 230#define HREG_DMA_CTRL_TX_BUSY BIT7 // read only bit 231//#define HREG_DMA_CTRL_TX_TBUFCONT_PLAIN 0 // bits 6..5 232//#define HREG_DMA_CTRL_TX_MODE_PLAIN_DMA 0 // mode 0 233#define HREG_DMA_CTRL_TX_MODE_SINGLE_PACKET BIT0 // mode 1 234#define HREG_DMA_CTRL_TX_MODE_MULTI_PACKET 0x00000002 // mode 2 235//#define HREG_DMA_CTRL_TX_MODE_DISABLE (0x00000001|0x00000002) // disable tx dma engine 236 237//configuration DWORD to configure DMA for mode2 operation, using BAP0 as the DMA BAP. 238#define DMA_CTRLSTAT_GO (HREG_DMA_CTRL_RXHWEN | HREG_DMA_CTRL_RX_MODE_MULTI_PACKET | \ 239 HREG_DMA_CTRL_RXAUTOACK_DMAEN | HREG_DMA_CTRL_RXAUTOACK_RX | \ 240 HREG_DMA_CTRL_TXHWEN | /*;?HREG_DMA_CTRL_TX_TBUFCONT_PLAIN |*/ \ 241 HREG_DMA_CTRL_TX_MODE_MULTI_PACKET | HREG_DMA_CTRL_TXAUTOACK_DMAEN |\ 242 HREG_DMA_CTRL_TXAUTOACK_DMAALLOC) 243 244//configuration DWORD to reset both the Tx and Rx DMA engines 245#define DMA_CTRLSTAT_RESET (HREG_DMA_CTRL_RXHWEN | HREG_DMA_CTRL_RXRESET | HREG_DMA_CTRL_TXHWEN | HREG_DMA_CTRL_TXRESET) 246 247//#define DESC_DMA_OWNED 0x80000000 // BIT31 248#define DESC_DMA_OWNED 0x8000 // BIT31 249#define DESC_SOP 0x8000 // BIT15 250#define DESC_EOP 0x4000 // BIT14 251 252#define DMA_RX 0 253#define DMA_TX 1 254 255// #define IFB_RxFirstDesc IFB_FirstDesc[DMA_RX] 256// #define IFB_TxFirstDesc IFB_FirstDesc[DMA_TX] 257// #define IFB_RxLastDesc IFB_LastDesc[DMA_RX] 258// #define IFB_TxLastDesc IFB_LastDesc[DMA_TX] 259 260#endif // HCF_DMA 261// 262/************************************************************************************************/ 263/********************************** EQUATES ***************************************************/ 264/************************************************************************************************/ 265 266 267// Hermes Command Codes and Qualifier bits 268#define HCMD_BUSY 0x8000 // Busy bit, applicable for all commands 269#define HCMD_INI 0x0000 // 270#define HCMD_ENABLE HCF_CNTL_ENABLE // 0x0001 271#define HCMD_DISABLE HCF_CNTL_DISABLE // 0x0002 272#define HCMD_CONNECT HCF_CNTL_CONNECT // 0x0003 273#define HCMD_EXECUTE 0x0004 // 274#define HCMD_DISCONNECT HCF_CNTL_DISCONNECT // 0x0005 275#define HCMD_SLEEP 0x0006 // 276#define HCMD_CONTINUE HCF_CNTL_CONTINUE // 0x0007 277#define HCMD_RETRY 0x0100 // Retry bit 278#define HCMD_ALLOC 0x000A // 279#define HCMD_TX 0x000B // 280#define HCMD_RECL 0x0100 // Reclaim bit, applicable for Tx and Inquire 281#define HCMD_INQUIRE 0x0011 // 282#define HCMD_ACCESS 0x0021 // 283#define HCMD_ACCESS_WRITE 0x0100 // Write bit 284#define HCMD_PROGRAM 0x0022 // 285#define HCMD_READ_MIF 0x0030 286#define HCMD_WRITE_MIF 0x0031 287#define HCMD_THESEUS 0x0038 288#define HCMD_STARTPREAMBLE 0x0E00 // Start continuous preamble Tx 289#define HCMD_STOP 0x0F00 // Stop Theseus test mode 290 291 292//Configuration Management 293// 294 295#define CFG_DRV_ACT_RANGES_PRI_3_BOTTOM 1 // Default Bottom Compatibility for Primary Firmware - driver I/F 296#define CFG_DRV_ACT_RANGES_PRI_3_TOP 1 // Default Top Compatibility for Primary Firmware - driver I/F 297 298#define CFG_DRV_ACT_RANGES_HSI_4_BOTTOM 1 // Default Bottom Compatibility for H/W - driver I/F 299#define CFG_DRV_ACT_RANGES_HSI_4_TOP 1 // Default Top Compatibility for H/W - driver I/F 300 301#define CFG_DRV_ACT_RANGES_HSI_5_BOTTOM 1 // Default Bottom Compatibility for H/W - driver I/F 302#define CFG_DRV_ACT_RANGES_HSI_5_TOP 1 // Default Top Compatibility for H/W - driver I/F 303 304#if (HCF_TYPE) & HCF_TYPE_WPA 305#define CFG_DRV_ACT_RANGES_APF_1_BOTTOM 16 // Default Bottom Compatibility for AP Firmware - driver I/F 306#define CFG_DRV_ACT_RANGES_APF_1_TOP 16 // Default Top Compatibility for AP Firmware - driver I/F 307#else //;? is this REALLY O.K. 308#define CFG_DRV_ACT_RANGES_APF_1_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F 309#define CFG_DRV_ACT_RANGES_APF_1_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F 310#endif // HCF_TYPE_WPA 311 312#define CFG_DRV_ACT_RANGES_APF_2_BOTTOM 2 // Default Bottom Compatibility for AP Firmware - driver I/F 313#define CFG_DRV_ACT_RANGES_APF_2_TOP 2 // Default Top Compatibility for AP Firmware - driver I/F 314 315#define CFG_DRV_ACT_RANGES_APF_3_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F 316#define CFG_DRV_ACT_RANGES_APF_3_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F 317 318#define CFG_DRV_ACT_RANGES_APF_4_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F 319#define CFG_DRV_ACT_RANGES_APF_4_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F 320 321#if (HCF_TYPE) & HCF_TYPE_HII5 322#define CFG_DRV_ACT_RANGES_STA_2_BOTTOM 6 // Default Bottom Compatibility for Station Firmware - driver I/F 323#define CFG_DRV_ACT_RANGES_STA_2_TOP 6 // Default Top Compatibility for Station Firmware - driver I/F 324#else // (HCF_TYPE) & HCF_TYPE_HII5 325#define CFG_DRV_ACT_RANGES_STA_2_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F 326#define CFG_DRV_ACT_RANGES_STA_2_TOP 2 // Default Top Compatibility for Station Firmware - driver I/F 327#endif // (HCF_TYPE) & HCF_TYPE_HII5 328 329#define CFG_DRV_ACT_RANGES_STA_3_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F 330#define CFG_DRV_ACT_RANGES_STA_3_TOP 1 // Default Top Compatibility for Station Firmware - driver I/F 331 332#define CFG_DRV_ACT_RANGES_STA_4_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F 333#define CFG_DRV_ACT_RANGES_STA_4_TOP 1 // Default Top Compatibility for Station Firmware - driver I/F 334 335//--------------------------------------------------------------------------------------------------------------------- 336#if defined HCF_CFG_PRI_1_TOP || defined HCF_CFG_PRI_1_BOTTOM 337err: PRI_1 not supported for H-I; // Compatibility for Primary Firmware - driver I/F 338#endif // HCF_CFG_PRI_1_TOP / HCF_CFG_PRI_1_BOTTOM 339 340#if defined HCF_CFG_PRI_2_TOP || defined HCF_CFG_PRI_2_BOTTOM 341err: PRI_2 not supported for H-I; // Compatibility for Primary Firmware - driver I/F 342#endif // HCF_CFG_PRI_2_TOP / HCF_CFG_PRI_2_BOTTOM 343 344#ifdef HCF_CFG_PRI_3_TOP // Top Compatibility for Primary Firmware - driver I/F 345#if HCF_CFG_PRI_3_TOP == 0 || CFG_DRV_ACT_RANGES_PRI_3_BOTTOM <= HCF_CFG_PRI_3_TOP && \ 346 HCF_CFG_PRI_3_TOP <= CFG_DRV_ACT_RANGES_PRI_3_TOP 347#undef CFG_DRV_ACT_RANGES_PRI_3_TOP 348#define CFG_DRV_ACT_RANGES_PRI_3_TOP HCF_CFG_PRI_3_TOP 349#else 350err: ; 351#endif 352#endif // HCF_CFG_PRI_3_TOP 353 354#ifdef HCF_CFG_PRI_3_BOTTOM // Bottom Compatibility for Primary Firmware - driver I/F 355#if CFG_DRV_ACT_RANGES_PRI_3_BOTTOM <= HCF_CFG_PRI_3_BOTTOM && HCF_CFG_PRI_3_BOTTOM <= \ 356 CFG_DRV_ACT_RANGES_PRI_3_TOP 357#undef CFG_DRV_ACT_RANGES_PRI_3_BOTTOM 358#define CFG_DRV_ACT_RANGES_PRI_3_BOTTOM HCF_CFG_PRI_3_BOTTOM 359#else 360err: ; 361#endif 362#endif // HCF_CFG_PRI_3_BOTTOM 363 364 365//--------------------------------------------------------------------------------------------------------------------- 366#if defined HCF_CFG_HSI_0_TOP || defined HCF_CFG_HSI_0_BOTTOM 367err: HSI_0 not supported for H-I; // Compatibility for HSI I/F 368#endif // HCF_CFG_HSI_0_TOP / HCF_CFG_HSI_0_BOTTOM 369 370#if defined HCF_CFG_HSI_1_TOP || defined HCF_CFG_HSI_1_BOTTOM 371err: HSI_1 not supported for H-I; // Compatibility for HSI I/F 372#endif // HCF_CFG_HSI_1_TOP / HCF_CFG_HSI_1_BOTTOM 373 374#if defined HCF_CFG_HSI_2_TOP || defined HCF_CFG_HSI_2_BOTTOM 375err: HSI_2 not supported for H-I; // Compatibility for HSI I/F 376#endif // HCF_CFG_HSI_2_TOP / HCF_CFG_HSI_2_BOTTOM 377 378#if defined HCF_CFG_HSI_3_TOP || defined HCF_CFG_HSI_3_BOTTOM 379err: HSI_3 not supported for H-I; // Compatibility for HSI I/F 380#endif // HCF_CFG_HSI_3_TOP / HCF_CFG_HSI_3_BOTTOM 381 382#ifdef HCF_CFG_HSI_4_TOP // Top Compatibility for HSI I/F 383#if HCF_CFG_HSI_4_TOP == 0 || CFG_DRV_ACT_RANGES_HSI_4_BOTTOM <= CF_CFG_HSI_4_TOP && \ 384 HCF_CFG_HSI_4_TOP <= CFG_DRV_ACT_RANGES_HSI_4_TOP 385#undef CFG_DRV_ACT_RANGES_HSI_4_TOP 386#define CFG_DRV_ACT_RANGES_HSI_4_TOP HCF_CFG_HSI_4_TOP 387#else 388err: ; 389#endif 390#endif // HCF_CFG_HSI_4_TOP 391 392#ifdef HCF_CFG_HSI_4_BOTTOM // Bottom Compatibility for HSI I/F 393#if CFG_DRV_ACT_RANGES_HSI_4_BOTTOM <= HCF_CFG_HSI_4_BOTTOM && HCF_CFG_HSI_4_BOTTOM <= \ 394 CFG_DRV_ACT_RANGES_HSI_4_TOP 395#undef CFG_DRV_ACT_RANGES_HSI_4_BOTTOM 396#define CFG_DRV_ACT_RANGES_HSI_4_BOTTOM HCF_CFG_HSI_4_BOTTOM 397#else 398err: ; 399#endif 400#endif // HCF_CFG_HSI_4_BOTTOM 401 402#ifdef HCF_CFG_HSI_5_TOP // Top Compatibility for HSI I/F 403#if HCF_CFG_HSI_5_TOP == 0 || CFG_DRV_ACT_RANGES_HSI_5_BOTTOM <= CF_CFG_HSI_5_TOP && \ 404 HCF_CFG_HSI_5_TOP <= CFG_DRV_ACT_RANGES_HSI_5_TOP 405#undef CFG_DRV_ACT_RANGES_HSI_5_TOP 406#define CFG_DRV_ACT_RANGES_HSI_5_TOP HCF_CFG_HSI_5_TOP 407#else 408err: ; 409#endif 410#endif // HCF_CFG_HSI_5_TOP 411 412#ifdef HCF_CFG_HSI_5_BOTTOM // Bottom Compatibility for HSI I/F 413#if CFG_DRV_ACT_RANGES_HSI_5_BOTTOM <= HCF_CFG_HSI_5_BOTTOM && HCF_CFG_HSI_5_BOTTOM <= \ 414 CFG_DRV_ACT_RANGES_HSI_5_TOP 415#undef CFG_DRV_ACT_RANGES_HSI_5_BOTTOM 416#define CFG_DRV_ACT_RANGES_HSI_5_BOTTOM HCF_CFG_HSI_5_BOTTOM 417#else 418err: ; 419#endif 420#endif // HCF_CFG_HSI_5_BOTTOM 421//--------------------------------------------------------------------------------------------------------------------- 422#if defined HCF_CFG_APF_1_TOP || defined HCF_CFG_APF_1_BOTTOM 423err: APF_1 not supported for H-I; // Compatibility for AP Firmware - driver I/F 424#endif // HCF_CFG_APF_1_TOP / HCF_CFG_APF_1_BOTTOM 425 426#ifdef HCF_CFG_APF_2_TOP // Top Compatibility for AP Firmware - driver I/F 427#if HCF_CFG_APF_2_TOP == 0 || CFG_DRV_ACT_RANGES_APF_2_BOTTOM <= HCF_CFG_APF_2_TOP && \ 428 HCF_CFG_APF_2_TOP <= CFG_DRV_ACT_RANGES_APF_2_TOP 429#undef CFG_DRV_ACT_RANGES_APF_2_TOP 430#define CFG_DRV_ACT_RANGES_APF_2_TOP HCF_CFG_APF_2_TOP 431#else 432err: ; 433#endif 434#endif // HCF_CFG_APF_TOP 435 436#ifdef HCF_CFG_APF_2_BOTTOM // Bottom Compatibility for AP Firmware - driver I/F 437#if CFG_DRV_ACT_RANGES_APF_2_BOTTOM <= HCF_CFG_APF_2_BOTTOM && HCF_CFG_APF_2_BOTTOM <= \ 438 CFG_DRV_ACT_RANGES_APF_2_TOP 439#undef CFG_DRV_ACT_RANGES_APF_2_BOTTOM 440#define CFG_DRV_ACT_RANGES_APF_2_BOTTOM HCF_CFG_APF_2_BOTTOM 441#else 442err: ; 443#endif 444#endif // HCF_CFG_APF_BOTTOM 445 446//--------------------------------------------------------------------------------------------------------------------- 447#if defined HCF_CFG_STA_1_TOP || defined HCF_CFG_STA_1_BOTTOM 448err: STA_1 not supported for H-I; // Compatibility for Station Firmware - driver I/F 449#endif // HCF_CFG_STA_1_TOP / HCF_CFG_STA_1_BOTTOM 450 451#ifdef HCF_CFG_STA_2_TOP // Top Compatibility for Station Firmware - driver I/F 452#if HCF_CFG_STA_2_TOP == 0 || CFG_DRV_ACT_RANGES_STA_2_BOTTOM <= HCF_CFG_STA_2_TOP && \ 453 HCF_CFG_STA_2_TOP <= CFG_DRV_ACT_RANGES_STA_2_TOP 454#undef CFG_DRV_ACT_RANGES_STA_2_TOP 455#define CFG_DRV_ACT_RANGES_STA_2_TOP HCF_CFG_STA_2_TOP 456#else 457err: ; 458#endif 459#endif // HCF_CFG_STA_TOP 460 461#ifdef HCF_CFG_STA_2_BOTTOM // Bottom Compatibility for Station Firmware - driver I/F 462#if CFG_DRV_ACT_RANGES_STA_2_BOTTOM <= HCF_CFG_STA_2_BOTTOM && HCF_CFG_STA_2_BOTTOM <= \ 463 CFG_DRV_ACT_RANGES_STA_2_TOP 464#undef CFG_DRV_ACT_RANGES_STA_2_BOTTOM 465#define CFG_DRV_ACT_RANGES_STA_2_BOTTOM HCF_CFG_STA_2_BOTTOM 466#else 467err: ; 468#endif 469#endif // HCF_CFG_STA_BOTTOM 470 471 472/************************************************************************************************/ 473/************************************** MACROS ************************************************/ 474/************************************************************************************************/ 475 476/* min and max macros */ 477#if ! defined max 478#define max(a,b) (((a) > (b)) ? (a) : (b)) 479#endif 480#if ! defined min 481#define min(a,b) (((a) < (b)) ? (a) : (b)) 482#endif 483 484#ifdef HCF_SLEEP 485#if defined MSF_WAIT 486err: MSF should no longer supply this macro; 487#else 488#define MSF_WAIT(x) \ 489 { PROT_CNT_INI \ 490 HCF_WAIT_WHILE( ( IPW( HREG_IO ) & HREG_IO_WOKEN_UP ) == 0 ); \ 491 HCFASSERT( prot_cnt, IPW( HREG_IO ) ) \ 492 } 493#endif // MSF_WAIT 494#else 495#define MSF_WAIT(x) /*NOP*/ 496#endif // HCF_SLEEP 497 498#define LOF(x) (sizeof(x)/sizeof(hcf_16)-1) 499 500#define MUL_BY_2( x ) ( (x) << 1 ) //used to multiply by 2 501#define DIV_BY_2( x ) ( (x) >> 1 ) //used to divide by 2 502 503//resolve problems on for some 16 bits compilers to create 32 bit values 504#define MERGE_2( hw, lw ) ( ( ((hcf_32)(hw)) << 16 ) | ((hcf_16)(lw)) ) 505 506#if ! defined HCF_STATIC 507#define HCF_STATIC static 508#endif // HCF_STATIC 509 510#if ( (HCF_TYPE) & HCF_TYPE_HII5 ) == 0 511#define DAWA_ACK( mask) { \ 512 OPW( HREG_EV_ACK, mask | HREG_EV_ACK_REG_READY ); \ 513 OPW( HREG_EV_ACK, (mask & ~HREG_EV_ALLOC) | HREG_EV_ACK_REG_READY ); } 514#define DAWA_ZERO_FID(reg) OPW( reg, 0 ); 515#else 516#define DAWA_ACK( mask) OPW( HREG_EV_ACK, mask ); 517#define DAWA_ZERO_FID(reg) 518#endif // HCF_TYPE_HII5 519 520#if (HCF_TYPE) & HCF_TYPE_WPA 521#define CALC_RX_MIC( p, len ) calc_mic_rx_frag( ifbp, p, len ) 522#define CALC_TX_MIC( p, len ) calc_mic_tx_frag( ifbp, p, len ) 523#define IF_SSN(x) x 524#define IF_NOT_SSN(x) 525#else 526#define CALC_RX_MIC( p, len ) 527#define CALC_TX_MIC( p, len ) 528#define MIC_RX_RTN( mic, dw ) 529#define MIC_TX_RTN( mic, dw ) 530#define IF_SSN(x) 531#define IF_NOT_SSN(x) x 532#endif // HCF_TYPE_WPA 533 534#if HCF_TALLIES & HCF_TALLIES_HCF //HCF tally support 535#define IF_TALLY(x) x 536#else 537#define IF_TALLY(x) 538#endif // HCF_TALLIES_HCF 539 540 541#if HCF_DMA 542#define IF_DMA(x) x 543#define IF_NOT_DMA(x) 544#define IF_USE_DMA(x) if ( ifbp->IFB_CntlOpt & USE_DMA ) x 545#define IF_NOT_USE_DMA(x) if ( !(ifbp->IFB_CntlOpt & USE_DMA) ) x 546#else 547#define IF_DMA(x) 548#define IF_NOT_DMA(x) x 549#define IF_USE_DMA(x) 550#define IF_NOT_USE_DMA(x) x 551#endif // HCF_DMA 552 553 554#define IPW(x) ((hcf_16)IN_PORT_WORD( ifbp->IFB_IOBase + (x) ) ) 555#define OPW(x, y) OUT_PORT_WORD( ifbp->IFB_IOBase + (x), y ) 556 /* make sure the implementation of HCF_WAIT_WHILE is such that there may be multiple HCF_WAIT_WHILE calls 557 * in a row and that when one fails all subsequent fail immediately without reinitialization of prot_cnt 558 */ 559#if HCF_PROT_TIME == 0 560#define PROT_CNT_INI 561#define IF_PROT_TIME(x) 562#if defined HCF_YIELD 563#define HCF_WAIT_WHILE( x ) while ( (x) && (HCF_YIELD) ) /*NOP*/; 564#else 565#define HCF_WAIT_WHILE( x ) while ( x ) /*NOP*/; 566#endif // HCF_YIELD 567#else 568#define PROT_CNT_INI hcf_32 prot_cnt = ifbp->IFB_TickIni; 569#define IF_PROT_TIME(x) x 570#if defined HCF_YIELD 571#define HCF_WAIT_WHILE( x ) while ( prot_cnt && (x) && (HCF_YIELD) ) prot_cnt--; 572#else 573#include <linux/delay.h> 574#define HCF_WAIT_WHILE( x ) while ( prot_cnt && (x) ) { udelay(2); prot_cnt--; } 575#endif // HCF_YIELD 576#endif // HCF_PROT_TIME 577 578#if defined HCF_EX_INT 579//#if HCF_EX_INT & ~( HCF_EX_INT_TX_EX | HCF_EX_INT_TX_OK | HCF_EX_INT_TICK ) 580;? out dated checking 581err: you used an invalid bitmask; 582// #endif // HCF_EX_INT validation 583// #else 584// #define HCF_EX_INT 0x000 585#endif // HCF_EX_INT 586 587 588 589/* The assert in HCFLOGENTRY checks against re-entrancy. Re-entrancy could be caused by MSF logic at 590 * task-level calling hcf_functions without shielding with HCF_ACT_ON/_OFF. When an interrupt occurs, 591 * the ISR could (either directly or indirectly) cause re-entering of the interrupted HCF-routine. 592 * 593 * The "(ifbp->IFB_AssertWhere = where)" test in HCFLOGENTRY services ALSO as a statement to get around: 594 * #pragma warning: conditional expression is constant 595 * on the if-statement 596 */ 597#if HCF_ASSERT 598#define HCFASSERT(x,q) {if (!(x)) {mdd_assert( ifbp, __LINE__ , q );}} 599#define MMDASSERT(x,q) {if (!(x)) {mdd_assert( assert_ifbp, __LINE__ + FILE_NAME_OFFSET, q );}} 600 601#define HCFLOGENTRY( where, what ) \ 602{if ( (ifbp->IFB_AssertWhere = where) <= 15 ) { \ 603 HCF_ENTRY( ifbp ); \ 604 HCFASSERT( (ifbp->IFB_AssertTrace & 1<<((where)&0xF)) == 0, ifbp->IFB_AssertTrace ); \ 605 ifbp->IFB_AssertTrace |= 1<<((where)&0xF); \ 606 } \ 607HCFTRACE(ifbp, where ) \ 608HCFTRACEVALUE(ifbp, what ) \ 609} 610 611#define HCFLOGEXIT( where ) \ 612{if ( (ifbp->IFB_AssertWhere = where) <= 15 ) { \ 613 HCF_EXIT( ifbp ); \ 614 ifbp->IFB_AssertTrace &= ~(1<<((where)&0xF)); \ 615 } \ 616HCFTRACE(ifbp, (where)|HCF_TRACE_EXIT ) \ 617} 618 619#else // HCF_ASSERT 620#define HCFASSERT( x, q ) 621#define MMDASSERT( x, q ) 622#define HCFLOGENTRY( where, what ) {HCF_ENTRY( ifbp );} 623#define HCFLOGEXIT( where ) {HCF_EXIT( ifbp );} 624#endif // HCF_ASSERT 625 626#if HCF_INT_ON 627/* ;? HCFASSERT_INT 628 * #if (HCF_SLEEP) & HCF_DDS 629 * #define HCFASSERT_INT HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFF && ifbp->IFB_IntOffCnt != 0xFFFE, \ 630 * ifbp->IFB_IntOffCnt ) 631 * #else 632 */ 633#define HCFASSERT_INT HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFF, ifbp->IFB_IntOffCnt ) 634// #endif // HCF_DDS 635#else 636#define HCFASSERT_INT 637#endif // HCF_INT_ON 638 639 640#if defined HCF_TRACE 641#define HCFTRACE(ifbp, where ) {OPW( HREG_SW_1, where );} 642//#define HCFTRACE(ifbp, where ) {HCFASSERT( DO_ASSERT, where );} 643#define HCFTRACEVALUE(ifbp, what ) {OPW( HREG_SW_2, what );} 644//#define HCFTRACEVALUE(ifbp, what ) {HCFASSERT( DO_ASSERT, what );} 645#else 646#define HCFTRACE(ifbp, where ) 647#define HCFTRACEVALUE(ifbp, what ) 648#endif // HCF_TRACE 649 650 651#if HCF_BIG_ENDIAN 652#define BE_PAR(x) ,x 653#else 654#define BE_PAR(x) 655#endif // HCF_BIG_ENDIAN 656 657/************************************************************************************************/ 658/************************************** END OF MACROS *****************************************/ 659/************************************************************************************************/ 660 661/************************************************************************************************/ 662/*************************************** PROTOTYPES *******************************************/ 663/************************************************************************************************/ 664 665#if HCF_ASSERT 666extern IFBP BASED assert_ifbp; //to make asserts easily work under MMD and DHF 667EXTERN_C void mdd_assert (IFBP ifbp, unsigned int line_number, hcf_32 q ); 668#endif //HCF_ASSERT 669 670#if ! ( (HCF_IO) & HCF_IO_32BITS ) // defined 16 bits only 671#undef OUT_PORT_STRING_32 672#undef IN_PORT_STRING_32 673#endif // HCF_IO 674#endif //HCFDEFC_H 675