1/* 2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk> 3 * 4 * lirc_sir - Device driver for use with SIR (serial infra red) 5 * mode of IrDA on many notebooks. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 * 22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> : 23 * added timeout and relaxed pulse detection, removed gap bug 24 * 25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> : 26 * added support for Tekram Irmate 210 (sending does not work yet, 27 * kind of disappointing that nobody was able to implement that 28 * before), 29 * major clean-up 30 * 31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> : 32 * added support for StrongARM SA1100 embedded microprocessor 33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King 34 */ 35 36#include <linux/module.h> 37#include <linux/sched.h> 38#include <linux/errno.h> 39#include <linux/signal.h> 40#include <linux/fs.h> 41#include <linux/interrupt.h> 42#include <linux/ioport.h> 43#include <linux/kernel.h> 44#include <linux/serial_reg.h> 45#include <linux/time.h> 46#include <linux/string.h> 47#include <linux/types.h> 48#include <linux/wait.h> 49#include <linux/mm.h> 50#include <linux/delay.h> 51#include <linux/poll.h> 52#include <asm/system.h> 53#include <linux/io.h> 54#include <asm/irq.h> 55#include <linux/fcntl.h> 56#ifdef LIRC_ON_SA1100 57#include <asm/hardware.h> 58#ifdef CONFIG_SA1100_COLLIE 59#include <asm/arch/tc35143.h> 60#include <asm/ucb1200.h> 61#endif 62#endif 63 64#include <linux/timer.h> 65 66#include <media/lirc.h> 67#include <media/lirc_dev.h> 68 69/* SECTION: Definitions */ 70 71/*** Tekram dongle ***/ 72#ifdef LIRC_SIR_TEKRAM 73/* stolen from kernel source */ 74/* definitions for Tekram dongle */ 75#define TEKRAM_115200 0x00 76#define TEKRAM_57600 0x01 77#define TEKRAM_38400 0x02 78#define TEKRAM_19200 0x03 79#define TEKRAM_9600 0x04 80#define TEKRAM_2400 0x08 81 82#define TEKRAM_PW 0x10 /* Pulse select bit */ 83 84/* 10bit * 1s/115200bit in milliseconds = 87ms*/ 85#define TIME_CONST (10000000ul/115200ul) 86 87#endif 88 89#ifdef LIRC_SIR_ACTISYS_ACT200L 90static void init_act200(void); 91#elif defined(LIRC_SIR_ACTISYS_ACT220L) 92static void init_act220(void); 93#endif 94 95/*** SA1100 ***/ 96#ifdef LIRC_ON_SA1100 97struct sa1100_ser2_registers { 98 /* HSSP control register */ 99 unsigned char hscr0; 100 /* UART registers */ 101 unsigned char utcr0; 102 unsigned char utcr1; 103 unsigned char utcr2; 104 unsigned char utcr3; 105 unsigned char utcr4; 106 unsigned char utdr; 107 unsigned char utsr0; 108 unsigned char utsr1; 109} sr; 110 111static int irq = IRQ_Ser2ICP; 112 113#define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0 114 115/* pulse/space ratio of 50/50 */ 116static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY); 117/* 1000000/freq-pulse_width */ 118static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY); 119static unsigned int freq = 38000; /* modulation frequency */ 120static unsigned int duty_cycle = 50; /* duty cycle of 50% */ 121 122#endif 123 124#define RBUF_LEN 1024 125#define WBUF_LEN 1024 126 127#define LIRC_DRIVER_NAME "lirc_sir" 128 129#define PULSE '[' 130 131#ifndef LIRC_SIR_TEKRAM 132/* 9bit * 1s/115200bit in milli seconds = 78.125ms*/ 133#define TIME_CONST (9000000ul/115200ul) 134#endif 135 136 137/* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */ 138#define SIR_TIMEOUT (HZ*5/100) 139 140#ifndef LIRC_ON_SA1100 141#ifndef LIRC_IRQ 142#define LIRC_IRQ 4 143#endif 144#ifndef LIRC_PORT 145/* for external dongles, default to com1 */ 146#if defined(LIRC_SIR_ACTISYS_ACT200L) || defined(LIRC_SIR_ACTISYS_ACT220L) || \ 147 defined(LIRC_SIR_TEKRAM) 148#define LIRC_PORT 0x3f8 149#else 150/* onboard sir ports are typically com3 */ 151#define LIRC_PORT 0x3e8 152#endif 153#endif 154 155static int io = LIRC_PORT; 156static int irq = LIRC_IRQ; 157static int threshold = 3; 158#endif 159 160static DEFINE_SPINLOCK(timer_lock); 161static struct timer_list timerlist; 162/* time of last signal change detected */ 163static struct timeval last_tv = {0, 0}; 164/* time of last UART data ready interrupt */ 165static struct timeval last_intr_tv = {0, 0}; 166static int last_value; 167 168static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue); 169 170static DEFINE_SPINLOCK(hardware_lock); 171 172static int rx_buf[RBUF_LEN]; 173static unsigned int rx_tail, rx_head; 174 175static int debug; 176#define dprintk(fmt, args...) \ 177 do { \ 178 if (debug) \ 179 printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ 180 fmt, ## args); \ 181 } while (0) 182 183/* SECTION: Prototypes */ 184 185/* Communication with user-space */ 186static unsigned int lirc_poll(struct file *file, poll_table *wait); 187static ssize_t lirc_read(struct file *file, char *buf, size_t count, 188 loff_t *ppos); 189static ssize_t lirc_write(struct file *file, const char *buf, size_t n, 190 loff_t *pos); 191static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); 192static void add_read_queue(int flag, unsigned long val); 193static int init_chrdev(void); 194static void drop_chrdev(void); 195/* Hardware */ 196static irqreturn_t sir_interrupt(int irq, void *dev_id); 197static void send_space(unsigned long len); 198static void send_pulse(unsigned long len); 199static int init_hardware(void); 200static void drop_hardware(void); 201/* Initialisation */ 202static int init_port(void); 203static void drop_port(void); 204 205#ifdef LIRC_ON_SA1100 206static void on(void) 207{ 208 PPSR |= PPC_TXD2; 209} 210 211static void off(void) 212{ 213 PPSR &= ~PPC_TXD2; 214} 215#else 216static inline unsigned int sinp(int offset) 217{ 218 return inb(io + offset); 219} 220 221static inline void soutp(int offset, int value) 222{ 223 outb(value, io + offset); 224} 225#endif 226 227#ifndef MAX_UDELAY_MS 228#define MAX_UDELAY_US 5000 229#else 230#define MAX_UDELAY_US (MAX_UDELAY_MS*1000) 231#endif 232 233static void safe_udelay(unsigned long usecs) 234{ 235 while (usecs > MAX_UDELAY_US) { 236 udelay(MAX_UDELAY_US); 237 usecs -= MAX_UDELAY_US; 238 } 239 udelay(usecs); 240} 241 242/* SECTION: Communication with user-space */ 243 244static unsigned int lirc_poll(struct file *file, poll_table *wait) 245{ 246 poll_wait(file, &lirc_read_queue, wait); 247 if (rx_head != rx_tail) 248 return POLLIN | POLLRDNORM; 249 return 0; 250} 251 252static ssize_t lirc_read(struct file *file, char *buf, size_t count, 253 loff_t *ppos) 254{ 255 int n = 0; 256 int retval = 0; 257 DECLARE_WAITQUEUE(wait, current); 258 259 if (count % sizeof(int)) 260 return -EINVAL; 261 262 add_wait_queue(&lirc_read_queue, &wait); 263 set_current_state(TASK_INTERRUPTIBLE); 264 while (n < count) { 265 if (rx_head != rx_tail) { 266 if (copy_to_user((void *) buf + n, 267 (void *) (rx_buf + rx_head), 268 sizeof(int))) { 269 retval = -EFAULT; 270 break; 271 } 272 rx_head = (rx_head + 1) & (RBUF_LEN - 1); 273 n += sizeof(int); 274 } else { 275 if (file->f_flags & O_NONBLOCK) { 276 retval = -EAGAIN; 277 break; 278 } 279 if (signal_pending(current)) { 280 retval = -ERESTARTSYS; 281 break; 282 } 283 schedule(); 284 set_current_state(TASK_INTERRUPTIBLE); 285 } 286 } 287 remove_wait_queue(&lirc_read_queue, &wait); 288 set_current_state(TASK_RUNNING); 289 return n ? n : retval; 290} 291static ssize_t lirc_write(struct file *file, const char *buf, size_t n, 292 loff_t *pos) 293{ 294 unsigned long flags; 295 int i, count; 296 int *tx_buf; 297 298 count = n / sizeof(int); 299 if (n % sizeof(int) || count % 2 == 0) 300 return -EINVAL; 301 tx_buf = memdup_user(buf, n); 302 if (IS_ERR(tx_buf)) 303 return PTR_ERR(tx_buf); 304 i = 0; 305#ifdef LIRC_ON_SA1100 306 /* disable receiver */ 307 Ser2UTCR3 = 0; 308#endif 309 local_irq_save(flags); 310 while (1) { 311 if (i >= count) 312 break; 313 if (tx_buf[i]) 314 send_pulse(tx_buf[i]); 315 i++; 316 if (i >= count) 317 break; 318 if (tx_buf[i]) 319 send_space(tx_buf[i]); 320 i++; 321 } 322 local_irq_restore(flags); 323#ifdef LIRC_ON_SA1100 324 off(); 325 udelay(1000); /* wait 1ms for IR diode to recover */ 326 Ser2UTCR3 = 0; 327 /* clear status register to prevent unwanted interrupts */ 328 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); 329 /* enable receiver */ 330 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE; 331#endif 332 return count; 333} 334 335static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 336{ 337 int retval = 0; 338 unsigned long value = 0; 339#ifdef LIRC_ON_SA1100 340 unsigned int ivalue; 341 342 if (cmd == LIRC_GET_FEATURES) 343 value = LIRC_CAN_SEND_PULSE | 344 LIRC_CAN_SET_SEND_DUTY_CYCLE | 345 LIRC_CAN_SET_SEND_CARRIER | 346 LIRC_CAN_REC_MODE2; 347 else if (cmd == LIRC_GET_SEND_MODE) 348 value = LIRC_MODE_PULSE; 349 else if (cmd == LIRC_GET_REC_MODE) 350 value = LIRC_MODE_MODE2; 351#else 352 if (cmd == LIRC_GET_FEATURES) 353 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2; 354 else if (cmd == LIRC_GET_SEND_MODE) 355 value = LIRC_MODE_PULSE; 356 else if (cmd == LIRC_GET_REC_MODE) 357 value = LIRC_MODE_MODE2; 358#endif 359 360 switch (cmd) { 361 case LIRC_GET_FEATURES: 362 case LIRC_GET_SEND_MODE: 363 case LIRC_GET_REC_MODE: 364 retval = put_user(value, (unsigned long *) arg); 365 break; 366 367 case LIRC_SET_SEND_MODE: 368 case LIRC_SET_REC_MODE: 369 retval = get_user(value, (unsigned long *) arg); 370 break; 371#ifdef LIRC_ON_SA1100 372 case LIRC_SET_SEND_DUTY_CYCLE: 373 retval = get_user(ivalue, (unsigned int *) arg); 374 if (retval) 375 return retval; 376 if (ivalue <= 0 || ivalue > 100) 377 return -EINVAL; 378 /* (ivalue/100)*(1000000/freq) */ 379 duty_cycle = ivalue; 380 pulse_width = (unsigned long) duty_cycle*10000/freq; 381 space_width = (unsigned long) 1000000L/freq-pulse_width; 382 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) 383 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; 384 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) 385 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; 386 break; 387 case LIRC_SET_SEND_CARRIER: 388 retval = get_user(ivalue, (unsigned int *) arg); 389 if (retval) 390 return retval; 391 if (ivalue > 500000 || ivalue < 20000) 392 return -EINVAL; 393 freq = ivalue; 394 pulse_width = (unsigned long) duty_cycle*10000/freq; 395 space_width = (unsigned long) 1000000L/freq-pulse_width; 396 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) 397 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; 398 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) 399 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; 400 break; 401#endif 402 default: 403 retval = -ENOIOCTLCMD; 404 405 } 406 407 if (retval) 408 return retval; 409 if (cmd == LIRC_SET_REC_MODE) { 410 if (value != LIRC_MODE_MODE2) 411 retval = -ENOSYS; 412 } else if (cmd == LIRC_SET_SEND_MODE) { 413 if (value != LIRC_MODE_PULSE) 414 retval = -ENOSYS; 415 } 416 417 return retval; 418} 419 420static void add_read_queue(int flag, unsigned long val) 421{ 422 unsigned int new_rx_tail; 423 int newval; 424 425 dprintk("add flag %d with val %lu\n", flag, val); 426 427 newval = val & PULSE_MASK; 428 429 /* 430 * statistically, pulses are ~TIME_CONST/2 too long. we could 431 * maybe make this more exact, but this is good enough 432 */ 433 if (flag) { 434 /* pulse */ 435 if (newval > TIME_CONST/2) 436 newval -= TIME_CONST/2; 437 else /* should not ever happen */ 438 newval = 1; 439 newval |= PULSE_BIT; 440 } else { 441 newval += TIME_CONST/2; 442 } 443 new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1); 444 if (new_rx_tail == rx_head) { 445 dprintk("Buffer overrun.\n"); 446 return; 447 } 448 rx_buf[rx_tail] = newval; 449 rx_tail = new_rx_tail; 450 wake_up_interruptible(&lirc_read_queue); 451} 452 453static const struct file_operations lirc_fops = { 454 .owner = THIS_MODULE, 455 .read = lirc_read, 456 .write = lirc_write, 457 .poll = lirc_poll, 458 .unlocked_ioctl = lirc_ioctl, 459 .open = lirc_dev_fop_open, 460 .release = lirc_dev_fop_close, 461}; 462 463static int set_use_inc(void *data) 464{ 465 return 0; 466} 467 468static void set_use_dec(void *data) 469{ 470} 471 472static struct lirc_driver driver = { 473 .name = LIRC_DRIVER_NAME, 474 .minor = -1, 475 .code_length = 1, 476 .sample_rate = 0, 477 .data = NULL, 478 .add_to_buf = NULL, 479 .set_use_inc = set_use_inc, 480 .set_use_dec = set_use_dec, 481 .fops = &lirc_fops, 482 .dev = NULL, 483 .owner = THIS_MODULE, 484}; 485 486 487static int init_chrdev(void) 488{ 489 driver.minor = lirc_register_driver(&driver); 490 if (driver.minor < 0) { 491 printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n"); 492 return -EIO; 493 } 494 return 0; 495} 496 497static void drop_chrdev(void) 498{ 499 lirc_unregister_driver(driver.minor); 500} 501 502/* SECTION: Hardware */ 503static long delta(struct timeval *tv1, struct timeval *tv2) 504{ 505 unsigned long deltv; 506 507 deltv = tv2->tv_sec - tv1->tv_sec; 508 if (deltv > 15) 509 deltv = 0xFFFFFF; 510 else 511 deltv = deltv*1000000 + 512 tv2->tv_usec - 513 tv1->tv_usec; 514 return deltv; 515} 516 517static void sir_timeout(unsigned long data) 518{ 519 /* 520 * if last received signal was a pulse, but receiving stopped 521 * within the 9 bit frame, we need to finish this pulse and 522 * simulate a signal change to from pulse to space. Otherwise 523 * upper layers will receive two sequences next time. 524 */ 525 526 unsigned long flags; 527 unsigned long pulse_end; 528 529 /* avoid interference with interrupt */ 530 spin_lock_irqsave(&timer_lock, flags); 531 if (last_value) { 532#ifndef LIRC_ON_SA1100 533 /* clear unread bits in UART and restart */ 534 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR); 535#endif 536 /* determine 'virtual' pulse end: */ 537 pulse_end = delta(&last_tv, &last_intr_tv); 538 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end); 539 add_read_queue(last_value, pulse_end); 540 last_value = 0; 541 last_tv = last_intr_tv; 542 } 543 spin_unlock_irqrestore(&timer_lock, flags); 544} 545 546static irqreturn_t sir_interrupt(int irq, void *dev_id) 547{ 548 unsigned char data; 549 struct timeval curr_tv; 550 static unsigned long deltv; 551#ifdef LIRC_ON_SA1100 552 int status; 553 static int n; 554 555 status = Ser2UTSR0; 556 /* 557 * Deal with any receive errors first. The bytes in error may be 558 * the only bytes in the receive FIFO, so we do this first. 559 */ 560 while (status & UTSR0_EIF) { 561 int bstat; 562 563 if (debug) { 564 dprintk("EIF\n"); 565 bstat = Ser2UTSR1; 566 567 if (bstat & UTSR1_FRE) 568 dprintk("frame error\n"); 569 if (bstat & UTSR1_ROR) 570 dprintk("receive fifo overrun\n"); 571 if (bstat & UTSR1_PRE) 572 dprintk("parity error\n"); 573 } 574 575 bstat = Ser2UTDR; 576 n++; 577 status = Ser2UTSR0; 578 } 579 580 if (status & (UTSR0_RFS | UTSR0_RID)) { 581 do_gettimeofday(&curr_tv); 582 deltv = delta(&last_tv, &curr_tv); 583 do { 584 data = Ser2UTDR; 585 dprintk("%d data: %u\n", n, (unsigned int) data); 586 n++; 587 } while (status & UTSR0_RID && /* do not empty fifo in order to 588 * get UTSR0_RID in any case */ 589 Ser2UTSR1 & UTSR1_RNE); /* data ready */ 590 591 if (status&UTSR0_RID) { 592 add_read_queue(0 , deltv - n * TIME_CONST); /*space*/ 593 add_read_queue(1, n * TIME_CONST); /*pulse*/ 594 n = 0; 595 last_tv = curr_tv; 596 } 597 } 598 599 if (status & UTSR0_TFS) 600 printk(KERN_ERR "transmit fifo not full, shouldn't happen\n"); 601 602 /* We must clear certain bits. */ 603 status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); 604 if (status) 605 Ser2UTSR0 = status; 606#else 607 unsigned long deltintrtv; 608 unsigned long flags; 609 int iir, lsr; 610 611 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) { 612 switch (iir&UART_IIR_ID) { 613 case UART_IIR_MSI: 614 (void) inb(io + UART_MSR); 615 break; 616 case UART_IIR_RLSI: 617 (void) inb(io + UART_LSR); 618 break; 619 case UART_IIR_THRI: 620 break; 621 case UART_IIR_RDI: 622 /* avoid interference with timer */ 623 spin_lock_irqsave(&timer_lock, flags); 624 do { 625 del_timer(&timerlist); 626 data = inb(io + UART_RX); 627 do_gettimeofday(&curr_tv); 628 deltv = delta(&last_tv, &curr_tv); 629 deltintrtv = delta(&last_intr_tv, &curr_tv); 630 dprintk("t %lu, d %d\n", deltintrtv, (int)data); 631 /* 632 * if nothing came in last X cycles, 633 * it was gap 634 */ 635 if (deltintrtv > TIME_CONST * threshold) { 636 if (last_value) { 637 dprintk("GAP\n"); 638 /* simulate signal change */ 639 add_read_queue(last_value, 640 deltv - 641 deltintrtv); 642 last_value = 0; 643 last_tv.tv_sec = 644 last_intr_tv.tv_sec; 645 last_tv.tv_usec = 646 last_intr_tv.tv_usec; 647 deltv = deltintrtv; 648 } 649 } 650 data = 1; 651 if (data ^ last_value) { 652 /* 653 * deltintrtv > 2*TIME_CONST, remember? 654 * the other case is timeout 655 */ 656 add_read_queue(last_value, 657 deltv-TIME_CONST); 658 last_value = data; 659 last_tv = curr_tv; 660 if (last_tv.tv_usec >= TIME_CONST) { 661 last_tv.tv_usec -= TIME_CONST; 662 } else { 663 last_tv.tv_sec--; 664 last_tv.tv_usec += 1000000 - 665 TIME_CONST; 666 } 667 } 668 last_intr_tv = curr_tv; 669 if (data) { 670 /* 671 * start timer for end of 672 * sequence detection 673 */ 674 timerlist.expires = jiffies + 675 SIR_TIMEOUT; 676 add_timer(&timerlist); 677 } 678 679 lsr = inb(io + UART_LSR); 680 } while (lsr & UART_LSR_DR); /* data ready */ 681 spin_unlock_irqrestore(&timer_lock, flags); 682 break; 683 default: 684 break; 685 } 686 } 687#endif 688 return IRQ_RETVAL(IRQ_HANDLED); 689} 690 691#ifdef LIRC_ON_SA1100 692static void send_pulse(unsigned long length) 693{ 694 unsigned long k, delay; 695 int flag; 696 697 if (length == 0) 698 return; 699 /* 700 * this won't give us the carrier frequency we really want 701 * due to integer arithmetic, but we can accept this inaccuracy 702 */ 703 704 for (k = flag = 0; k < length; k += delay, flag = !flag) { 705 if (flag) { 706 off(); 707 delay = space_width; 708 } else { 709 on(); 710 delay = pulse_width; 711 } 712 safe_udelay(delay); 713 } 714 off(); 715} 716 717static void send_space(unsigned long length) 718{ 719 if (length == 0) 720 return; 721 off(); 722 safe_udelay(length); 723} 724#else 725static void send_space(unsigned long len) 726{ 727 safe_udelay(len); 728} 729 730static void send_pulse(unsigned long len) 731{ 732 long bytes_out = len / TIME_CONST; 733 long time_left; 734 735 time_left = (long)len - (long)bytes_out * (long)TIME_CONST; 736 if (bytes_out == 0) { 737 bytes_out++; 738 time_left = 0; 739 } 740 while (bytes_out--) { 741 outb(PULSE, io + UART_TX); 742 while (!(inb(io + UART_LSR) & UART_LSR_THRE)) 743 ; 744 } 745} 746#endif 747 748#ifdef CONFIG_SA1100_COLLIE 749static int sa1100_irda_set_power_collie(int state) 750{ 751 if (state) { 752 /* 753 * 0 - off 754 * 1 - short range, lowest power 755 * 2 - medium range, medium power 756 * 3 - maximum range, high power 757 */ 758 ucb1200_set_io_direction(TC35143_GPIO_IR_ON, 759 TC35143_IODIR_OUTPUT); 760 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW); 761 udelay(100); 762 } else { 763 /* OFF */ 764 ucb1200_set_io_direction(TC35143_GPIO_IR_ON, 765 TC35143_IODIR_OUTPUT); 766 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH); 767 } 768 return 0; 769} 770#endif 771 772static int init_hardware(void) 773{ 774 unsigned long flags; 775 776 spin_lock_irqsave(&hardware_lock, flags); 777 /* reset UART */ 778#ifdef LIRC_ON_SA1100 779#ifdef CONFIG_SA1100_BITSY 780 if (machine_is_bitsy()) { 781 printk(KERN_INFO "Power on IR module\n"); 782 set_bitsy_egpio(EGPIO_BITSY_IR_ON); 783 } 784#endif 785#ifdef CONFIG_SA1100_COLLIE 786 sa1100_irda_set_power_collie(3); /* power on */ 787#endif 788 sr.hscr0 = Ser2HSCR0; 789 790 sr.utcr0 = Ser2UTCR0; 791 sr.utcr1 = Ser2UTCR1; 792 sr.utcr2 = Ser2UTCR2; 793 sr.utcr3 = Ser2UTCR3; 794 sr.utcr4 = Ser2UTCR4; 795 796 sr.utdr = Ser2UTDR; 797 sr.utsr0 = Ser2UTSR0; 798 sr.utsr1 = Ser2UTSR1; 799 800 /* configure GPIO */ 801 /* output */ 802 PPDR |= PPC_TXD2; 803 PSDR |= PPC_TXD2; 804 /* set output to 0 */ 805 off(); 806 807 /* Enable HP-SIR modulation, and ensure that the port is disabled. */ 808 Ser2UTCR3 = 0; 809 Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP); 810 811 /* clear status register to prevent unwanted interrupts */ 812 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); 813 814 /* 7N1 */ 815 Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData; 816 /* 115200 */ 817 Ser2UTCR1 = 0; 818 Ser2UTCR2 = 1; 819 /* use HPSIR, 1.6 usec pulses */ 820 Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us; 821 822 /* enable receiver, receive fifo interrupt */ 823 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE; 824 825 /* clear status register to prevent unwanted interrupts */ 826 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); 827 828#elif defined(LIRC_SIR_TEKRAM) 829 /* disable FIFO */ 830 soutp(UART_FCR, 831 UART_FCR_CLEAR_RCVR| 832 UART_FCR_CLEAR_XMIT| 833 UART_FCR_TRIGGER_1); 834 835 /* Set DLAB 0. */ 836 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); 837 838 /* First of all, disable all interrupts */ 839 soutp(UART_IER, sinp(UART_IER) & 840 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI))); 841 842 /* Set DLAB 1. */ 843 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); 844 845 /* Set divisor to 12 => 9600 Baud */ 846 soutp(UART_DLM, 0); 847 soutp(UART_DLL, 12); 848 849 /* Set DLAB 0. */ 850 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); 851 852 /* power supply */ 853 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 854 safe_udelay(50*1000); 855 856 /* -DTR low -> reset PIC */ 857 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); 858 udelay(1*1000); 859 860 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 861 udelay(100); 862 863 864 /* -RTS low -> send control byte */ 865 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); 866 udelay(7); 867 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW); 868 869 /* one byte takes ~1042 usec to transmit at 9600,8N1 */ 870 udelay(1500); 871 872 /* back to normal operation */ 873 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 874 udelay(50); 875 876 udelay(1500); 877 878 /* read previous control byte */ 879 printk(KERN_INFO LIRC_DRIVER_NAME 880 ": 0x%02x\n", sinp(UART_RX)); 881 882 /* Set DLAB 1. */ 883 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); 884 885 /* Set divisor to 1 => 115200 Baud */ 886 soutp(UART_DLM, 0); 887 soutp(UART_DLL, 1); 888 889 /* Set DLAB 0, 8 Bit */ 890 soutp(UART_LCR, UART_LCR_WLEN8); 891 /* enable interrupts */ 892 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); 893#else 894 outb(0, io + UART_MCR); 895 outb(0, io + UART_IER); 896 /* init UART */ 897 /* set DLAB, speed = 115200 */ 898 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR); 899 outb(1, io + UART_DLL); outb(0, io + UART_DLM); 900 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */ 901 outb(UART_LCR_WLEN7, io + UART_LCR); 902 /* FIFO operation */ 903 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR); 904 /* interrupts */ 905 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */ 906 outb(UART_IER_RDI, io + UART_IER); 907 /* turn on UART */ 908 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR); 909#ifdef LIRC_SIR_ACTISYS_ACT200L 910 init_act200(); 911#elif defined(LIRC_SIR_ACTISYS_ACT220L) 912 init_act220(); 913#endif 914#endif 915 spin_unlock_irqrestore(&hardware_lock, flags); 916 return 0; 917} 918 919static void drop_hardware(void) 920{ 921 unsigned long flags; 922 923 spin_lock_irqsave(&hardware_lock, flags); 924 925#ifdef LIRC_ON_SA1100 926 Ser2UTCR3 = 0; 927 928 Ser2UTCR0 = sr.utcr0; 929 Ser2UTCR1 = sr.utcr1; 930 Ser2UTCR2 = sr.utcr2; 931 Ser2UTCR4 = sr.utcr4; 932 Ser2UTCR3 = sr.utcr3; 933 934 Ser2HSCR0 = sr.hscr0; 935#ifdef CONFIG_SA1100_BITSY 936 if (machine_is_bitsy()) 937 clr_bitsy_egpio(EGPIO_BITSY_IR_ON); 938#endif 939#ifdef CONFIG_SA1100_COLLIE 940 sa1100_irda_set_power_collie(0); /* power off */ 941#endif 942#else 943 /* turn off interrupts */ 944 outb(0, io + UART_IER); 945#endif 946 spin_unlock_irqrestore(&hardware_lock, flags); 947} 948 949/* SECTION: Initialisation */ 950 951static int init_port(void) 952{ 953 int retval; 954 955 /* get I/O port access and IRQ line */ 956#ifndef LIRC_ON_SA1100 957 if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) { 958 printk(KERN_ERR LIRC_DRIVER_NAME 959 ": i/o port 0x%.4x already in use.\n", io); 960 return -EBUSY; 961 } 962#endif 963 retval = request_irq(irq, sir_interrupt, IRQF_DISABLED, 964 LIRC_DRIVER_NAME, NULL); 965 if (retval < 0) { 966# ifndef LIRC_ON_SA1100 967 release_region(io, 8); 968# endif 969 printk(KERN_ERR LIRC_DRIVER_NAME 970 ": IRQ %d already in use.\n", 971 irq); 972 return retval; 973 } 974#ifndef LIRC_ON_SA1100 975 printk(KERN_INFO LIRC_DRIVER_NAME 976 ": I/O port 0x%.4x, IRQ %d.\n", 977 io, irq); 978#endif 979 980 init_timer(&timerlist); 981 timerlist.function = sir_timeout; 982 timerlist.data = 0xabadcafe; 983 984 return 0; 985} 986 987static void drop_port(void) 988{ 989 free_irq(irq, NULL); 990 del_timer_sync(&timerlist); 991#ifndef LIRC_ON_SA1100 992 release_region(io, 8); 993#endif 994} 995 996#ifdef LIRC_SIR_ACTISYS_ACT200L 997/* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */ 998/* some code borrowed from Linux IRDA driver */ 999 1000/* Register 0: Control register #1 */ 1001#define ACT200L_REG0 0x00 1002#define ACT200L_TXEN 0x01 /* Enable transmitter */ 1003#define ACT200L_RXEN 0x02 /* Enable receiver */ 1004#define ACT200L_ECHO 0x08 /* Echo control chars */ 1005 1006/* Register 1: Control register #2 */ 1007#define ACT200L_REG1 0x10 1008#define ACT200L_LODB 0x01 /* Load new baud rate count value */ 1009#define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */ 1010 1011/* Register 3: Transmit mode register #2 */ 1012#define ACT200L_REG3 0x30 1013#define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ 1014#define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ 1015#define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */ 1016 1017/* Register 4: Output Power register */ 1018#define ACT200L_REG4 0x40 1019#define ACT200L_OP0 0x01 /* Enable LED1C output */ 1020#define ACT200L_OP1 0x02 /* Enable LED2C output */ 1021#define ACT200L_BLKR 0x04 1022 1023/* Register 5: Receive Mode register */ 1024#define ACT200L_REG5 0x50 1025#define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */ 1026 /*.. other various IRDA bit modes, and TV remote modes..*/ 1027 1028/* Register 6: Receive Sensitivity register #1 */ 1029#define ACT200L_REG6 0x60 1030#define ACT200L_RS0 0x01 /* receive threshold bit 0 */ 1031#define ACT200L_RS1 0x02 /* receive threshold bit 1 */ 1032 1033/* Register 7: Receive Sensitivity register #2 */ 1034#define ACT200L_REG7 0x70 1035#define ACT200L_ENPOS 0x04 /* Ignore the falling edge */ 1036 1037/* Register 8,9: Baud Rate Divider register #1,#2 */ 1038#define ACT200L_REG8 0x80 1039#define ACT200L_REG9 0x90 1040 1041#define ACT200L_2400 0x5f 1042#define ACT200L_9600 0x17 1043#define ACT200L_19200 0x0b 1044#define ACT200L_38400 0x05 1045#define ACT200L_57600 0x03 1046#define ACT200L_115200 0x01 1047 1048/* Register 13: Control register #3 */ 1049#define ACT200L_REG13 0xd0 1050#define ACT200L_SHDW 0x01 /* Enable access to shadow registers */ 1051 1052/* Register 15: Status register */ 1053#define ACT200L_REG15 0xf0 1054 1055/* Register 21: Control register #4 */ 1056#define ACT200L_REG21 0x50 1057#define ACT200L_EXCK 0x02 /* Disable clock output driver */ 1058#define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */ 1059 1060static void init_act200(void) 1061{ 1062 int i; 1063 __u8 control[] = { 1064 ACT200L_REG15, 1065 ACT200L_REG13 | ACT200L_SHDW, 1066 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL, 1067 ACT200L_REG13, 1068 ACT200L_REG7 | ACT200L_ENPOS, 1069 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1, 1070 ACT200L_REG5 | ACT200L_RWIDL, 1071 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR, 1072 ACT200L_REG3 | ACT200L_B0, 1073 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN, 1074 ACT200L_REG8 | (ACT200L_115200 & 0x0f), 1075 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f), 1076 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE 1077 }; 1078 1079 /* Set DLAB 1. */ 1080 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8); 1081 1082 /* Set divisor to 12 => 9600 Baud */ 1083 soutp(UART_DLM, 0); 1084 soutp(UART_DLL, 12); 1085 1086 /* Set DLAB 0. */ 1087 soutp(UART_LCR, UART_LCR_WLEN8); 1088 /* Set divisor to 12 => 9600 Baud */ 1089 1090 /* power supply */ 1091 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 1092 for (i = 0; i < 50; i++) 1093 safe_udelay(1000); 1094 1095 /* Reset the dongle : set RTS low for 25 ms */ 1096 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); 1097 for (i = 0; i < 25; i++) 1098 udelay(1000); 1099 1100 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 1101 udelay(100); 1102 1103 /* Clear DTR and set RTS to enter command mode */ 1104 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); 1105 udelay(7); 1106 1107 /* send out the control register settings for 115K 7N1 SIR operation */ 1108 for (i = 0; i < sizeof(control); i++) { 1109 soutp(UART_TX, control[i]); 1110 /* one byte takes ~1042 usec to transmit at 9600,8N1 */ 1111 udelay(1500); 1112 } 1113 1114 /* back to normal operation */ 1115 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 1116 udelay(50); 1117 1118 udelay(1500); 1119 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); 1120 1121 /* Set DLAB 1. */ 1122 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); 1123 1124 /* Set divisor to 1 => 115200 Baud */ 1125 soutp(UART_DLM, 0); 1126 soutp(UART_DLL, 1); 1127 1128 /* Set DLAB 0. */ 1129 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); 1130 1131 /* Set DLAB 0, 7 Bit */ 1132 soutp(UART_LCR, UART_LCR_WLEN7); 1133 1134 /* enable interrupts */ 1135 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); 1136} 1137#endif 1138 1139#ifdef LIRC_SIR_ACTISYS_ACT220L 1140/* 1141 * Derived from linux IrDA driver (net/irda/actisys.c) 1142 * Drop me a mail for any kind of comment: maxx@spaceboyz.net 1143 */ 1144 1145void init_act220(void) 1146{ 1147 int i; 1148 1149 /* DLAB 1 */ 1150 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7); 1151 1152 /* 9600 baud */ 1153 soutp(UART_DLM, 0); 1154 soutp(UART_DLL, 12); 1155 1156 /* DLAB 0 */ 1157 soutp(UART_LCR, UART_LCR_WLEN7); 1158 1159 /* reset the dongle, set DTR low for 10us */ 1160 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); 1161 udelay(10); 1162 1163 /* back to normal (still 9600) */ 1164 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2); 1165 1166 /* 1167 * send RTS pulses until we reach 115200 1168 * i hope this is really the same for act220l/act220l+ 1169 */ 1170 for (i = 0; i < 3; i++) { 1171 udelay(10); 1172 /* set RTS low for 10 us */ 1173 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); 1174 udelay(10); 1175 /* set RTS high for 10 us */ 1176 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); 1177 } 1178 1179 /* back to normal operation */ 1180 udelay(1500); /* better safe than sorry ;) */ 1181 1182 /* Set DLAB 1. */ 1183 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); 1184 1185 /* Set divisor to 1 => 115200 Baud */ 1186 soutp(UART_DLM, 0); 1187 soutp(UART_DLL, 1); 1188 1189 /* Set DLAB 0, 7 Bit */ 1190 /* The dongle doesn't seem to have any problems with operation at 7N1 */ 1191 soutp(UART_LCR, UART_LCR_WLEN7); 1192 1193 /* enable interrupts */ 1194 soutp(UART_IER, UART_IER_RDI); 1195} 1196#endif 1197 1198static int init_lirc_sir(void) 1199{ 1200 int retval; 1201 1202 init_waitqueue_head(&lirc_read_queue); 1203 retval = init_port(); 1204 if (retval < 0) 1205 return retval; 1206 init_hardware(); 1207 printk(KERN_INFO LIRC_DRIVER_NAME 1208 ": Installed.\n"); 1209 return 0; 1210} 1211 1212 1213static int __init lirc_sir_init(void) 1214{ 1215 int retval; 1216 1217 retval = init_chrdev(); 1218 if (retval < 0) 1219 return retval; 1220 retval = init_lirc_sir(); 1221 if (retval) { 1222 drop_chrdev(); 1223 return retval; 1224 } 1225 return 0; 1226} 1227 1228static void __exit lirc_sir_exit(void) 1229{ 1230 drop_hardware(); 1231 drop_chrdev(); 1232 drop_port(); 1233 printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n"); 1234} 1235 1236module_init(lirc_sir_init); 1237module_exit(lirc_sir_exit); 1238 1239#ifdef LIRC_SIR_TEKRAM 1240MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210"); 1241MODULE_AUTHOR("Christoph Bartelmus"); 1242#elif defined(LIRC_ON_SA1100) 1243MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor"); 1244MODULE_AUTHOR("Christoph Bartelmus"); 1245#elif defined(LIRC_SIR_ACTISYS_ACT200L) 1246MODULE_DESCRIPTION("LIRC driver for Actisys Act200L"); 1247MODULE_AUTHOR("Karl Bongers"); 1248#elif defined(LIRC_SIR_ACTISYS_ACT220L) 1249MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)"); 1250MODULE_AUTHOR("Jan Roemisch"); 1251#else 1252MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports"); 1253MODULE_AUTHOR("Milan Pikula"); 1254#endif 1255MODULE_LICENSE("GPL"); 1256 1257#ifdef LIRC_ON_SA1100 1258module_param(irq, int, S_IRUGO); 1259MODULE_PARM_DESC(irq, "Interrupt (16)"); 1260#else 1261module_param(io, int, S_IRUGO); 1262MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)"); 1263 1264module_param(irq, int, S_IRUGO); 1265MODULE_PARM_DESC(irq, "Interrupt (4 or 3)"); 1266 1267module_param(threshold, int, S_IRUGO); 1268MODULE_PARM_DESC(threshold, "space detection threshold (3)"); 1269#endif 1270 1271module_param(debug, bool, S_IRUGO | S_IWUSR); 1272MODULE_PARM_DESC(debug, "Enable debugging messages"); 1273