1/* 2 * linux/drivers/serial/pmac_zilog.c 3 * 4 * Driver for PowerMac Z85c30 based ESCC cell found in the 5 * "macio" ASICs of various PowerMac models 6 * 7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) 8 * 9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras 10 * and drivers/serial/sunzilog.c by David S. Miller 11 * 12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and 13 * adapted special tweaks needed for us. I don't think it's worth 14 * merging back those though. The DMA code still has to get in 15 * and once done, I expect that driver to remain fairly stable in 16 * the long term, unless we change the driver model again... 17 * 18 * This program is free software; you can redistribute it and/or modify 19 * it under the terms of the GNU General Public License as published by 20 * the Free Software Foundation; either version 2 of the License, or 21 * (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 31 * 32 * 2004-08-06 Harald Welte <laforge@gnumonks.org> 33 * - Enable BREAK interrupt 34 * - Add support for sysreq 35 * 36 * TODO: - Add DMA support 37 * - Defer port shutdown to a few seconds after close 38 * - maybe put something right into uap->clk_divisor 39 */ 40 41#undef DEBUG 42#undef DEBUG_HARD 43#undef USE_CTRL_O_SYSRQ 44 45#include <linux/module.h> 46#include <linux/tty.h> 47 48#include <linux/tty_flip.h> 49#include <linux/major.h> 50#include <linux/string.h> 51#include <linux/fcntl.h> 52#include <linux/mm.h> 53#include <linux/kernel.h> 54#include <linux/delay.h> 55#include <linux/init.h> 56#include <linux/console.h> 57#include <linux/adb.h> 58#include <linux/pmu.h> 59#include <linux/bitops.h> 60#include <linux/sysrq.h> 61#include <linux/mutex.h> 62#include <asm/sections.h> 63#include <asm/io.h> 64#include <asm/irq.h> 65 66#ifdef CONFIG_PPC_PMAC 67#include <asm/prom.h> 68#include <asm/machdep.h> 69#include <asm/pmac_feature.h> 70#include <asm/dbdma.h> 71#include <asm/macio.h> 72#else 73#include <linux/platform_device.h> 74#define of_machine_is_compatible(x) (0) 75#endif 76 77#if defined(CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 78#define SUPPORT_SYSRQ 79#endif 80 81#include <linux/serial.h> 82#include <linux/serial_core.h> 83 84#include "pmac_zilog.h" 85 86/* Not yet implemented */ 87#undef HAS_DBDMA 88 89static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)"; 90MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); 91MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports."); 92MODULE_LICENSE("GPL"); 93 94#ifdef CONFIG_SERIAL_PMACZILOG_TTYS 95#define PMACZILOG_MAJOR TTY_MAJOR 96#define PMACZILOG_MINOR 64 97#define PMACZILOG_NAME "ttyS" 98#else 99#define PMACZILOG_MAJOR 204 100#define PMACZILOG_MINOR 192 101#define PMACZILOG_NAME "ttyPZ" 102#endif 103 104 105/* 106 * For the sake of early serial console, we can do a pre-probe 107 * (optional) of the ports at rather early boot time. 108 */ 109static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; 110static int pmz_ports_count; 111static DEFINE_MUTEX(pmz_irq_mutex); 112 113static struct uart_driver pmz_uart_reg = { 114 .owner = THIS_MODULE, 115 .driver_name = PMACZILOG_NAME, 116 .dev_name = PMACZILOG_NAME, 117 .major = PMACZILOG_MAJOR, 118 .minor = PMACZILOG_MINOR, 119}; 120 121 122/* 123 * Load all registers to reprogram the port 124 * This function must only be called when the TX is not busy. The UART 125 * port lock must be held and local interrupts disabled. 126 */ 127static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) 128{ 129 int i; 130 131 if (ZS_IS_ASLEEP(uap)) 132 return; 133 134 /* Let pending transmits finish. */ 135 for (i = 0; i < 1000; i++) { 136 unsigned char stat = read_zsreg(uap, R1); 137 if (stat & ALL_SNT) 138 break; 139 udelay(100); 140 } 141 142 ZS_CLEARERR(uap); 143 zssync(uap); 144 ZS_CLEARFIFO(uap); 145 zssync(uap); 146 ZS_CLEARERR(uap); 147 148 /* Disable all interrupts. */ 149 write_zsreg(uap, R1, 150 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 151 152 /* Set parity, sync config, stop bits, and clock divisor. */ 153 write_zsreg(uap, R4, regs[R4]); 154 155 /* Set misc. TX/RX control bits. */ 156 write_zsreg(uap, R10, regs[R10]); 157 158 /* Set TX/RX controls sans the enable bits. */ 159 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); 160 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); 161 162 /* now set R7 "prime" on ESCC */ 163 write_zsreg(uap, R15, regs[R15] | EN85C30); 164 write_zsreg(uap, R7, regs[R7P]); 165 166 /* make sure we use R7 "non-prime" on ESCC */ 167 write_zsreg(uap, R15, regs[R15] & ~EN85C30); 168 169 /* Synchronous mode config. */ 170 write_zsreg(uap, R6, regs[R6]); 171 write_zsreg(uap, R7, regs[R7]); 172 173 /* Disable baud generator. */ 174 write_zsreg(uap, R14, regs[R14] & ~BRENAB); 175 176 /* Clock mode control. */ 177 write_zsreg(uap, R11, regs[R11]); 178 179 /* Lower and upper byte of baud rate generator divisor. */ 180 write_zsreg(uap, R12, regs[R12]); 181 write_zsreg(uap, R13, regs[R13]); 182 183 /* Now rewrite R14, with BRENAB (if set). */ 184 write_zsreg(uap, R14, regs[R14]); 185 186 /* Reset external status interrupts. */ 187 write_zsreg(uap, R0, RES_EXT_INT); 188 write_zsreg(uap, R0, RES_EXT_INT); 189 190 /* Rewrite R3/R5, this time without enables masked. */ 191 write_zsreg(uap, R3, regs[R3]); 192 write_zsreg(uap, R5, regs[R5]); 193 194 /* Rewrite R1, this time without IRQ enabled masked. */ 195 write_zsreg(uap, R1, regs[R1]); 196 197 /* Enable interrupts */ 198 write_zsreg(uap, R9, regs[R9]); 199} 200 201/* 202 * We do like sunzilog to avoid disrupting pending Tx 203 * Reprogram the Zilog channel HW registers with the copies found in the 204 * software state struct. If the transmitter is busy, we defer this update 205 * until the next TX complete interrupt. Else, we do it right now. 206 * 207 * The UART port lock must be held and local interrupts disabled. 208 */ 209static void pmz_maybe_update_regs(struct uart_pmac_port *uap) 210{ 211 if (!ZS_REGS_HELD(uap)) { 212 if (ZS_TX_ACTIVE(uap)) { 213 uap->flags |= PMACZILOG_FLAG_REGS_HELD; 214 } else { 215 pmz_debug("pmz: maybe_update_regs: updating\n"); 216 pmz_load_zsregs(uap, uap->curregs); 217 } 218 } 219} 220 221static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap) 222{ 223 struct tty_struct *tty = NULL; 224 unsigned char ch, r1, drop, error, flag; 225 int loops = 0; 226 227 /* The interrupt can be enabled when the port isn't open, typically 228 * that happens when using one port is open and the other closed (stale 229 * interrupt) or when one port is used as a console. 230 */ 231 if (!ZS_IS_OPEN(uap)) { 232 pmz_debug("pmz: draining input\n"); 233 /* Port is closed, drain input data */ 234 for (;;) { 235 if ((++loops) > 1000) 236 goto flood; 237 (void)read_zsreg(uap, R1); 238 write_zsreg(uap, R0, ERR_RES); 239 (void)read_zsdata(uap); 240 ch = read_zsreg(uap, R0); 241 if (!(ch & Rx_CH_AV)) 242 break; 243 } 244 return NULL; 245 } 246 247 /* Sanity check, make sure the old bug is no longer happening */ 248 if (uap->port.state == NULL || uap->port.state->port.tty == NULL) { 249 WARN_ON(1); 250 (void)read_zsdata(uap); 251 return NULL; 252 } 253 tty = uap->port.state->port.tty; 254 255 while (1) { 256 error = 0; 257 drop = 0; 258 259 r1 = read_zsreg(uap, R1); 260 ch = read_zsdata(uap); 261 262 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 263 write_zsreg(uap, R0, ERR_RES); 264 zssync(uap); 265 } 266 267 ch &= uap->parity_mask; 268 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { 269 uap->flags &= ~PMACZILOG_FLAG_BREAK; 270 } 271 272#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) 273#ifdef USE_CTRL_O_SYSRQ 274 /* Handle the SysRq ^O Hack */ 275 if (ch == '\x0f') { 276 uap->port.sysrq = jiffies + HZ*5; 277 goto next_char; 278 } 279#endif /* USE_CTRL_O_SYSRQ */ 280 if (uap->port.sysrq) { 281 int swallow; 282 spin_unlock(&uap->port.lock); 283 swallow = uart_handle_sysrq_char(&uap->port, ch); 284 spin_lock(&uap->port.lock); 285 if (swallow) 286 goto next_char; 287 } 288#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ 289 290 /* A real serial line, record the character and status. */ 291 if (drop) 292 goto next_char; 293 294 flag = TTY_NORMAL; 295 uap->port.icount.rx++; 296 297 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { 298 error = 1; 299 if (r1 & BRK_ABRT) { 300 pmz_debug("pmz: got break !\n"); 301 r1 &= ~(PAR_ERR | CRC_ERR); 302 uap->port.icount.brk++; 303 if (uart_handle_break(&uap->port)) 304 goto next_char; 305 } 306 else if (r1 & PAR_ERR) 307 uap->port.icount.parity++; 308 else if (r1 & CRC_ERR) 309 uap->port.icount.frame++; 310 if (r1 & Rx_OVR) 311 uap->port.icount.overrun++; 312 r1 &= uap->port.read_status_mask; 313 if (r1 & BRK_ABRT) 314 flag = TTY_BREAK; 315 else if (r1 & PAR_ERR) 316 flag = TTY_PARITY; 317 else if (r1 & CRC_ERR) 318 flag = TTY_FRAME; 319 } 320 321 if (uap->port.ignore_status_mask == 0xff || 322 (r1 & uap->port.ignore_status_mask) == 0) { 323 tty_insert_flip_char(tty, ch, flag); 324 } 325 if (r1 & Rx_OVR) 326 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 327 next_char: 328 /* We can get stuck in an infinite loop getting char 0 when the 329 * line is in a wrong HW state, we break that here. 330 * When that happens, I disable the receive side of the driver. 331 * Note that what I've been experiencing is a real irq loop where 332 * I'm getting flooded regardless of the actual port speed. 333 * Something stange is going on with the HW 334 */ 335 if ((++loops) > 1000) 336 goto flood; 337 ch = read_zsreg(uap, R0); 338 if (!(ch & Rx_CH_AV)) 339 break; 340 } 341 342 return tty; 343 flood: 344 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 345 write_zsreg(uap, R1, uap->curregs[R1]); 346 zssync(uap); 347 pmz_error("pmz: rx irq flood !\n"); 348 return tty; 349} 350 351static void pmz_status_handle(struct uart_pmac_port *uap) 352{ 353 unsigned char status; 354 355 status = read_zsreg(uap, R0); 356 write_zsreg(uap, R0, RES_EXT_INT); 357 zssync(uap); 358 359 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { 360 if (status & SYNC_HUNT) 361 uap->port.icount.dsr++; 362 363 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 364 * But it does not tell us which bit has changed, we have to keep 365 * track of this ourselves. 366 * The CTS input is inverted for some reason. -- paulus 367 */ 368 if ((status ^ uap->prev_status) & DCD) 369 uart_handle_dcd_change(&uap->port, 370 (status & DCD)); 371 if ((status ^ uap->prev_status) & CTS) 372 uart_handle_cts_change(&uap->port, 373 !(status & CTS)); 374 375 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 376 } 377 378 if (status & BRK_ABRT) 379 uap->flags |= PMACZILOG_FLAG_BREAK; 380 381 uap->prev_status = status; 382} 383 384static void pmz_transmit_chars(struct uart_pmac_port *uap) 385{ 386 struct circ_buf *xmit; 387 388 if (ZS_IS_ASLEEP(uap)) 389 return; 390 if (ZS_IS_CONS(uap)) { 391 unsigned char status = read_zsreg(uap, R0); 392 393 /* TX still busy? Just wait for the next TX done interrupt. 394 * 395 * It can occur because of how we do serial console writes. It would 396 * be nice to transmit console writes just like we normally would for 397 * a TTY line. (ie. buffered and TX interrupt driven). That is not 398 * easy because console writes cannot sleep. One solution might be 399 * to poll on enough port->xmit space becomming free. -DaveM 400 */ 401 if (!(status & Tx_BUF_EMP)) 402 return; 403 } 404 405 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; 406 407 if (ZS_REGS_HELD(uap)) { 408 pmz_load_zsregs(uap, uap->curregs); 409 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; 410 } 411 412 if (ZS_TX_STOPPED(uap)) { 413 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 414 goto ack_tx_int; 415 } 416 417 /* Under some circumstances, we see interrupts reported for 418 * a closed channel. The interrupt mask in R1 is clear, but 419 * R3 still signals the interrupts and we see them when taking 420 * an interrupt for the other channel (this could be a qemu 421 * bug but since the ESCC doc doesn't specify precsiely whether 422 * R3 interrup status bits are masked by R1 interrupt enable 423 * bits, better safe than sorry). --BenH. 424 */ 425 if (!ZS_IS_OPEN(uap)) 426 goto ack_tx_int; 427 428 if (uap->port.x_char) { 429 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 430 write_zsdata(uap, uap->port.x_char); 431 zssync(uap); 432 uap->port.icount.tx++; 433 uap->port.x_char = 0; 434 return; 435 } 436 437 if (uap->port.state == NULL) 438 goto ack_tx_int; 439 xmit = &uap->port.state->xmit; 440 if (uart_circ_empty(xmit)) { 441 uart_write_wakeup(&uap->port); 442 goto ack_tx_int; 443 } 444 if (uart_tx_stopped(&uap->port)) 445 goto ack_tx_int; 446 447 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 448 write_zsdata(uap, xmit->buf[xmit->tail]); 449 zssync(uap); 450 451 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 452 uap->port.icount.tx++; 453 454 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 455 uart_write_wakeup(&uap->port); 456 457 return; 458 459ack_tx_int: 460 write_zsreg(uap, R0, RES_Tx_P); 461 zssync(uap); 462} 463 464static irqreturn_t pmz_interrupt(int irq, void *dev_id) 465{ 466 struct uart_pmac_port *uap = dev_id; 467 struct uart_pmac_port *uap_a; 468 struct uart_pmac_port *uap_b; 469 int rc = IRQ_NONE; 470 struct tty_struct *tty; 471 u8 r3; 472 473 uap_a = pmz_get_port_A(uap); 474 uap_b = uap_a->mate; 475 476 spin_lock(&uap_a->port.lock); 477 r3 = read_zsreg(uap_a, R3); 478 479#ifdef DEBUG_HARD 480 pmz_debug("irq, r3: %x\n", r3); 481#endif 482 /* Channel A */ 483 tty = NULL; 484 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 485 write_zsreg(uap_a, R0, RES_H_IUS); 486 zssync(uap_a); 487 if (r3 & CHAEXT) 488 pmz_status_handle(uap_a); 489 if (r3 & CHARxIP) 490 tty = pmz_receive_chars(uap_a); 491 if (r3 & CHATxIP) 492 pmz_transmit_chars(uap_a); 493 rc = IRQ_HANDLED; 494 } 495 spin_unlock(&uap_a->port.lock); 496 if (tty != NULL) 497 tty_flip_buffer_push(tty); 498 499 if (uap_b->node == NULL) 500 goto out; 501 502 spin_lock(&uap_b->port.lock); 503 tty = NULL; 504 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 505 write_zsreg(uap_b, R0, RES_H_IUS); 506 zssync(uap_b); 507 if (r3 & CHBEXT) 508 pmz_status_handle(uap_b); 509 if (r3 & CHBRxIP) 510 tty = pmz_receive_chars(uap_b); 511 if (r3 & CHBTxIP) 512 pmz_transmit_chars(uap_b); 513 rc = IRQ_HANDLED; 514 } 515 spin_unlock(&uap_b->port.lock); 516 if (tty != NULL) 517 tty_flip_buffer_push(tty); 518 519 out: 520#ifdef DEBUG_HARD 521 pmz_debug("irq done.\n"); 522#endif 523 return rc; 524} 525 526/* 527 * Peek the status register, lock not held by caller 528 */ 529static inline u8 pmz_peek_status(struct uart_pmac_port *uap) 530{ 531 unsigned long flags; 532 u8 status; 533 534 spin_lock_irqsave(&uap->port.lock, flags); 535 status = read_zsreg(uap, R0); 536 spin_unlock_irqrestore(&uap->port.lock, flags); 537 538 return status; 539} 540 541/* 542 * Check if transmitter is empty 543 * The port lock is not held. 544 */ 545static unsigned int pmz_tx_empty(struct uart_port *port) 546{ 547 struct uart_pmac_port *uap = to_pmz(port); 548 unsigned char status; 549 550 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 551 return TIOCSER_TEMT; 552 553 status = pmz_peek_status(to_pmz(port)); 554 if (status & Tx_BUF_EMP) 555 return TIOCSER_TEMT; 556 return 0; 557} 558 559/* 560 * Set Modem Control (RTS & DTR) bits 561 * The port lock is held and interrupts are disabled. 562 * Note: Shall we really filter out RTS on external ports or 563 * should that be dealt at higher level only ? 564 */ 565static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) 566{ 567 struct uart_pmac_port *uap = to_pmz(port); 568 unsigned char set_bits, clear_bits; 569 570 /* Do nothing for irda for now... */ 571 if (ZS_IS_IRDA(uap)) 572 return; 573 /* We get called during boot with a port not up yet */ 574 if (ZS_IS_ASLEEP(uap) || 575 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) 576 return; 577 578 set_bits = clear_bits = 0; 579 580 if (ZS_IS_INTMODEM(uap)) { 581 if (mctrl & TIOCM_RTS) 582 set_bits |= RTS; 583 else 584 clear_bits |= RTS; 585 } 586 if (mctrl & TIOCM_DTR) 587 set_bits |= DTR; 588 else 589 clear_bits |= DTR; 590 591 /* NOTE: Not subject to 'transmitter active' rule. */ 592 uap->curregs[R5] |= set_bits; 593 uap->curregs[R5] &= ~clear_bits; 594 if (ZS_IS_ASLEEP(uap)) 595 return; 596 write_zsreg(uap, R5, uap->curregs[R5]); 597 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", 598 set_bits, clear_bits, uap->curregs[R5]); 599 zssync(uap); 600} 601 602/* 603 * Get Modem Control bits (only the input ones, the core will 604 * or that with a cached value of the control ones) 605 * The port lock is held and interrupts are disabled. 606 */ 607static unsigned int pmz_get_mctrl(struct uart_port *port) 608{ 609 struct uart_pmac_port *uap = to_pmz(port); 610 unsigned char status; 611 unsigned int ret; 612 613 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 614 return 0; 615 616 status = read_zsreg(uap, R0); 617 618 ret = 0; 619 if (status & DCD) 620 ret |= TIOCM_CAR; 621 if (status & SYNC_HUNT) 622 ret |= TIOCM_DSR; 623 if (!(status & CTS)) 624 ret |= TIOCM_CTS; 625 626 return ret; 627} 628 629/* 630 * Stop TX side. Dealt like sunzilog at next Tx interrupt, 631 * though for DMA, we will have to do a bit more. 632 * The port lock is held and interrupts are disabled. 633 */ 634static void pmz_stop_tx(struct uart_port *port) 635{ 636 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; 637} 638 639/* 640 * Kick the Tx side. 641 * The port lock is held and interrupts are disabled. 642 */ 643static void pmz_start_tx(struct uart_port *port) 644{ 645 struct uart_pmac_port *uap = to_pmz(port); 646 unsigned char status; 647 648 pmz_debug("pmz: start_tx()\n"); 649 650 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 651 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 652 653 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 654 return; 655 656 status = read_zsreg(uap, R0); 657 658 /* TX busy? Just wait for the TX done interrupt. */ 659 if (!(status & Tx_BUF_EMP)) 660 return; 661 662 /* Send the first character to jump-start the TX done 663 * IRQ sending engine. 664 */ 665 if (port->x_char) { 666 write_zsdata(uap, port->x_char); 667 zssync(uap); 668 port->icount.tx++; 669 port->x_char = 0; 670 } else { 671 struct circ_buf *xmit = &port->state->xmit; 672 673 write_zsdata(uap, xmit->buf[xmit->tail]); 674 zssync(uap); 675 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 676 port->icount.tx++; 677 678 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 679 uart_write_wakeup(&uap->port); 680 } 681 pmz_debug("pmz: start_tx() done.\n"); 682} 683 684/* 685 * Stop Rx side, basically disable emitting of 686 * Rx interrupts on the port. We don't disable the rx 687 * side of the chip proper though 688 * The port lock is held. 689 */ 690static void pmz_stop_rx(struct uart_port *port) 691{ 692 struct uart_pmac_port *uap = to_pmz(port); 693 694 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 695 return; 696 697 pmz_debug("pmz: stop_rx()()\n"); 698 699 /* Disable all RX interrupts. */ 700 uap->curregs[R1] &= ~RxINT_MASK; 701 pmz_maybe_update_regs(uap); 702 703 pmz_debug("pmz: stop_rx() done.\n"); 704} 705 706/* 707 * Enable modem status change interrupts 708 * The port lock is held. 709 */ 710static void pmz_enable_ms(struct uart_port *port) 711{ 712 struct uart_pmac_port *uap = to_pmz(port); 713 unsigned char new_reg; 714 715 if (ZS_IS_IRDA(uap) || uap->node == NULL) 716 return; 717 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 718 if (new_reg != uap->curregs[R15]) { 719 uap->curregs[R15] = new_reg; 720 721 if (ZS_IS_ASLEEP(uap)) 722 return; 723 /* NOTE: Not subject to 'transmitter active' rule. */ 724 write_zsreg(uap, R15, uap->curregs[R15]); 725 } 726} 727 728/* 729 * Control break state emission 730 * The port lock is not held. 731 */ 732static void pmz_break_ctl(struct uart_port *port, int break_state) 733{ 734 struct uart_pmac_port *uap = to_pmz(port); 735 unsigned char set_bits, clear_bits, new_reg; 736 unsigned long flags; 737 738 if (uap->node == NULL) 739 return; 740 set_bits = clear_bits = 0; 741 742 if (break_state) 743 set_bits |= SND_BRK; 744 else 745 clear_bits |= SND_BRK; 746 747 spin_lock_irqsave(&port->lock, flags); 748 749 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; 750 if (new_reg != uap->curregs[R5]) { 751 uap->curregs[R5] = new_reg; 752 753 /* NOTE: Not subject to 'transmitter active' rule. */ 754 if (ZS_IS_ASLEEP(uap)) { 755 spin_unlock_irqrestore(&port->lock, flags); 756 return; 757 } 758 write_zsreg(uap, R5, uap->curregs[R5]); 759 } 760 761 spin_unlock_irqrestore(&port->lock, flags); 762} 763 764#ifdef CONFIG_PPC_PMAC 765 766/* 767 * Turn power on or off to the SCC and associated stuff 768 * (port drivers, modem, IR port, etc.) 769 * Returns the number of milliseconds we should wait before 770 * trying to use the port. 771 */ 772static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 773{ 774 int delay = 0; 775 int rc; 776 777 if (state) { 778 rc = pmac_call_feature( 779 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); 780 pmz_debug("port power on result: %d\n", rc); 781 if (ZS_IS_INTMODEM(uap)) { 782 rc = pmac_call_feature( 783 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); 784 delay = 2500; /* wait for 2.5s before using */ 785 pmz_debug("modem power result: %d\n", rc); 786 } 787 } else { 788 /* TODO: Make that depend on a timer, don't power down 789 * immediately 790 */ 791 if (ZS_IS_INTMODEM(uap)) { 792 rc = pmac_call_feature( 793 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); 794 pmz_debug("port power off result: %d\n", rc); 795 } 796 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); 797 } 798 return delay; 799} 800 801#else 802 803static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 804{ 805 return 0; 806} 807 808#endif /* !CONFIG_PPC_PMAC */ 809 810static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) 811{ 812 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 813 zssync(uap); 814 udelay(10); 815 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); 816 zssync(uap); 817 818 write_zsreg(uap, 4, X1CLK | MONSYNC); 819 write_zsreg(uap, 3, Rx8); 820 write_zsreg(uap, 5, Tx8 | RTS); 821 write_zsreg(uap, 9, NV); /* Didn't we already do this? */ 822 write_zsreg(uap, 11, RCBR | TCBR); 823 write_zsreg(uap, 12, 0); 824 write_zsreg(uap, 13, 0); 825 write_zsreg(uap, 14, (LOOPBAK | BRSRC)); 826 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); 827 write_zsreg(uap, 3, Rx8 | RxENABLE); 828 write_zsreg(uap, 0, RES_EXT_INT); 829 write_zsreg(uap, 0, RES_EXT_INT); 830 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ 831 832 /* The channel should be OK now, but it is probably receiving 833 * loopback garbage. 834 * Switch to asynchronous mode, disable the receiver, 835 * and discard everything in the receive buffer. 836 */ 837 write_zsreg(uap, 9, NV); 838 write_zsreg(uap, 4, X16CLK | SB_MASK); 839 write_zsreg(uap, 3, Rx8); 840 841 while (read_zsreg(uap, 0) & Rx_CH_AV) { 842 (void)read_zsreg(uap, 8); 843 write_zsreg(uap, 0, RES_EXT_INT); 844 write_zsreg(uap, 0, ERR_RES); 845 } 846} 847 848/* 849 * Real startup routine, powers up the hardware and sets up 850 * the SCC. Returns a delay in ms where you need to wait before 851 * actually using the port, this is typically the internal modem 852 * powerup delay. This routine expect the lock to be taken. 853 */ 854static int __pmz_startup(struct uart_pmac_port *uap) 855{ 856 int pwr_delay = 0; 857 858 memset(&uap->curregs, 0, sizeof(uap->curregs)); 859 860 /* Power up the SCC & underlying hardware (modem/irda) */ 861 pwr_delay = pmz_set_scc_power(uap, 1); 862 863 /* Nice buggy HW ... */ 864 pmz_fix_zero_bug_scc(uap); 865 866 /* Reset the channel */ 867 uap->curregs[R9] = 0; 868 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 869 zssync(uap); 870 udelay(10); 871 write_zsreg(uap, 9, 0); 872 zssync(uap); 873 874 /* Clear the interrupt registers */ 875 write_zsreg(uap, R1, 0); 876 write_zsreg(uap, R0, ERR_RES); 877 write_zsreg(uap, R0, ERR_RES); 878 write_zsreg(uap, R0, RES_H_IUS); 879 write_zsreg(uap, R0, RES_H_IUS); 880 881 /* Setup some valid baud rate */ 882 uap->curregs[R4] = X16CLK | SB1; 883 uap->curregs[R3] = Rx8; 884 uap->curregs[R5] = Tx8 | RTS; 885 if (!ZS_IS_IRDA(uap)) 886 uap->curregs[R5] |= DTR; 887 uap->curregs[R12] = 0; 888 uap->curregs[R13] = 0; 889 uap->curregs[R14] = BRENAB; 890 891 /* Clear handshaking, enable BREAK interrupts */ 892 uap->curregs[R15] = BRKIE; 893 894 /* Master interrupt enable */ 895 uap->curregs[R9] |= NV | MIE; 896 897 pmz_load_zsregs(uap, uap->curregs); 898 899 /* Enable receiver and transmitter. */ 900 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); 901 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); 902 903 /* Remember status for DCD/CTS changes */ 904 uap->prev_status = read_zsreg(uap, R0); 905 906 return pwr_delay; 907} 908 909static void pmz_irda_reset(struct uart_pmac_port *uap) 910{ 911 uap->curregs[R5] |= DTR; 912 write_zsreg(uap, R5, uap->curregs[R5]); 913 zssync(uap); 914 mdelay(110); 915 uap->curregs[R5] &= ~DTR; 916 write_zsreg(uap, R5, uap->curregs[R5]); 917 zssync(uap); 918 mdelay(10); 919} 920 921/* 922 * This is the "normal" startup routine, using the above one 923 * wrapped with the lock and doing a schedule delay 924 */ 925static int pmz_startup(struct uart_port *port) 926{ 927 struct uart_pmac_port *uap = to_pmz(port); 928 unsigned long flags; 929 int pwr_delay = 0; 930 931 pmz_debug("pmz: startup()\n"); 932 933 if (ZS_IS_ASLEEP(uap)) 934 return -EAGAIN; 935 if (uap->node == NULL) 936 return -ENODEV; 937 938 mutex_lock(&pmz_irq_mutex); 939 940 uap->flags |= PMACZILOG_FLAG_IS_OPEN; 941 942 /* A console is never powered down. Else, power up and 943 * initialize the chip 944 */ 945 if (!ZS_IS_CONS(uap)) { 946 spin_lock_irqsave(&port->lock, flags); 947 pwr_delay = __pmz_startup(uap); 948 spin_unlock_irqrestore(&port->lock, flags); 949 } 950 951 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; 952 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, 953 "SCC", uap)) { 954 pmz_error("Unable to register zs interrupt handler.\n"); 955 pmz_set_scc_power(uap, 0); 956 mutex_unlock(&pmz_irq_mutex); 957 return -ENXIO; 958 } 959 960 mutex_unlock(&pmz_irq_mutex); 961 962 /* Right now, we deal with delay by blocking here, I'll be 963 * smarter later on 964 */ 965 if (pwr_delay != 0) { 966 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 967 msleep(pwr_delay); 968 } 969 970 /* IrDA reset is done now */ 971 if (ZS_IS_IRDA(uap)) 972 pmz_irda_reset(uap); 973 974 /* Enable interrupts emission from the chip */ 975 spin_lock_irqsave(&port->lock, flags); 976 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 977 if (!ZS_IS_EXTCLK(uap)) 978 uap->curregs[R1] |= EXT_INT_ENAB; 979 write_zsreg(uap, R1, uap->curregs[R1]); 980 spin_unlock_irqrestore(&port->lock, flags); 981 982 pmz_debug("pmz: startup() done.\n"); 983 984 return 0; 985} 986 987static void pmz_shutdown(struct uart_port *port) 988{ 989 struct uart_pmac_port *uap = to_pmz(port); 990 unsigned long flags; 991 992 pmz_debug("pmz: shutdown()\n"); 993 994 if (uap->node == NULL) 995 return; 996 997 mutex_lock(&pmz_irq_mutex); 998 999 /* Release interrupt handler */ 1000 free_irq(uap->port.irq, uap); 1001 1002 spin_lock_irqsave(&port->lock, flags); 1003 1004 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; 1005 1006 if (!ZS_IS_OPEN(uap->mate)) 1007 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; 1008 1009 /* Disable interrupts */ 1010 if (!ZS_IS_ASLEEP(uap)) { 1011 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1012 write_zsreg(uap, R1, uap->curregs[R1]); 1013 zssync(uap); 1014 } 1015 1016 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) { 1017 spin_unlock_irqrestore(&port->lock, flags); 1018 mutex_unlock(&pmz_irq_mutex); 1019 return; 1020 } 1021 1022 /* Disable receiver and transmitter. */ 1023 uap->curregs[R3] &= ~RxENABLE; 1024 uap->curregs[R5] &= ~TxENABLE; 1025 1026 /* Disable all interrupts and BRK assertion. */ 1027 uap->curregs[R5] &= ~SND_BRK; 1028 pmz_maybe_update_regs(uap); 1029 1030 /* Shut the chip down */ 1031 pmz_set_scc_power(uap, 0); 1032 1033 spin_unlock_irqrestore(&port->lock, flags); 1034 1035 mutex_unlock(&pmz_irq_mutex); 1036 1037 pmz_debug("pmz: shutdown() done.\n"); 1038} 1039 1040/* Shared by TTY driver and serial console setup. The port lock is held 1041 * and local interrupts are disabled. 1042 */ 1043static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, 1044 unsigned int iflag, unsigned long baud) 1045{ 1046 int brg; 1047 1048 /* Switch to external clocking for IrDA high clock rates. That 1049 * code could be re-used for Midi interfaces with different 1050 * multipliers 1051 */ 1052 if (baud >= 115200 && ZS_IS_IRDA(uap)) { 1053 uap->curregs[R4] = X1CLK; 1054 uap->curregs[R11] = RCTRxCP | TCTRxCP; 1055 uap->curregs[R14] = 0; /* BRG off */ 1056 uap->curregs[R12] = 0; 1057 uap->curregs[R13] = 0; 1058 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; 1059 } else { 1060 switch (baud) { 1061 case ZS_CLOCK/16: /* 230400 */ 1062 uap->curregs[R4] = X16CLK; 1063 uap->curregs[R11] = 0; 1064 uap->curregs[R14] = 0; 1065 break; 1066 case ZS_CLOCK/32: /* 115200 */ 1067 uap->curregs[R4] = X32CLK; 1068 uap->curregs[R11] = 0; 1069 uap->curregs[R14] = 0; 1070 break; 1071 default: 1072 uap->curregs[R4] = X16CLK; 1073 uap->curregs[R11] = TCBR | RCBR; 1074 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); 1075 uap->curregs[R12] = (brg & 255); 1076 uap->curregs[R13] = ((brg >> 8) & 255); 1077 uap->curregs[R14] = BRENAB; 1078 } 1079 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; 1080 } 1081 1082 /* Character size, stop bits, and parity. */ 1083 uap->curregs[3] &= ~RxN_MASK; 1084 uap->curregs[5] &= ~TxN_MASK; 1085 1086 switch (cflag & CSIZE) { 1087 case CS5: 1088 uap->curregs[3] |= Rx5; 1089 uap->curregs[5] |= Tx5; 1090 uap->parity_mask = 0x1f; 1091 break; 1092 case CS6: 1093 uap->curregs[3] |= Rx6; 1094 uap->curregs[5] |= Tx6; 1095 uap->parity_mask = 0x3f; 1096 break; 1097 case CS7: 1098 uap->curregs[3] |= Rx7; 1099 uap->curregs[5] |= Tx7; 1100 uap->parity_mask = 0x7f; 1101 break; 1102 case CS8: 1103 default: 1104 uap->curregs[3] |= Rx8; 1105 uap->curregs[5] |= Tx8; 1106 uap->parity_mask = 0xff; 1107 break; 1108 }; 1109 uap->curregs[4] &= ~(SB_MASK); 1110 if (cflag & CSTOPB) 1111 uap->curregs[4] |= SB2; 1112 else 1113 uap->curregs[4] |= SB1; 1114 if (cflag & PARENB) 1115 uap->curregs[4] |= PAR_ENAB; 1116 else 1117 uap->curregs[4] &= ~PAR_ENAB; 1118 if (!(cflag & PARODD)) 1119 uap->curregs[4] |= PAR_EVEN; 1120 else 1121 uap->curregs[4] &= ~PAR_EVEN; 1122 1123 uap->port.read_status_mask = Rx_OVR; 1124 if (iflag & INPCK) 1125 uap->port.read_status_mask |= CRC_ERR | PAR_ERR; 1126 if (iflag & (BRKINT | PARMRK)) 1127 uap->port.read_status_mask |= BRK_ABRT; 1128 1129 uap->port.ignore_status_mask = 0; 1130 if (iflag & IGNPAR) 1131 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 1132 if (iflag & IGNBRK) { 1133 uap->port.ignore_status_mask |= BRK_ABRT; 1134 if (iflag & IGNPAR) 1135 uap->port.ignore_status_mask |= Rx_OVR; 1136 } 1137 1138 if ((cflag & CREAD) == 0) 1139 uap->port.ignore_status_mask = 0xff; 1140} 1141 1142 1143/* 1144 * Set the irda codec on the imac to the specified baud rate. 1145 */ 1146static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) 1147{ 1148 u8 cmdbyte; 1149 int t, version; 1150 1151 switch (*baud) { 1152 /* SIR modes */ 1153 case 2400: 1154 cmdbyte = 0x53; 1155 break; 1156 case 4800: 1157 cmdbyte = 0x52; 1158 break; 1159 case 9600: 1160 cmdbyte = 0x51; 1161 break; 1162 case 19200: 1163 cmdbyte = 0x50; 1164 break; 1165 case 38400: 1166 cmdbyte = 0x4f; 1167 break; 1168 case 57600: 1169 cmdbyte = 0x4e; 1170 break; 1171 case 115200: 1172 cmdbyte = 0x4d; 1173 break; 1174 /* The FIR modes aren't really supported at this point, how 1175 * do we select the speed ? via the FCR on KeyLargo ? 1176 */ 1177 case 1152000: 1178 cmdbyte = 0; 1179 break; 1180 case 4000000: 1181 cmdbyte = 0; 1182 break; 1183 default: /* 9600 */ 1184 cmdbyte = 0x51; 1185 *baud = 9600; 1186 break; 1187 } 1188 1189 /* Wait for transmitter to drain */ 1190 t = 10000; 1191 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 1192 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { 1193 if (--t <= 0) { 1194 pmz_error("transmitter didn't drain\n"); 1195 return; 1196 } 1197 udelay(10); 1198 } 1199 1200 /* Drain the receiver too */ 1201 t = 100; 1202 (void)read_zsdata(uap); 1203 (void)read_zsdata(uap); 1204 (void)read_zsdata(uap); 1205 mdelay(10); 1206 while (read_zsreg(uap, R0) & Rx_CH_AV) { 1207 read_zsdata(uap); 1208 mdelay(10); 1209 if (--t <= 0) { 1210 pmz_error("receiver didn't drain\n"); 1211 return; 1212 } 1213 } 1214 1215 /* Switch to command mode */ 1216 uap->curregs[R5] |= DTR; 1217 write_zsreg(uap, R5, uap->curregs[R5]); 1218 zssync(uap); 1219 mdelay(1); 1220 1221 /* Switch SCC to 19200 */ 1222 pmz_convert_to_zs(uap, CS8, 0, 19200); 1223 pmz_load_zsregs(uap, uap->curregs); 1224 mdelay(1); 1225 1226 /* Write get_version command byte */ 1227 write_zsdata(uap, 1); 1228 t = 5000; 1229 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1230 if (--t <= 0) { 1231 pmz_error("irda_setup timed out on get_version byte\n"); 1232 goto out; 1233 } 1234 udelay(10); 1235 } 1236 version = read_zsdata(uap); 1237 1238 if (version < 4) { 1239 pmz_info("IrDA: dongle version %d not supported\n", version); 1240 goto out; 1241 } 1242 1243 /* Send speed mode */ 1244 write_zsdata(uap, cmdbyte); 1245 t = 5000; 1246 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1247 if (--t <= 0) { 1248 pmz_error("irda_setup timed out on speed mode byte\n"); 1249 goto out; 1250 } 1251 udelay(10); 1252 } 1253 t = read_zsdata(uap); 1254 if (t != cmdbyte) 1255 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); 1256 1257 pmz_info("IrDA setup for %ld bps, dongle version: %d\n", 1258 *baud, version); 1259 1260 (void)read_zsdata(uap); 1261 (void)read_zsdata(uap); 1262 (void)read_zsdata(uap); 1263 1264 out: 1265 /* Switch back to data mode */ 1266 uap->curregs[R5] &= ~DTR; 1267 write_zsreg(uap, R5, uap->curregs[R5]); 1268 zssync(uap); 1269 1270 (void)read_zsdata(uap); 1271 (void)read_zsdata(uap); 1272 (void)read_zsdata(uap); 1273} 1274 1275 1276static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1277 struct ktermios *old) 1278{ 1279 struct uart_pmac_port *uap = to_pmz(port); 1280 unsigned long baud; 1281 1282 pmz_debug("pmz: set_termios()\n"); 1283 1284 if (ZS_IS_ASLEEP(uap)) 1285 return; 1286 1287 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); 1288 1289 if (ZS_IS_IRDA(uap)) { 1290 /* Calc baud rate */ 1291 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); 1292 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); 1293 /* Cet the irda codec to the right rate */ 1294 pmz_irda_setup(uap, &baud); 1295 /* Set final baud rate */ 1296 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1297 pmz_load_zsregs(uap, uap->curregs); 1298 zssync(uap); 1299 } else { 1300 baud = uart_get_baud_rate(port, termios, old, 1200, 230400); 1301 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1302 /* Make sure modem status interrupts are correctly configured */ 1303 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { 1304 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; 1305 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; 1306 } else { 1307 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); 1308 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; 1309 } 1310 1311 /* Load registers to the chip */ 1312 pmz_maybe_update_regs(uap); 1313 } 1314 uart_update_timeout(port, termios->c_cflag, baud); 1315 1316 pmz_debug("pmz: set_termios() done.\n"); 1317} 1318 1319/* The port lock is not held. */ 1320static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1321 struct ktermios *old) 1322{ 1323 struct uart_pmac_port *uap = to_pmz(port); 1324 unsigned long flags; 1325 1326 spin_lock_irqsave(&port->lock, flags); 1327 1328 /* Disable IRQs on the port */ 1329 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1330 write_zsreg(uap, R1, uap->curregs[R1]); 1331 1332 /* Setup new port configuration */ 1333 __pmz_set_termios(port, termios, old); 1334 1335 /* Re-enable IRQs on the port */ 1336 if (ZS_IS_OPEN(uap)) { 1337 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 1338 if (!ZS_IS_EXTCLK(uap)) 1339 uap->curregs[R1] |= EXT_INT_ENAB; 1340 write_zsreg(uap, R1, uap->curregs[R1]); 1341 } 1342 spin_unlock_irqrestore(&port->lock, flags); 1343} 1344 1345static const char *pmz_type(struct uart_port *port) 1346{ 1347 struct uart_pmac_port *uap = to_pmz(port); 1348 1349 if (ZS_IS_IRDA(uap)) 1350 return "Z85c30 ESCC - Infrared port"; 1351 else if (ZS_IS_INTMODEM(uap)) 1352 return "Z85c30 ESCC - Internal modem"; 1353 return "Z85c30 ESCC - Serial port"; 1354} 1355 1356/* We do not request/release mappings of the registers here, this 1357 * happens at early serial probe time. 1358 */ 1359static void pmz_release_port(struct uart_port *port) 1360{ 1361} 1362 1363static int pmz_request_port(struct uart_port *port) 1364{ 1365 return 0; 1366} 1367 1368/* These do not need to do anything interesting either. */ 1369static void pmz_config_port(struct uart_port *port, int flags) 1370{ 1371} 1372 1373/* We do not support letting the user mess with the divisor, IRQ, etc. */ 1374static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) 1375{ 1376 return -EINVAL; 1377} 1378 1379#ifdef CONFIG_CONSOLE_POLL 1380 1381static int pmz_poll_get_char(struct uart_port *port) 1382{ 1383 struct uart_pmac_port *uap = (struct uart_pmac_port *)port; 1384 1385 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) 1386 udelay(5); 1387 return read_zsdata(uap); 1388} 1389 1390static void pmz_poll_put_char(struct uart_port *port, unsigned char c) 1391{ 1392 struct uart_pmac_port *uap = (struct uart_pmac_port *)port; 1393 1394 /* Wait for the transmit buffer to empty. */ 1395 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1396 udelay(5); 1397 write_zsdata(uap, c); 1398} 1399 1400#endif /* CONFIG_CONSOLE_POLL */ 1401 1402static struct uart_ops pmz_pops = { 1403 .tx_empty = pmz_tx_empty, 1404 .set_mctrl = pmz_set_mctrl, 1405 .get_mctrl = pmz_get_mctrl, 1406 .stop_tx = pmz_stop_tx, 1407 .start_tx = pmz_start_tx, 1408 .stop_rx = pmz_stop_rx, 1409 .enable_ms = pmz_enable_ms, 1410 .break_ctl = pmz_break_ctl, 1411 .startup = pmz_startup, 1412 .shutdown = pmz_shutdown, 1413 .set_termios = pmz_set_termios, 1414 .type = pmz_type, 1415 .release_port = pmz_release_port, 1416 .request_port = pmz_request_port, 1417 .config_port = pmz_config_port, 1418 .verify_port = pmz_verify_port, 1419#ifdef CONFIG_CONSOLE_POLL 1420 .poll_get_char = pmz_poll_get_char, 1421 .poll_put_char = pmz_poll_put_char, 1422#endif 1423}; 1424 1425#ifdef CONFIG_PPC_PMAC 1426 1427/* 1428 * Setup one port structure after probing, HW is down at this point, 1429 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't 1430 * register our console before uart_add_one_port() is called 1431 */ 1432static int __init pmz_init_port(struct uart_pmac_port *uap) 1433{ 1434 struct device_node *np = uap->node; 1435 const char *conn; 1436 const struct slot_names_prop { 1437 int count; 1438 char name[1]; 1439 } *slots; 1440 int len; 1441 struct resource r_ports, r_rxdma, r_txdma; 1442 1443 /* 1444 * Request & map chip registers 1445 */ 1446 if (of_address_to_resource(np, 0, &r_ports)) 1447 return -ENODEV; 1448 uap->port.mapbase = r_ports.start; 1449 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); 1450 1451 uap->control_reg = uap->port.membase; 1452 uap->data_reg = uap->control_reg + 0x10; 1453 1454 /* 1455 * Request & map DBDMA registers 1456 */ 1457#ifdef HAS_DBDMA 1458 if (of_address_to_resource(np, 1, &r_txdma) == 0 && 1459 of_address_to_resource(np, 2, &r_rxdma) == 0) 1460 uap->flags |= PMACZILOG_FLAG_HAS_DMA; 1461#else 1462 memset(&r_txdma, 0, sizeof(struct resource)); 1463 memset(&r_rxdma, 0, sizeof(struct resource)); 1464#endif 1465 if (ZS_HAS_DMA(uap)) { 1466 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); 1467 if (uap->tx_dma_regs == NULL) { 1468 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1469 goto no_dma; 1470 } 1471 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); 1472 if (uap->rx_dma_regs == NULL) { 1473 iounmap(uap->tx_dma_regs); 1474 uap->tx_dma_regs = NULL; 1475 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1476 goto no_dma; 1477 } 1478 uap->tx_dma_irq = irq_of_parse_and_map(np, 1); 1479 uap->rx_dma_irq = irq_of_parse_and_map(np, 2); 1480 } 1481no_dma: 1482 1483 /* 1484 * Detect port type 1485 */ 1486 if (of_device_is_compatible(np, "cobalt")) 1487 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1488 conn = of_get_property(np, "AAPL,connector", &len); 1489 if (conn && (strcmp(conn, "infrared") == 0)) 1490 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1491 uap->port_type = PMAC_SCC_ASYNC; 1492 /* 1999 Powerbook G3 has slot-names property instead */ 1493 slots = of_get_property(np, "slot-names", &len); 1494 if (slots && slots->count > 0) { 1495 if (strcmp(slots->name, "IrDA") == 0) 1496 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1497 else if (strcmp(slots->name, "Modem") == 0) 1498 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1499 } 1500 if (ZS_IS_IRDA(uap)) 1501 uap->port_type = PMAC_SCC_IRDA; 1502 if (ZS_IS_INTMODEM(uap)) { 1503 struct device_node* i2c_modem = 1504 of_find_node_by_name(NULL, "i2c-modem"); 1505 if (i2c_modem) { 1506 const char* mid = 1507 of_get_property(i2c_modem, "modem-id", NULL); 1508 if (mid) switch(*mid) { 1509 case 0x04 : 1510 case 0x05 : 1511 case 0x07 : 1512 case 0x08 : 1513 case 0x0b : 1514 case 0x0c : 1515 uap->port_type = PMAC_SCC_I2S1; 1516 } 1517 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", 1518 mid ? (*mid) : 0); 1519 of_node_put(i2c_modem); 1520 } else { 1521 printk(KERN_INFO "pmac_zilog: serial modem detected\n"); 1522 } 1523 } 1524 1525 /* 1526 * Init remaining bits of "port" structure 1527 */ 1528 uap->port.iotype = UPIO_MEM; 1529 uap->port.irq = irq_of_parse_and_map(np, 0); 1530 uap->port.uartclk = ZS_CLOCK; 1531 uap->port.fifosize = 1; 1532 uap->port.ops = &pmz_pops; 1533 uap->port.type = PORT_PMAC_ZILOG; 1534 uap->port.flags = 0; 1535 1536 /* 1537 * Fixup for the port on Gatwick for which the device-tree has 1538 * missing interrupts. Normally, the macio_dev would contain 1539 * fixed up interrupt info, but we use the device-tree directly 1540 * here due to early probing so we need the fixup too. 1541 */ 1542 if (uap->port.irq == NO_IRQ && 1543 np->parent && np->parent->parent && 1544 of_device_is_compatible(np->parent->parent, "gatwick")) { 1545 /* IRQs on gatwick are offset by 64 */ 1546 uap->port.irq = irq_create_mapping(NULL, 64 + 15); 1547 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4); 1548 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5); 1549 } 1550 1551 /* Setup some valid baud rate information in the register 1552 * shadows so we don't write crap there before baud rate is 1553 * first initialized. 1554 */ 1555 pmz_convert_to_zs(uap, CS8, 0, 9600); 1556 1557 return 0; 1558} 1559 1560/* 1561 * Get rid of a port on module removal 1562 */ 1563static void pmz_dispose_port(struct uart_pmac_port *uap) 1564{ 1565 struct device_node *np; 1566 1567 np = uap->node; 1568 iounmap(uap->rx_dma_regs); 1569 iounmap(uap->tx_dma_regs); 1570 iounmap(uap->control_reg); 1571 uap->node = NULL; 1572 of_node_put(np); 1573 memset(uap, 0, sizeof(struct uart_pmac_port)); 1574} 1575 1576/* 1577 * Called upon match with an escc node in the device-tree. 1578 */ 1579static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) 1580{ 1581 int i; 1582 1583 /* Iterate the pmz_ports array to find a matching entry 1584 */ 1585 for (i = 0; i < MAX_ZS_PORTS; i++) 1586 if (pmz_ports[i].node == mdev->ofdev.dev.of_node) { 1587 struct uart_pmac_port *uap = &pmz_ports[i]; 1588 1589 uap->dev = mdev; 1590 dev_set_drvdata(&mdev->ofdev.dev, uap); 1591 if (macio_request_resources(uap->dev, "pmac_zilog")) 1592 printk(KERN_WARNING "%s: Failed to request resource" 1593 ", port still active\n", 1594 uap->node->name); 1595 else 1596 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; 1597 return 0; 1598 } 1599 return -ENODEV; 1600} 1601 1602/* 1603 * That one should not be called, macio isn't really a hotswap device, 1604 * we don't expect one of those serial ports to go away... 1605 */ 1606static int pmz_detach(struct macio_dev *mdev) 1607{ 1608 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1609 1610 if (!uap) 1611 return -ENODEV; 1612 1613 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { 1614 macio_release_resources(uap->dev); 1615 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; 1616 } 1617 dev_set_drvdata(&mdev->ofdev.dev, NULL); 1618 uap->dev = NULL; 1619 1620 return 0; 1621} 1622 1623 1624static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) 1625{ 1626 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1627 struct uart_state *state; 1628 unsigned long flags; 1629 1630 if (uap == NULL) { 1631 printk("HRM... pmz_suspend with NULL uap\n"); 1632 return 0; 1633 } 1634 1635 if (pm_state.event == mdev->ofdev.dev.power.power_state.event) 1636 return 0; 1637 1638 pmz_debug("suspend, switching to state %d\n", pm_state.event); 1639 1640 state = pmz_uart_reg.state + uap->port.line; 1641 1642 mutex_lock(&pmz_irq_mutex); 1643 mutex_lock(&state->port.mutex); 1644 1645 spin_lock_irqsave(&uap->port.lock, flags); 1646 1647 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) { 1648 /* Disable receiver and transmitter. */ 1649 uap->curregs[R3] &= ~RxENABLE; 1650 uap->curregs[R5] &= ~TxENABLE; 1651 1652 /* Disable all interrupts and BRK assertion. */ 1653 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1654 uap->curregs[R5] &= ~SND_BRK; 1655 pmz_load_zsregs(uap, uap->curregs); 1656 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP; 1657 mb(); 1658 } 1659 1660 spin_unlock_irqrestore(&uap->port.lock, flags); 1661 1662 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate)) 1663 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { 1664 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; 1665 disable_irq(uap->port.irq); 1666 } 1667 1668 if (ZS_IS_CONS(uap)) 1669 uap->port.cons->flags &= ~CON_ENABLED; 1670 1671 /* Shut the chip down */ 1672 pmz_set_scc_power(uap, 0); 1673 1674 mutex_unlock(&state->port.mutex); 1675 mutex_unlock(&pmz_irq_mutex); 1676 1677 pmz_debug("suspend, switching complete\n"); 1678 1679 mdev->ofdev.dev.power.power_state = pm_state; 1680 1681 return 0; 1682} 1683 1684 1685static int pmz_resume(struct macio_dev *mdev) 1686{ 1687 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1688 struct uart_state *state; 1689 unsigned long flags; 1690 int pwr_delay = 0; 1691 1692 if (uap == NULL) 1693 return 0; 1694 1695 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON) 1696 return 0; 1697 1698 pmz_debug("resume, switching to state 0\n"); 1699 1700 state = pmz_uart_reg.state + uap->port.line; 1701 1702 mutex_lock(&pmz_irq_mutex); 1703 mutex_lock(&state->port.mutex); 1704 1705 spin_lock_irqsave(&uap->port.lock, flags); 1706 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) { 1707 spin_unlock_irqrestore(&uap->port.lock, flags); 1708 goto bail; 1709 } 1710 pwr_delay = __pmz_startup(uap); 1711 1712 /* Take care of config that may have changed while asleep */ 1713 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL); 1714 1715 if (ZS_IS_OPEN(uap)) { 1716 /* Enable interrupts */ 1717 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 1718 if (!ZS_IS_EXTCLK(uap)) 1719 uap->curregs[R1] |= EXT_INT_ENAB; 1720 write_zsreg(uap, R1, uap->curregs[R1]); 1721 } 1722 1723 spin_unlock_irqrestore(&uap->port.lock, flags); 1724 1725 if (ZS_IS_CONS(uap)) 1726 uap->port.cons->flags |= CON_ENABLED; 1727 1728 /* Re-enable IRQ on the controller */ 1729 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { 1730 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; 1731 enable_irq(uap->port.irq); 1732 } 1733 1734 bail: 1735 mutex_unlock(&state->port.mutex); 1736 mutex_unlock(&pmz_irq_mutex); 1737 1738 /* Right now, we deal with delay by blocking here, I'll be 1739 * smarter later on 1740 */ 1741 if (pwr_delay != 0) { 1742 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 1743 msleep(pwr_delay); 1744 } 1745 1746 pmz_debug("resume, switching complete\n"); 1747 1748 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON; 1749 1750 return 0; 1751} 1752 1753/* 1754 * Probe all ports in the system and build the ports array, we register 1755 * with the serial layer at this point, the macio-type probing is only 1756 * used later to "attach" to the sysfs tree so we get power management 1757 * events 1758 */ 1759static int __init pmz_probe(void) 1760{ 1761 struct device_node *node_p, *node_a, *node_b, *np; 1762 int count = 0; 1763 int rc; 1764 1765 /* 1766 * Find all escc chips in the system 1767 */ 1768 node_p = of_find_node_by_name(NULL, "escc"); 1769 while (node_p) { 1770 /* 1771 * First get channel A/B node pointers 1772 * 1773 * TODO: Add routines with proper locking to do that... 1774 */ 1775 node_a = node_b = NULL; 1776 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) { 1777 if (strncmp(np->name, "ch-a", 4) == 0) 1778 node_a = of_node_get(np); 1779 else if (strncmp(np->name, "ch-b", 4) == 0) 1780 node_b = of_node_get(np); 1781 } 1782 if (!node_a && !node_b) { 1783 of_node_put(node_a); 1784 of_node_put(node_b); 1785 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n", 1786 (!node_a) ? 'a' : 'b', node_p->full_name); 1787 goto next; 1788 } 1789 1790 /* 1791 * Fill basic fields in the port structures 1792 */ 1793 pmz_ports[count].mate = &pmz_ports[count+1]; 1794 pmz_ports[count+1].mate = &pmz_ports[count]; 1795 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1796 pmz_ports[count].node = node_a; 1797 pmz_ports[count+1].node = node_b; 1798 pmz_ports[count].port.line = count; 1799 pmz_ports[count+1].port.line = count+1; 1800 1801 /* 1802 * Setup the ports for real 1803 */ 1804 rc = pmz_init_port(&pmz_ports[count]); 1805 if (rc == 0 && node_b != NULL) 1806 rc = pmz_init_port(&pmz_ports[count+1]); 1807 if (rc != 0) { 1808 of_node_put(node_a); 1809 of_node_put(node_b); 1810 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); 1811 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); 1812 goto next; 1813 } 1814 count += 2; 1815next: 1816 node_p = of_find_node_by_name(node_p, "escc"); 1817 } 1818 pmz_ports_count = count; 1819 1820 return 0; 1821} 1822 1823#else 1824 1825extern struct platform_device scc_a_pdev, scc_b_pdev; 1826 1827static int __init pmz_init_port(struct uart_pmac_port *uap) 1828{ 1829 struct resource *r_ports; 1830 int irq; 1831 1832 r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0); 1833 irq = platform_get_irq(uap->node, 0); 1834 if (!r_ports || !irq) 1835 return -ENODEV; 1836 1837 uap->port.mapbase = r_ports->start; 1838 uap->port.membase = (unsigned char __iomem *) r_ports->start; 1839 uap->port.iotype = UPIO_MEM; 1840 uap->port.irq = irq; 1841 uap->port.uartclk = ZS_CLOCK; 1842 uap->port.fifosize = 1; 1843 uap->port.ops = &pmz_pops; 1844 uap->port.type = PORT_PMAC_ZILOG; 1845 uap->port.flags = 0; 1846 1847 uap->control_reg = uap->port.membase; 1848 uap->data_reg = uap->control_reg + 4; 1849 uap->port_type = 0; 1850 1851 pmz_convert_to_zs(uap, CS8, 0, 9600); 1852 1853 return 0; 1854} 1855 1856static int __init pmz_probe(void) 1857{ 1858 int err; 1859 1860 pmz_ports_count = 0; 1861 1862 pmz_ports[0].mate = &pmz_ports[1]; 1863 pmz_ports[0].port.line = 0; 1864 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1865 pmz_ports[0].node = &scc_a_pdev; 1866 err = pmz_init_port(&pmz_ports[0]); 1867 if (err) 1868 return err; 1869 pmz_ports_count++; 1870 1871 pmz_ports[1].mate = &pmz_ports[0]; 1872 pmz_ports[1].port.line = 1; 1873 pmz_ports[1].flags = 0; 1874 pmz_ports[1].node = &scc_b_pdev; 1875 err = pmz_init_port(&pmz_ports[1]); 1876 if (err) 1877 return err; 1878 pmz_ports_count++; 1879 1880 return 0; 1881} 1882 1883static void pmz_dispose_port(struct uart_pmac_port *uap) 1884{ 1885 memset(uap, 0, sizeof(struct uart_pmac_port)); 1886} 1887 1888static int __init pmz_attach(struct platform_device *pdev) 1889{ 1890 int i; 1891 1892 for (i = 0; i < pmz_ports_count; i++) 1893 if (pmz_ports[i].node == pdev) 1894 return 0; 1895 return -ENODEV; 1896} 1897 1898static int __exit pmz_detach(struct platform_device *pdev) 1899{ 1900 return 0; 1901} 1902 1903#endif /* !CONFIG_PPC_PMAC */ 1904 1905#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1906 1907static void pmz_console_write(struct console *con, const char *s, unsigned int count); 1908static int __init pmz_console_setup(struct console *co, char *options); 1909 1910static struct console pmz_console = { 1911 .name = PMACZILOG_NAME, 1912 .write = pmz_console_write, 1913 .device = uart_console_device, 1914 .setup = pmz_console_setup, 1915 .flags = CON_PRINTBUFFER, 1916 .index = -1, 1917 .data = &pmz_uart_reg, 1918}; 1919 1920#define PMACZILOG_CONSOLE &pmz_console 1921#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1922#define PMACZILOG_CONSOLE (NULL) 1923#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1924 1925/* 1926 * Register the driver, console driver and ports with the serial 1927 * core 1928 */ 1929static int __init pmz_register(void) 1930{ 1931 int i, rc; 1932 1933 pmz_uart_reg.nr = pmz_ports_count; 1934 pmz_uart_reg.cons = PMACZILOG_CONSOLE; 1935 1936 /* 1937 * Register this driver with the serial core 1938 */ 1939 rc = uart_register_driver(&pmz_uart_reg); 1940 if (rc) 1941 return rc; 1942 1943 /* 1944 * Register each port with the serial core 1945 */ 1946 for (i = 0; i < pmz_ports_count; i++) { 1947 struct uart_pmac_port *uport = &pmz_ports[i]; 1948 /* NULL node may happen on wallstreet */ 1949 if (uport->node != NULL) 1950 rc = uart_add_one_port(&pmz_uart_reg, &uport->port); 1951 if (rc) 1952 goto err_out; 1953 } 1954 1955 return 0; 1956err_out: 1957 while (i-- > 0) { 1958 struct uart_pmac_port *uport = &pmz_ports[i]; 1959 uart_remove_one_port(&pmz_uart_reg, &uport->port); 1960 } 1961 uart_unregister_driver(&pmz_uart_reg); 1962 return rc; 1963} 1964 1965#ifdef CONFIG_PPC_PMAC 1966 1967static struct of_device_id pmz_match[] = 1968{ 1969 { 1970 .name = "ch-a", 1971 }, 1972 { 1973 .name = "ch-b", 1974 }, 1975 {}, 1976}; 1977MODULE_DEVICE_TABLE (of, pmz_match); 1978 1979static struct macio_driver pmz_driver = { 1980 .driver = { 1981 .name = "pmac_zilog", 1982 .owner = THIS_MODULE, 1983 .of_match_table = pmz_match, 1984 }, 1985 .probe = pmz_attach, 1986 .remove = pmz_detach, 1987 .suspend = pmz_suspend, 1988 .resume = pmz_resume, 1989}; 1990 1991#else 1992 1993static struct platform_driver pmz_driver = { 1994 .remove = __exit_p(pmz_detach), 1995 .driver = { 1996 .name = "scc", 1997 .owner = THIS_MODULE, 1998 }, 1999}; 2000 2001#endif /* !CONFIG_PPC_PMAC */ 2002 2003static int __init init_pmz(void) 2004{ 2005 int rc, i; 2006 printk(KERN_INFO "%s\n", version); 2007 2008 /* 2009 * First, we need to do a direct OF-based probe pass. We 2010 * do that because we want serial console up before the 2011 * macio stuffs calls us back, and since that makes it 2012 * easier to pass the proper number of channels to 2013 * uart_register_driver() 2014 */ 2015 if (pmz_ports_count == 0) 2016 pmz_probe(); 2017 2018 /* 2019 * Bail early if no port found 2020 */ 2021 if (pmz_ports_count == 0) 2022 return -ENODEV; 2023 2024 /* 2025 * Now we register with the serial layer 2026 */ 2027 rc = pmz_register(); 2028 if (rc) { 2029 printk(KERN_ERR 2030 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" 2031 "pmac_zilog: Did another serial driver already claim the minors?\n"); 2032 /* effectively "pmz_unprobe()" */ 2033 for (i=0; i < pmz_ports_count; i++) 2034 pmz_dispose_port(&pmz_ports[i]); 2035 return rc; 2036 } 2037 2038 /* 2039 * Then we register the macio driver itself 2040 */ 2041#ifdef CONFIG_PPC_PMAC 2042 return macio_register_driver(&pmz_driver); 2043#else 2044 return platform_driver_probe(&pmz_driver, pmz_attach); 2045#endif 2046} 2047 2048static void __exit exit_pmz(void) 2049{ 2050 int i; 2051 2052#ifdef CONFIG_PPC_PMAC 2053 /* Get rid of macio-driver (detach from macio) */ 2054 macio_unregister_driver(&pmz_driver); 2055#else 2056 platform_driver_unregister(&pmz_driver); 2057#endif 2058 2059 for (i = 0; i < pmz_ports_count; i++) { 2060 struct uart_pmac_port *uport = &pmz_ports[i]; 2061 if (uport->node != NULL) { 2062 uart_remove_one_port(&pmz_uart_reg, &uport->port); 2063 pmz_dispose_port(uport); 2064 } 2065 } 2066 /* Unregister UART driver */ 2067 uart_unregister_driver(&pmz_uart_reg); 2068} 2069 2070#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 2071 2072static void pmz_console_putchar(struct uart_port *port, int ch) 2073{ 2074 struct uart_pmac_port *uap = (struct uart_pmac_port *)port; 2075 2076 /* Wait for the transmit buffer to empty. */ 2077 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 2078 udelay(5); 2079 write_zsdata(uap, ch); 2080} 2081 2082/* 2083 * Print a string to the serial port trying not to disturb 2084 * any possible real use of the port... 2085 */ 2086static void pmz_console_write(struct console *con, const char *s, unsigned int count) 2087{ 2088 struct uart_pmac_port *uap = &pmz_ports[con->index]; 2089 unsigned long flags; 2090 2091 if (ZS_IS_ASLEEP(uap)) 2092 return; 2093 spin_lock_irqsave(&uap->port.lock, flags); 2094 2095 /* Turn of interrupts and enable the transmitter. */ 2096 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); 2097 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); 2098 2099 uart_console_write(&uap->port, s, count, pmz_console_putchar); 2100 2101 /* Restore the values in the registers. */ 2102 write_zsreg(uap, R1, uap->curregs[1]); 2103 /* Don't disable the transmitter. */ 2104 2105 spin_unlock_irqrestore(&uap->port.lock, flags); 2106} 2107 2108/* 2109 * Setup the serial console 2110 */ 2111static int __init pmz_console_setup(struct console *co, char *options) 2112{ 2113 struct uart_pmac_port *uap; 2114 struct uart_port *port; 2115 int baud = 38400; 2116 int bits = 8; 2117 int parity = 'n'; 2118 int flow = 'n'; 2119 unsigned long pwr_delay; 2120 2121 /* 2122 * XServe's default to 57600 bps 2123 */ 2124 if (of_machine_is_compatible("RackMac1,1") 2125 || of_machine_is_compatible("RackMac1,2") 2126 || of_machine_is_compatible("MacRISC4")) 2127 baud = 57600; 2128 2129 /* 2130 * Check whether an invalid uart number has been specified, and 2131 * if so, search for the first available port that does have 2132 * console support. 2133 */ 2134 if (co->index >= pmz_ports_count) 2135 co->index = 0; 2136 uap = &pmz_ports[co->index]; 2137 if (uap->node == NULL) 2138 return -ENODEV; 2139 port = &uap->port; 2140 2141 /* 2142 * Mark port as beeing a console 2143 */ 2144 uap->flags |= PMACZILOG_FLAG_IS_CONS; 2145 2146 /* 2147 * Temporary fix for uart layer who didn't setup the spinlock yet 2148 */ 2149 spin_lock_init(&port->lock); 2150 2151 /* 2152 * Enable the hardware 2153 */ 2154 pwr_delay = __pmz_startup(uap); 2155 if (pwr_delay) 2156 mdelay(pwr_delay); 2157 2158 if (options) 2159 uart_parse_options(options, &baud, &parity, &bits, &flow); 2160 2161 return uart_set_options(port, co, baud, parity, bits, flow); 2162} 2163 2164static int __init pmz_console_init(void) 2165{ 2166 /* Probe ports */ 2167 pmz_probe(); 2168 2169 /* TODO: Autoprobe console based on OF */ 2170 /* pmz_console.index = i; */ 2171 register_console(&pmz_console); 2172 2173 return 0; 2174 2175} 2176console_initcall(pmz_console_init); 2177#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 2178 2179module_init(init_pmz); 2180module_exit(exit_pmz); 2181