1/* 2 * linux/drivers/char/atmel_serial.c 3 * 4 * Driver for Atmel AT91 / AT32 Serial ports 5 * Copyright (C) 2003 Rick Bronson 6 * 7 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 8 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 9 * 10 * DMA support added by Chip Coldwell. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27#include <linux/module.h> 28#include <linux/tty.h> 29#include <linux/ioport.h> 30#include <linux/slab.h> 31#include <linux/init.h> 32#include <linux/serial.h> 33#include <linux/clk.h> 34#include <linux/console.h> 35#include <linux/sysrq.h> 36#include <linux/tty_flip.h> 37#include <linux/platform_device.h> 38#include <linux/dma-mapping.h> 39#include <linux/atmel_pdc.h> 40#include <linux/atmel_serial.h> 41#include <linux/uaccess.h> 42 43#include <asm/io.h> 44#include <asm/ioctls.h> 45 46#include <asm/mach/serial_at91.h> 47#include <mach/board.h> 48 49#ifdef CONFIG_ARM 50#include <mach/cpu.h> 51#include <mach/gpio.h> 52#endif 53 54#define PDC_BUFFER_SIZE 512 55/* Revisit: We should calculate this based on the actual port settings */ 56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 57 58#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 59#define SUPPORT_SYSRQ 60#endif 61 62#include <linux/serial_core.h> 63 64static void atmel_start_rx(struct uart_port *port); 65static void atmel_stop_rx(struct uart_port *port); 66 67#ifdef CONFIG_SERIAL_ATMEL_TTYAT 68 69/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 70 * should coexist with the 8250 driver, such as if we have an external 16C550 71 * UART. */ 72#define SERIAL_ATMEL_MAJOR 204 73#define MINOR_START 154 74#define ATMEL_DEVICENAME "ttyAT" 75 76#else 77 78/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 79 * name, but it is legally reserved for the 8250 driver. */ 80#define SERIAL_ATMEL_MAJOR TTY_MAJOR 81#define MINOR_START 64 82#define ATMEL_DEVICENAME "ttyS" 83 84#endif 85 86#define ATMEL_ISR_PASS_LIMIT 256 87 88/* UART registers. CR is write-only, hence no GET macro */ 89#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) 90#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) 91#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) 92#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) 93#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) 94#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) 95#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) 96#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) 97#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) 98#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) 99#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) 100#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) 101#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) 102 103 /* PDC registers */ 104#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) 105#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) 106 107#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) 108#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) 109#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) 110#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) 111#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) 112 113#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) 114#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) 115#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) 116 117static int (*atmel_open_hook)(struct uart_port *); 118static void (*atmel_close_hook)(struct uart_port *); 119 120struct atmel_dma_buffer { 121 unsigned char *buf; 122 dma_addr_t dma_addr; 123 unsigned int dma_size; 124 unsigned int ofs; 125}; 126 127struct atmel_uart_char { 128 u16 status; 129 u16 ch; 130}; 131 132#define ATMEL_SERIAL_RINGSIZE 1024 133 134/* 135 * We wrap our port structure around the generic uart_port. 136 */ 137struct atmel_uart_port { 138 struct uart_port uart; /* uart */ 139 struct clk *clk; /* uart clock */ 140 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 141 u32 backup_imr; /* IMR saved during suspend */ 142 int break_active; /* break being received */ 143 144 short use_dma_rx; /* enable PDC receiver */ 145 short pdc_rx_idx; /* current PDC RX buffer */ 146 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 147 148 short use_dma_tx; /* enable PDC transmitter */ 149 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 150 151 struct tasklet_struct tasklet; 152 unsigned int irq_status; 153 unsigned int irq_status_prev; 154 155 struct circ_buf rx_ring; 156 157 struct serial_rs485 rs485; /* rs485 settings */ 158 unsigned int tx_done_mask; 159}; 160 161static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 162 163#ifdef SUPPORT_SYSRQ 164static struct console atmel_console; 165#endif 166 167static inline struct atmel_uart_port * 168to_atmel_uart_port(struct uart_port *uart) 169{ 170 return container_of(uart, struct atmel_uart_port, uart); 171} 172 173#ifdef CONFIG_SERIAL_ATMEL_PDC 174static bool atmel_use_dma_rx(struct uart_port *port) 175{ 176 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 177 178 return atmel_port->use_dma_rx; 179} 180 181static bool atmel_use_dma_tx(struct uart_port *port) 182{ 183 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 184 185 return atmel_port->use_dma_tx; 186} 187#else 188static bool atmel_use_dma_rx(struct uart_port *port) 189{ 190 return false; 191} 192 193static bool atmel_use_dma_tx(struct uart_port *port) 194{ 195 return false; 196} 197#endif 198 199/* Enable or disable the rs485 support */ 200void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) 201{ 202 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 203 unsigned int mode; 204 205 spin_lock(&port->lock); 206 207 /* Disable interrupts */ 208 UART_PUT_IDR(port, atmel_port->tx_done_mask); 209 210 mode = UART_GET_MR(port); 211 212 /* Resetting serial mode to RS232 (0x0) */ 213 mode &= ~ATMEL_US_USMODE; 214 215 atmel_port->rs485 = *rs485conf; 216 217 if (rs485conf->flags & SER_RS485_ENABLED) { 218 dev_dbg(port->dev, "Setting UART to RS485\n"); 219 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 220 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 221 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); 222 mode |= ATMEL_US_USMODE_RS485; 223 } else { 224 dev_dbg(port->dev, "Setting UART to RS232\n"); 225 if (atmel_use_dma_tx(port)) 226 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 227 ATMEL_US_TXBUFE; 228 else 229 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 230 } 231 UART_PUT_MR(port, mode); 232 233 /* Enable interrupts */ 234 UART_PUT_IER(port, atmel_port->tx_done_mask); 235 236 spin_unlock(&port->lock); 237 238} 239 240/* 241 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 242 */ 243static u_int atmel_tx_empty(struct uart_port *port) 244{ 245 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; 246} 247 248/* 249 * Set state of the modem control output lines 250 */ 251static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 252{ 253 unsigned int control = 0; 254 unsigned int mode; 255 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 256 257#ifdef CONFIG_ARCH_AT91RM9200 258 if (cpu_is_at91rm9200()) { 259 /* 260 * AT91RM9200 Errata #39: RTS0 is not internally connected 261 * to PA21. We need to drive the pin manually. 262 */ 263 if (port->mapbase == AT91RM9200_BASE_US0) { 264 if (mctrl & TIOCM_RTS) 265 at91_set_gpio_value(AT91_PIN_PA21, 0); 266 else 267 at91_set_gpio_value(AT91_PIN_PA21, 1); 268 } 269 } 270#endif 271 272 if (mctrl & TIOCM_RTS) 273 control |= ATMEL_US_RTSEN; 274 else 275 control |= ATMEL_US_RTSDIS; 276 277 if (mctrl & TIOCM_DTR) 278 control |= ATMEL_US_DTREN; 279 else 280 control |= ATMEL_US_DTRDIS; 281 282 UART_PUT_CR(port, control); 283 284 /* Local loopback mode? */ 285 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; 286 if (mctrl & TIOCM_LOOP) 287 mode |= ATMEL_US_CHMODE_LOC_LOOP; 288 else 289 mode |= ATMEL_US_CHMODE_NORMAL; 290 291 /* Resetting serial mode to RS232 (0x0) */ 292 mode &= ~ATMEL_US_USMODE; 293 294 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 295 dev_dbg(port->dev, "Setting UART to RS485\n"); 296 if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 297 UART_PUT_TTGR(port, 298 atmel_port->rs485.delay_rts_after_send); 299 mode |= ATMEL_US_USMODE_RS485; 300 } else { 301 dev_dbg(port->dev, "Setting UART to RS232\n"); 302 } 303 UART_PUT_MR(port, mode); 304} 305 306/* 307 * Get state of the modem control input lines 308 */ 309static u_int atmel_get_mctrl(struct uart_port *port) 310{ 311 unsigned int status, ret = 0; 312 313 status = UART_GET_CSR(port); 314 315 /* 316 * The control signals are active low. 317 */ 318 if (!(status & ATMEL_US_DCD)) 319 ret |= TIOCM_CD; 320 if (!(status & ATMEL_US_CTS)) 321 ret |= TIOCM_CTS; 322 if (!(status & ATMEL_US_DSR)) 323 ret |= TIOCM_DSR; 324 if (!(status & ATMEL_US_RI)) 325 ret |= TIOCM_RI; 326 327 return ret; 328} 329 330/* 331 * Stop transmitting. 332 */ 333static void atmel_stop_tx(struct uart_port *port) 334{ 335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 336 337 if (atmel_use_dma_tx(port)) { 338 /* disable PDC transmit */ 339 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 340 } 341 /* Disable interrupts */ 342 UART_PUT_IDR(port, atmel_port->tx_done_mask); 343 344 if (atmel_port->rs485.flags & SER_RS485_ENABLED) 345 atmel_start_rx(port); 346} 347 348/* 349 * Start transmitting. 350 */ 351static void atmel_start_tx(struct uart_port *port) 352{ 353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 354 355 if (atmel_use_dma_tx(port)) { 356 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) 357 /* The transmitter is already running. Yes, we 358 really need this.*/ 359 return; 360 361 if (atmel_port->rs485.flags & SER_RS485_ENABLED) 362 atmel_stop_rx(port); 363 364 /* re-enable PDC transmit */ 365 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 366 } 367 /* Enable interrupts */ 368 UART_PUT_IER(port, atmel_port->tx_done_mask); 369} 370 371/* 372 * start receiving - port is in process of being opened. 373 */ 374static void atmel_start_rx(struct uart_port *port) 375{ 376 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ 377 378 if (atmel_use_dma_rx(port)) { 379 /* enable PDC controller */ 380 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 381 port->read_status_mask); 382 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 383 } else { 384 UART_PUT_IER(port, ATMEL_US_RXRDY); 385 } 386} 387 388/* 389 * Stop receiving - port is in process of being closed. 390 */ 391static void atmel_stop_rx(struct uart_port *port) 392{ 393 if (atmel_use_dma_rx(port)) { 394 /* disable PDC receive */ 395 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); 396 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 397 port->read_status_mask); 398 } else { 399 UART_PUT_IDR(port, ATMEL_US_RXRDY); 400 } 401} 402 403/* 404 * Enable modem status interrupts 405 */ 406static void atmel_enable_ms(struct uart_port *port) 407{ 408 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC 409 | ATMEL_US_DCDIC | ATMEL_US_CTSIC); 410} 411 412/* 413 * Control the transmission of a break signal 414 */ 415static void atmel_break_ctl(struct uart_port *port, int break_state) 416{ 417 if (break_state != 0) 418 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ 419 else 420 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ 421} 422 423/* 424 * Stores the incoming character in the ring buffer 425 */ 426static void 427atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 428 unsigned int ch) 429{ 430 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 431 struct circ_buf *ring = &atmel_port->rx_ring; 432 struct atmel_uart_char *c; 433 434 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 435 /* Buffer overflow, ignore char */ 436 return; 437 438 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 439 c->status = status; 440 c->ch = ch; 441 442 /* Make sure the character is stored before we update head. */ 443 smp_wmb(); 444 445 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 446} 447 448/* 449 * Deal with parity, framing and overrun errors. 450 */ 451static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 452{ 453 /* clear error */ 454 UART_PUT_CR(port, ATMEL_US_RSTSTA); 455 456 if (status & ATMEL_US_RXBRK) { 457 /* ignore side-effect */ 458 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 459 port->icount.brk++; 460 } 461 if (status & ATMEL_US_PARE) 462 port->icount.parity++; 463 if (status & ATMEL_US_FRAME) 464 port->icount.frame++; 465 if (status & ATMEL_US_OVRE) 466 port->icount.overrun++; 467} 468 469/* 470 * Characters received (called from interrupt handler) 471 */ 472static void atmel_rx_chars(struct uart_port *port) 473{ 474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 475 unsigned int status, ch; 476 477 status = UART_GET_CSR(port); 478 while (status & ATMEL_US_RXRDY) { 479 ch = UART_GET_CHAR(port); 480 481 /* 482 * note that the error handling code is 483 * out of the main execution path 484 */ 485 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 486 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 487 || atmel_port->break_active)) { 488 489 /* clear error */ 490 UART_PUT_CR(port, ATMEL_US_RSTSTA); 491 492 if (status & ATMEL_US_RXBRK 493 && !atmel_port->break_active) { 494 atmel_port->break_active = 1; 495 UART_PUT_IER(port, ATMEL_US_RXBRK); 496 } else { 497 /* 498 * This is either the end-of-break 499 * condition or we've received at 500 * least one character without RXBRK 501 * being set. In both cases, the next 502 * RXBRK will indicate start-of-break. 503 */ 504 UART_PUT_IDR(port, ATMEL_US_RXBRK); 505 status &= ~ATMEL_US_RXBRK; 506 atmel_port->break_active = 0; 507 } 508 } 509 510 atmel_buffer_rx_char(port, status, ch); 511 status = UART_GET_CSR(port); 512 } 513 514 tasklet_schedule(&atmel_port->tasklet); 515} 516 517/* 518 * Transmit characters (called from tasklet with TXRDY interrupt 519 * disabled) 520 */ 521static void atmel_tx_chars(struct uart_port *port) 522{ 523 struct circ_buf *xmit = &port->state->xmit; 524 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 525 526 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { 527 UART_PUT_CHAR(port, port->x_char); 528 port->icount.tx++; 529 port->x_char = 0; 530 } 531 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 532 return; 533 534 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { 535 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 536 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 537 port->icount.tx++; 538 if (uart_circ_empty(xmit)) 539 break; 540 } 541 542 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 543 uart_write_wakeup(port); 544 545 if (!uart_circ_empty(xmit)) 546 /* Enable interrupts */ 547 UART_PUT_IER(port, atmel_port->tx_done_mask); 548} 549 550/* 551 * receive interrupt handler. 552 */ 553static void 554atmel_handle_receive(struct uart_port *port, unsigned int pending) 555{ 556 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 557 558 if (atmel_use_dma_rx(port)) { 559 /* 560 * PDC receive. Just schedule the tasklet and let it 561 * figure out the details. 562 * 563 * TODO: We're not handling error flags correctly at 564 * the moment. 565 */ 566 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 567 UART_PUT_IDR(port, (ATMEL_US_ENDRX 568 | ATMEL_US_TIMEOUT)); 569 tasklet_schedule(&atmel_port->tasklet); 570 } 571 572 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 573 ATMEL_US_FRAME | ATMEL_US_PARE)) 574 atmel_pdc_rxerr(port, pending); 575 } 576 577 /* Interrupt receive */ 578 if (pending & ATMEL_US_RXRDY) 579 atmel_rx_chars(port); 580 else if (pending & ATMEL_US_RXBRK) { 581 /* 582 * End of break detected. If it came along with a 583 * character, atmel_rx_chars will handle it. 584 */ 585 UART_PUT_CR(port, ATMEL_US_RSTSTA); 586 UART_PUT_IDR(port, ATMEL_US_RXBRK); 587 atmel_port->break_active = 0; 588 } 589} 590 591/* 592 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 593 */ 594static void 595atmel_handle_transmit(struct uart_port *port, unsigned int pending) 596{ 597 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 598 599 if (pending & atmel_port->tx_done_mask) { 600 /* Either PDC or interrupt transmission */ 601 UART_PUT_IDR(port, atmel_port->tx_done_mask); 602 tasklet_schedule(&atmel_port->tasklet); 603 } 604} 605 606/* 607 * status flags interrupt handler. 608 */ 609static void 610atmel_handle_status(struct uart_port *port, unsigned int pending, 611 unsigned int status) 612{ 613 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 614 615 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 616 | ATMEL_US_CTSIC)) { 617 atmel_port->irq_status = status; 618 tasklet_schedule(&atmel_port->tasklet); 619 } 620} 621 622/* 623 * Interrupt handler 624 */ 625static irqreturn_t atmel_interrupt(int irq, void *dev_id) 626{ 627 struct uart_port *port = dev_id; 628 unsigned int status, pending, pass_counter = 0; 629 630 do { 631 status = UART_GET_CSR(port); 632 pending = status & UART_GET_IMR(port); 633 if (!pending) 634 break; 635 636 atmel_handle_receive(port, pending); 637 atmel_handle_status(port, pending, status); 638 atmel_handle_transmit(port, pending); 639 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 640 641 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 642} 643 644/* 645 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 646 */ 647static void atmel_tx_dma(struct uart_port *port) 648{ 649 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 650 struct circ_buf *xmit = &port->state->xmit; 651 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 652 int count; 653 654 /* nothing left to transmit? */ 655 if (UART_GET_TCR(port)) 656 return; 657 658 xmit->tail += pdc->ofs; 659 xmit->tail &= UART_XMIT_SIZE - 1; 660 661 port->icount.tx += pdc->ofs; 662 pdc->ofs = 0; 663 664 /* more to transmit - setup next transfer */ 665 666 /* disable PDC transmit */ 667 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 668 669 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 670 dma_sync_single_for_device(port->dev, 671 pdc->dma_addr, 672 pdc->dma_size, 673 DMA_TO_DEVICE); 674 675 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 676 pdc->ofs = count; 677 678 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); 679 UART_PUT_TCR(port, count); 680 /* re-enable PDC transmit */ 681 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 682 /* Enable interrupts */ 683 UART_PUT_IER(port, atmel_port->tx_done_mask); 684 } else { 685 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 686 /* DMA done, stop TX, start RX for RS485 */ 687 atmel_start_rx(port); 688 } 689 } 690 691 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 692 uart_write_wakeup(port); 693} 694 695static void atmel_rx_from_ring(struct uart_port *port) 696{ 697 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 698 struct circ_buf *ring = &atmel_port->rx_ring; 699 unsigned int flg; 700 unsigned int status; 701 702 while (ring->head != ring->tail) { 703 struct atmel_uart_char c; 704 705 /* Make sure c is loaded after head. */ 706 smp_rmb(); 707 708 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 709 710 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 711 712 port->icount.rx++; 713 status = c.status; 714 flg = TTY_NORMAL; 715 716 /* 717 * note that the error handling code is 718 * out of the main execution path 719 */ 720 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 721 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 722 if (status & ATMEL_US_RXBRK) { 723 /* ignore side-effect */ 724 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 725 726 port->icount.brk++; 727 if (uart_handle_break(port)) 728 continue; 729 } 730 if (status & ATMEL_US_PARE) 731 port->icount.parity++; 732 if (status & ATMEL_US_FRAME) 733 port->icount.frame++; 734 if (status & ATMEL_US_OVRE) 735 port->icount.overrun++; 736 737 status &= port->read_status_mask; 738 739 if (status & ATMEL_US_RXBRK) 740 flg = TTY_BREAK; 741 else if (status & ATMEL_US_PARE) 742 flg = TTY_PARITY; 743 else if (status & ATMEL_US_FRAME) 744 flg = TTY_FRAME; 745 } 746 747 748 if (uart_handle_sysrq_char(port, c.ch)) 749 continue; 750 751 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 752 } 753 754 /* 755 * Drop the lock here since it might end up calling 756 * uart_start(), which takes the lock. 757 */ 758 spin_unlock(&port->lock); 759 tty_flip_buffer_push(port->state->port.tty); 760 spin_lock(&port->lock); 761} 762 763static void atmel_rx_from_dma(struct uart_port *port) 764{ 765 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 766 struct tty_struct *tty = port->state->port.tty; 767 struct atmel_dma_buffer *pdc; 768 int rx_idx = atmel_port->pdc_rx_idx; 769 unsigned int head; 770 unsigned int tail; 771 unsigned int count; 772 773 do { 774 /* Reset the UART timeout early so that we don't miss one */ 775 UART_PUT_CR(port, ATMEL_US_STTTO); 776 777 pdc = &atmel_port->pdc_rx[rx_idx]; 778 head = UART_GET_RPR(port) - pdc->dma_addr; 779 tail = pdc->ofs; 780 781 /* If the PDC has switched buffers, RPR won't contain 782 * any address within the current buffer. Since head 783 * is unsigned, we just need a one-way comparison to 784 * find out. 785 * 786 * In this case, we just need to consume the entire 787 * buffer and resubmit it for DMA. This will clear the 788 * ENDRX bit as well, so that we can safely re-enable 789 * all interrupts below. 790 */ 791 head = min(head, pdc->dma_size); 792 793 if (likely(head != tail)) { 794 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 795 pdc->dma_size, DMA_FROM_DEVICE); 796 797 /* 798 * head will only wrap around when we recycle 799 * the DMA buffer, and when that happens, we 800 * explicitly set tail to 0. So head will 801 * always be greater than tail. 802 */ 803 count = head - tail; 804 805 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); 806 807 dma_sync_single_for_device(port->dev, pdc->dma_addr, 808 pdc->dma_size, DMA_FROM_DEVICE); 809 810 port->icount.rx += count; 811 pdc->ofs = head; 812 } 813 814 /* 815 * If the current buffer is full, we need to check if 816 * the next one contains any additional data. 817 */ 818 if (head >= pdc->dma_size) { 819 pdc->ofs = 0; 820 UART_PUT_RNPR(port, pdc->dma_addr); 821 UART_PUT_RNCR(port, pdc->dma_size); 822 823 rx_idx = !rx_idx; 824 atmel_port->pdc_rx_idx = rx_idx; 825 } 826 } while (head >= pdc->dma_size); 827 828 /* 829 * Drop the lock here since it might end up calling 830 * uart_start(), which takes the lock. 831 */ 832 spin_unlock(&port->lock); 833 tty_flip_buffer_push(tty); 834 spin_lock(&port->lock); 835 836 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 837} 838 839/* 840 * tasklet handling tty stuff outside the interrupt handler. 841 */ 842static void atmel_tasklet_func(unsigned long data) 843{ 844 struct uart_port *port = (struct uart_port *)data; 845 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 846 unsigned int status; 847 unsigned int status_change; 848 849 /* The interrupt handler does not take the lock */ 850 spin_lock(&port->lock); 851 852 if (atmel_use_dma_tx(port)) 853 atmel_tx_dma(port); 854 else 855 atmel_tx_chars(port); 856 857 status = atmel_port->irq_status; 858 status_change = status ^ atmel_port->irq_status_prev; 859 860 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 861 | ATMEL_US_DCD | ATMEL_US_CTS)) { 862 /* TODO: All reads to CSR will clear these interrupts! */ 863 if (status_change & ATMEL_US_RI) 864 port->icount.rng++; 865 if (status_change & ATMEL_US_DSR) 866 port->icount.dsr++; 867 if (status_change & ATMEL_US_DCD) 868 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 869 if (status_change & ATMEL_US_CTS) 870 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 871 872 wake_up_interruptible(&port->state->port.delta_msr_wait); 873 874 atmel_port->irq_status_prev = status; 875 } 876 877 if (atmel_use_dma_rx(port)) 878 atmel_rx_from_dma(port); 879 else 880 atmel_rx_from_ring(port); 881 882 spin_unlock(&port->lock); 883} 884 885/* 886 * Perform initialization and enable port for reception 887 */ 888static int atmel_startup(struct uart_port *port) 889{ 890 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 891 struct tty_struct *tty = port->state->port.tty; 892 int retval; 893 894 /* 895 * Ensure that no interrupts are enabled otherwise when 896 * request_irq() is called we could get stuck trying to 897 * handle an unexpected interrupt 898 */ 899 UART_PUT_IDR(port, -1); 900 901 /* 902 * Allocate the IRQ 903 */ 904 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, 905 tty ? tty->name : "atmel_serial", port); 906 if (retval) { 907 printk("atmel_serial: atmel_startup - Can't get irq\n"); 908 return retval; 909 } 910 911 /* 912 * Initialize DMA (if necessary) 913 */ 914 if (atmel_use_dma_rx(port)) { 915 int i; 916 917 for (i = 0; i < 2; i++) { 918 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 919 920 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 921 if (pdc->buf == NULL) { 922 if (i != 0) { 923 dma_unmap_single(port->dev, 924 atmel_port->pdc_rx[0].dma_addr, 925 PDC_BUFFER_SIZE, 926 DMA_FROM_DEVICE); 927 kfree(atmel_port->pdc_rx[0].buf); 928 } 929 free_irq(port->irq, port); 930 return -ENOMEM; 931 } 932 pdc->dma_addr = dma_map_single(port->dev, 933 pdc->buf, 934 PDC_BUFFER_SIZE, 935 DMA_FROM_DEVICE); 936 pdc->dma_size = PDC_BUFFER_SIZE; 937 pdc->ofs = 0; 938 } 939 940 atmel_port->pdc_rx_idx = 0; 941 942 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); 943 UART_PUT_RCR(port, PDC_BUFFER_SIZE); 944 945 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); 946 UART_PUT_RNCR(port, PDC_BUFFER_SIZE); 947 } 948 if (atmel_use_dma_tx(port)) { 949 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 950 struct circ_buf *xmit = &port->state->xmit; 951 952 pdc->buf = xmit->buf; 953 pdc->dma_addr = dma_map_single(port->dev, 954 pdc->buf, 955 UART_XMIT_SIZE, 956 DMA_TO_DEVICE); 957 pdc->dma_size = UART_XMIT_SIZE; 958 pdc->ofs = 0; 959 } 960 961 /* 962 * If there is a specific "open" function (to register 963 * control line interrupts) 964 */ 965 if (atmel_open_hook) { 966 retval = atmel_open_hook(port); 967 if (retval) { 968 free_irq(port->irq, port); 969 return retval; 970 } 971 } 972 973 /* Save current CSR for comparison in atmel_tasklet_func() */ 974 atmel_port->irq_status_prev = UART_GET_CSR(port); 975 atmel_port->irq_status = atmel_port->irq_status_prev; 976 977 /* 978 * Finally, enable the serial port 979 */ 980 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 981 /* enable xmit & rcvr */ 982 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 983 984 if (atmel_use_dma_rx(port)) { 985 /* set UART timeout */ 986 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 987 UART_PUT_CR(port, ATMEL_US_STTTO); 988 989 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 990 /* enable PDC controller */ 991 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 992 } else { 993 /* enable receive only */ 994 UART_PUT_IER(port, ATMEL_US_RXRDY); 995 } 996 997 return 0; 998} 999 1000/* 1001 * Disable the port 1002 */ 1003static void atmel_shutdown(struct uart_port *port) 1004{ 1005 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1006 /* 1007 * Ensure everything is stopped. 1008 */ 1009 atmel_stop_rx(port); 1010 atmel_stop_tx(port); 1011 1012 /* 1013 * Shut-down the DMA. 1014 */ 1015 if (atmel_use_dma_rx(port)) { 1016 int i; 1017 1018 for (i = 0; i < 2; i++) { 1019 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1020 1021 dma_unmap_single(port->dev, 1022 pdc->dma_addr, 1023 pdc->dma_size, 1024 DMA_FROM_DEVICE); 1025 kfree(pdc->buf); 1026 } 1027 } 1028 if (atmel_use_dma_tx(port)) { 1029 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1030 1031 dma_unmap_single(port->dev, 1032 pdc->dma_addr, 1033 pdc->dma_size, 1034 DMA_TO_DEVICE); 1035 } 1036 1037 /* 1038 * Disable all interrupts, port and break condition. 1039 */ 1040 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1041 UART_PUT_IDR(port, -1); 1042 1043 /* 1044 * Free the interrupt 1045 */ 1046 free_irq(port->irq, port); 1047 1048 /* 1049 * If there is a specific "close" function (to unregister 1050 * control line interrupts) 1051 */ 1052 if (atmel_close_hook) 1053 atmel_close_hook(port); 1054} 1055 1056/* 1057 * Flush any TX data submitted for DMA. Called when the TX circular 1058 * buffer is reset. 1059 */ 1060static void atmel_flush_buffer(struct uart_port *port) 1061{ 1062 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1063 1064 if (atmel_use_dma_tx(port)) { 1065 UART_PUT_TCR(port, 0); 1066 atmel_port->pdc_tx.ofs = 0; 1067 } 1068} 1069 1070/* 1071 * Power / Clock management. 1072 */ 1073static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1074 unsigned int oldstate) 1075{ 1076 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1077 1078 switch (state) { 1079 case 0: 1080 /* 1081 * Enable the peripheral clock for this serial port. 1082 * This is called on uart_open() or a resume event. 1083 */ 1084 clk_enable(atmel_port->clk); 1085 1086 /* re-enable interrupts if we disabled some on suspend */ 1087 UART_PUT_IER(port, atmel_port->backup_imr); 1088 break; 1089 case 3: 1090 /* Back up the interrupt mask and disable all interrupts */ 1091 atmel_port->backup_imr = UART_GET_IMR(port); 1092 UART_PUT_IDR(port, -1); 1093 1094 /* 1095 * Disable the peripheral clock for this serial port. 1096 * This is called on uart_close() or a suspend event. 1097 */ 1098 clk_disable(atmel_port->clk); 1099 break; 1100 default: 1101 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); 1102 } 1103} 1104 1105/* 1106 * Change the port parameters 1107 */ 1108static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1109 struct ktermios *old) 1110{ 1111 unsigned long flags; 1112 unsigned int mode, imr, quot, baud; 1113 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1114 1115 /* Get current mode register */ 1116 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL 1117 | ATMEL_US_NBSTOP | ATMEL_US_PAR 1118 | ATMEL_US_USMODE); 1119 1120 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1121 quot = uart_get_divisor(port, baud); 1122 1123 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 1124 quot /= 8; 1125 mode |= ATMEL_US_USCLKS_MCK_DIV8; 1126 } 1127 1128 /* byte size */ 1129 switch (termios->c_cflag & CSIZE) { 1130 case CS5: 1131 mode |= ATMEL_US_CHRL_5; 1132 break; 1133 case CS6: 1134 mode |= ATMEL_US_CHRL_6; 1135 break; 1136 case CS7: 1137 mode |= ATMEL_US_CHRL_7; 1138 break; 1139 default: 1140 mode |= ATMEL_US_CHRL_8; 1141 break; 1142 } 1143 1144 /* stop bits */ 1145 if (termios->c_cflag & CSTOPB) 1146 mode |= ATMEL_US_NBSTOP_2; 1147 1148 /* parity */ 1149 if (termios->c_cflag & PARENB) { 1150 /* Mark or Space parity */ 1151 if (termios->c_cflag & CMSPAR) { 1152 if (termios->c_cflag & PARODD) 1153 mode |= ATMEL_US_PAR_MARK; 1154 else 1155 mode |= ATMEL_US_PAR_SPACE; 1156 } else if (termios->c_cflag & PARODD) 1157 mode |= ATMEL_US_PAR_ODD; 1158 else 1159 mode |= ATMEL_US_PAR_EVEN; 1160 } else 1161 mode |= ATMEL_US_PAR_NONE; 1162 1163 /* hardware handshake (RTS/CTS) */ 1164 if (termios->c_cflag & CRTSCTS) 1165 mode |= ATMEL_US_USMODE_HWHS; 1166 else 1167 mode |= ATMEL_US_USMODE_NORMAL; 1168 1169 spin_lock_irqsave(&port->lock, flags); 1170 1171 port->read_status_mask = ATMEL_US_OVRE; 1172 if (termios->c_iflag & INPCK) 1173 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 1174 if (termios->c_iflag & (BRKINT | PARMRK)) 1175 port->read_status_mask |= ATMEL_US_RXBRK; 1176 1177 if (atmel_use_dma_rx(port)) 1178 /* need to enable error interrupts */ 1179 UART_PUT_IER(port, port->read_status_mask); 1180 1181 /* 1182 * Characters to ignore 1183 */ 1184 port->ignore_status_mask = 0; 1185 if (termios->c_iflag & IGNPAR) 1186 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 1187 if (termios->c_iflag & IGNBRK) { 1188 port->ignore_status_mask |= ATMEL_US_RXBRK; 1189 /* 1190 * If we're ignoring parity and break indicators, 1191 * ignore overruns too (for real raw support). 1192 */ 1193 if (termios->c_iflag & IGNPAR) 1194 port->ignore_status_mask |= ATMEL_US_OVRE; 1195 } 1196 /* TODO: Ignore all characters if CREAD is set.*/ 1197 1198 /* update the per-port timeout */ 1199 uart_update_timeout(port, termios->c_cflag, baud); 1200 1201 /* 1202 * save/disable interrupts. The tty layer will ensure that the 1203 * transmitter is empty if requested by the caller, so there's 1204 * no need to wait for it here. 1205 */ 1206 imr = UART_GET_IMR(port); 1207 UART_PUT_IDR(port, -1); 1208 1209 /* disable receiver and transmitter */ 1210 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 1211 1212 /* Resetting serial mode to RS232 (0x0) */ 1213 mode &= ~ATMEL_US_USMODE; 1214 1215 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 1216 dev_dbg(port->dev, "Setting UART to RS485\n"); 1217 if (atmel_port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1218 UART_PUT_TTGR(port, 1219 atmel_port->rs485.delay_rts_after_send); 1220 mode |= ATMEL_US_USMODE_RS485; 1221 } else { 1222 dev_dbg(port->dev, "Setting UART to RS232\n"); 1223 } 1224 1225 /* set the parity, stop bits and data size */ 1226 UART_PUT_MR(port, mode); 1227 1228 /* set the baud rate */ 1229 UART_PUT_BRGR(port, quot); 1230 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1231 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1232 1233 /* restore interrupts */ 1234 UART_PUT_IER(port, imr); 1235 1236 /* CTS flow-control and modem-status interrupts */ 1237 if (UART_ENABLE_MS(port, termios->c_cflag)) 1238 port->ops->enable_ms(port); 1239 1240 spin_unlock_irqrestore(&port->lock, flags); 1241} 1242 1243/* 1244 * Return string describing the specified port 1245 */ 1246static const char *atmel_type(struct uart_port *port) 1247{ 1248 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 1249} 1250 1251/* 1252 * Release the memory region(s) being used by 'port'. 1253 */ 1254static void atmel_release_port(struct uart_port *port) 1255{ 1256 struct platform_device *pdev = to_platform_device(port->dev); 1257 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 1258 1259 release_mem_region(port->mapbase, size); 1260 1261 if (port->flags & UPF_IOREMAP) { 1262 iounmap(port->membase); 1263 port->membase = NULL; 1264 } 1265} 1266 1267/* 1268 * Request the memory region(s) being used by 'port'. 1269 */ 1270static int atmel_request_port(struct uart_port *port) 1271{ 1272 struct platform_device *pdev = to_platform_device(port->dev); 1273 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 1274 1275 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 1276 return -EBUSY; 1277 1278 if (port->flags & UPF_IOREMAP) { 1279 port->membase = ioremap(port->mapbase, size); 1280 if (port->membase == NULL) { 1281 release_mem_region(port->mapbase, size); 1282 return -ENOMEM; 1283 } 1284 } 1285 1286 return 0; 1287} 1288 1289/* 1290 * Configure/autoconfigure the port. 1291 */ 1292static void atmel_config_port(struct uart_port *port, int flags) 1293{ 1294 if (flags & UART_CONFIG_TYPE) { 1295 port->type = PORT_ATMEL; 1296 atmel_request_port(port); 1297 } 1298} 1299 1300/* 1301 * Verify the new serial_struct (for TIOCSSERIAL). 1302 */ 1303static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 1304{ 1305 int ret = 0; 1306 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 1307 ret = -EINVAL; 1308 if (port->irq != ser->irq) 1309 ret = -EINVAL; 1310 if (ser->io_type != SERIAL_IO_MEM) 1311 ret = -EINVAL; 1312 if (port->uartclk / 16 != ser->baud_base) 1313 ret = -EINVAL; 1314 if ((void *)port->mapbase != ser->iomem_base) 1315 ret = -EINVAL; 1316 if (port->iobase != ser->port) 1317 ret = -EINVAL; 1318 if (ser->hub6 != 0) 1319 ret = -EINVAL; 1320 return ret; 1321} 1322 1323#ifdef CONFIG_CONSOLE_POLL 1324static int atmel_poll_get_char(struct uart_port *port) 1325{ 1326 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) 1327 cpu_relax(); 1328 1329 return UART_GET_CHAR(port); 1330} 1331 1332static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 1333{ 1334 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 1335 cpu_relax(); 1336 1337 UART_PUT_CHAR(port, ch); 1338} 1339#endif 1340 1341static int 1342atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) 1343{ 1344 struct serial_rs485 rs485conf; 1345 1346 switch (cmd) { 1347 case TIOCSRS485: 1348 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, 1349 sizeof(rs485conf))) 1350 return -EFAULT; 1351 1352 atmel_config_rs485(port, &rs485conf); 1353 break; 1354 1355 case TIOCGRS485: 1356 if (copy_to_user((struct serial_rs485 *) arg, 1357 &(to_atmel_uart_port(port)->rs485), 1358 sizeof(rs485conf))) 1359 return -EFAULT; 1360 break; 1361 1362 default: 1363 return -ENOIOCTLCMD; 1364 } 1365 return 0; 1366} 1367 1368 1369 1370static struct uart_ops atmel_pops = { 1371 .tx_empty = atmel_tx_empty, 1372 .set_mctrl = atmel_set_mctrl, 1373 .get_mctrl = atmel_get_mctrl, 1374 .stop_tx = atmel_stop_tx, 1375 .start_tx = atmel_start_tx, 1376 .stop_rx = atmel_stop_rx, 1377 .enable_ms = atmel_enable_ms, 1378 .break_ctl = atmel_break_ctl, 1379 .startup = atmel_startup, 1380 .shutdown = atmel_shutdown, 1381 .flush_buffer = atmel_flush_buffer, 1382 .set_termios = atmel_set_termios, 1383 .type = atmel_type, 1384 .release_port = atmel_release_port, 1385 .request_port = atmel_request_port, 1386 .config_port = atmel_config_port, 1387 .verify_port = atmel_verify_port, 1388 .pm = atmel_serial_pm, 1389 .ioctl = atmel_ioctl, 1390#ifdef CONFIG_CONSOLE_POLL 1391 .poll_get_char = atmel_poll_get_char, 1392 .poll_put_char = atmel_poll_put_char, 1393#endif 1394}; 1395 1396/* 1397 * Configure the port from the platform device resource info. 1398 */ 1399static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, 1400 struct platform_device *pdev) 1401{ 1402 struct uart_port *port = &atmel_port->uart; 1403 struct atmel_uart_data *data = pdev->dev.platform_data; 1404 1405 port->iotype = UPIO_MEM; 1406 port->flags = UPF_BOOT_AUTOCONF; 1407 port->ops = &atmel_pops; 1408 port->fifosize = 1; 1409 port->line = pdev->id; 1410 port->dev = &pdev->dev; 1411 port->mapbase = pdev->resource[0].start; 1412 port->irq = pdev->resource[1].start; 1413 1414 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 1415 (unsigned long)port); 1416 1417 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 1418 1419 if (data->regs) 1420 /* Already mapped by setup code */ 1421 port->membase = data->regs; 1422 else { 1423 port->flags |= UPF_IOREMAP; 1424 port->membase = NULL; 1425 } 1426 1427 /* for console, the clock could already be configured */ 1428 if (!atmel_port->clk) { 1429 atmel_port->clk = clk_get(&pdev->dev, "usart"); 1430 clk_enable(atmel_port->clk); 1431 port->uartclk = clk_get_rate(atmel_port->clk); 1432 clk_disable(atmel_port->clk); 1433 /* only enable clock when USART is in use */ 1434 } 1435 1436 atmel_port->use_dma_rx = data->use_dma_rx; 1437 atmel_port->use_dma_tx = data->use_dma_tx; 1438 atmel_port->rs485 = data->rs485; 1439 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 1440 if (atmel_port->rs485.flags & SER_RS485_ENABLED) 1441 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 1442 else if (atmel_use_dma_tx(port)) { 1443 port->fifosize = PDC_BUFFER_SIZE; 1444 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 1445 } else { 1446 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 1447 } 1448} 1449 1450/* 1451 * Register board-specific modem-control line handlers. 1452 */ 1453void __init atmel_register_uart_fns(struct atmel_port_fns *fns) 1454{ 1455 if (fns->enable_ms) 1456 atmel_pops.enable_ms = fns->enable_ms; 1457 if (fns->get_mctrl) 1458 atmel_pops.get_mctrl = fns->get_mctrl; 1459 if (fns->set_mctrl) 1460 atmel_pops.set_mctrl = fns->set_mctrl; 1461 atmel_open_hook = fns->open; 1462 atmel_close_hook = fns->close; 1463 atmel_pops.pm = fns->pm; 1464 atmel_pops.set_wake = fns->set_wake; 1465} 1466 1467#ifdef CONFIG_SERIAL_ATMEL_CONSOLE 1468static void atmel_console_putchar(struct uart_port *port, int ch) 1469{ 1470 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 1471 cpu_relax(); 1472 UART_PUT_CHAR(port, ch); 1473} 1474 1475/* 1476 * Interrupts are disabled on entering 1477 */ 1478static void atmel_console_write(struct console *co, const char *s, u_int count) 1479{ 1480 struct uart_port *port = &atmel_ports[co->index].uart; 1481 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1482 unsigned int status, imr; 1483 unsigned int pdc_tx; 1484 1485 /* 1486 * First, save IMR and then disable interrupts 1487 */ 1488 imr = UART_GET_IMR(port); 1489 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); 1490 1491 /* Store PDC transmit status and disable it */ 1492 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; 1493 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 1494 1495 uart_console_write(port, s, count, atmel_console_putchar); 1496 1497 /* 1498 * Finally, wait for transmitter to become empty 1499 * and restore IMR 1500 */ 1501 do { 1502 status = UART_GET_CSR(port); 1503 } while (!(status & ATMEL_US_TXRDY)); 1504 1505 /* Restore PDC transmit status */ 1506 if (pdc_tx) 1507 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 1508 1509 /* set interrupts back the way they were */ 1510 UART_PUT_IER(port, imr); 1511} 1512 1513/* 1514 * If the port was already initialised (eg, by a boot loader), 1515 * try to determine the current setup. 1516 */ 1517static void __init atmel_console_get_options(struct uart_port *port, int *baud, 1518 int *parity, int *bits) 1519{ 1520 unsigned int mr, quot; 1521 1522 /* 1523 * If the baud rate generator isn't running, the port wasn't 1524 * initialized by the boot loader. 1525 */ 1526 quot = UART_GET_BRGR(port) & ATMEL_US_CD; 1527 if (!quot) 1528 return; 1529 1530 mr = UART_GET_MR(port) & ATMEL_US_CHRL; 1531 if (mr == ATMEL_US_CHRL_8) 1532 *bits = 8; 1533 else 1534 *bits = 7; 1535 1536 mr = UART_GET_MR(port) & ATMEL_US_PAR; 1537 if (mr == ATMEL_US_PAR_EVEN) 1538 *parity = 'e'; 1539 else if (mr == ATMEL_US_PAR_ODD) 1540 *parity = 'o'; 1541 1542 /* 1543 * The serial core only rounds down when matching this to a 1544 * supported baud rate. Make sure we don't end up slightly 1545 * lower than one of those, as it would make us fall through 1546 * to a much lower baud rate than we really want. 1547 */ 1548 *baud = port->uartclk / (16 * (quot - 1)); 1549} 1550 1551static int __init atmel_console_setup(struct console *co, char *options) 1552{ 1553 struct uart_port *port = &atmel_ports[co->index].uart; 1554 int baud = 115200; 1555 int bits = 8; 1556 int parity = 'n'; 1557 int flow = 'n'; 1558 1559 if (port->membase == NULL) { 1560 /* Port not initialized yet - delay setup */ 1561 return -ENODEV; 1562 } 1563 1564 clk_enable(atmel_ports[co->index].clk); 1565 1566 UART_PUT_IDR(port, -1); 1567 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1568 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1569 1570 if (options) 1571 uart_parse_options(options, &baud, &parity, &bits, &flow); 1572 else 1573 atmel_console_get_options(port, &baud, &parity, &bits); 1574 1575 return uart_set_options(port, co, baud, parity, bits, flow); 1576} 1577 1578static struct uart_driver atmel_uart; 1579 1580static struct console atmel_console = { 1581 .name = ATMEL_DEVICENAME, 1582 .write = atmel_console_write, 1583 .device = uart_console_device, 1584 .setup = atmel_console_setup, 1585 .flags = CON_PRINTBUFFER, 1586 .index = -1, 1587 .data = &atmel_uart, 1588}; 1589 1590#define ATMEL_CONSOLE_DEVICE (&atmel_console) 1591 1592/* 1593 * Early console initialization (before VM subsystem initialized). 1594 */ 1595static int __init atmel_console_init(void) 1596{ 1597 if (atmel_default_console_device) { 1598 add_preferred_console(ATMEL_DEVICENAME, 1599 atmel_default_console_device->id, NULL); 1600 atmel_init_port(&atmel_ports[atmel_default_console_device->id], 1601 atmel_default_console_device); 1602 register_console(&atmel_console); 1603 } 1604 1605 return 0; 1606} 1607 1608console_initcall(atmel_console_init); 1609 1610/* 1611 * Late console initialization. 1612 */ 1613static int __init atmel_late_console_init(void) 1614{ 1615 if (atmel_default_console_device 1616 && !(atmel_console.flags & CON_ENABLED)) 1617 register_console(&atmel_console); 1618 1619 return 0; 1620} 1621 1622core_initcall(atmel_late_console_init); 1623 1624static inline bool atmel_is_console_port(struct uart_port *port) 1625{ 1626 return port->cons && port->cons->index == port->line; 1627} 1628 1629#else 1630#define ATMEL_CONSOLE_DEVICE NULL 1631 1632static inline bool atmel_is_console_port(struct uart_port *port) 1633{ 1634 return false; 1635} 1636#endif 1637 1638static struct uart_driver atmel_uart = { 1639 .owner = THIS_MODULE, 1640 .driver_name = "atmel_serial", 1641 .dev_name = ATMEL_DEVICENAME, 1642 .major = SERIAL_ATMEL_MAJOR, 1643 .minor = MINOR_START, 1644 .nr = ATMEL_MAX_UART, 1645 .cons = ATMEL_CONSOLE_DEVICE, 1646}; 1647 1648#ifdef CONFIG_PM 1649static bool atmel_serial_clk_will_stop(void) 1650{ 1651#ifdef CONFIG_ARCH_AT91 1652 return at91_suspend_entering_slow_clock(); 1653#else 1654 return false; 1655#endif 1656} 1657 1658static int atmel_serial_suspend(struct platform_device *pdev, 1659 pm_message_t state) 1660{ 1661 struct uart_port *port = platform_get_drvdata(pdev); 1662 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1663 1664 if (atmel_is_console_port(port) && console_suspend_enabled) { 1665 /* Drain the TX shifter */ 1666 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) 1667 cpu_relax(); 1668 } 1669 1670 /* we can not wake up if we're running on slow clock */ 1671 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 1672 if (atmel_serial_clk_will_stop()) 1673 device_set_wakeup_enable(&pdev->dev, 0); 1674 1675 uart_suspend_port(&atmel_uart, port); 1676 1677 return 0; 1678} 1679 1680static int atmel_serial_resume(struct platform_device *pdev) 1681{ 1682 struct uart_port *port = platform_get_drvdata(pdev); 1683 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1684 1685 uart_resume_port(&atmel_uart, port); 1686 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 1687 1688 return 0; 1689} 1690#else 1691#define atmel_serial_suspend NULL 1692#define atmel_serial_resume NULL 1693#endif 1694 1695static int __devinit atmel_serial_probe(struct platform_device *pdev) 1696{ 1697 struct atmel_uart_port *port; 1698 void *data; 1699 int ret; 1700 1701 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 1702 1703 port = &atmel_ports[pdev->id]; 1704 port->backup_imr = 0; 1705 1706 atmel_init_port(port, pdev); 1707 1708 if (!atmel_use_dma_rx(&port->uart)) { 1709 ret = -ENOMEM; 1710 data = kmalloc(sizeof(struct atmel_uart_char) 1711 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 1712 if (!data) 1713 goto err_alloc_ring; 1714 port->rx_ring.buf = data; 1715 } 1716 1717 ret = uart_add_one_port(&atmel_uart, &port->uart); 1718 if (ret) 1719 goto err_add_port; 1720 1721#ifdef CONFIG_SERIAL_ATMEL_CONSOLE 1722 if (atmel_is_console_port(&port->uart) 1723 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 1724 /* 1725 * The serial core enabled the clock for us, so undo 1726 * the clk_enable() in atmel_console_setup() 1727 */ 1728 clk_disable(port->clk); 1729 } 1730#endif 1731 1732 device_init_wakeup(&pdev->dev, 1); 1733 platform_set_drvdata(pdev, port); 1734 1735 return 0; 1736 1737err_add_port: 1738 kfree(port->rx_ring.buf); 1739 port->rx_ring.buf = NULL; 1740err_alloc_ring: 1741 if (!atmel_is_console_port(&port->uart)) { 1742 clk_put(port->clk); 1743 port->clk = NULL; 1744 } 1745 1746 return ret; 1747} 1748 1749static int __devexit atmel_serial_remove(struct platform_device *pdev) 1750{ 1751 struct uart_port *port = platform_get_drvdata(pdev); 1752 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1753 int ret = 0; 1754 1755 device_init_wakeup(&pdev->dev, 0); 1756 platform_set_drvdata(pdev, NULL); 1757 1758 ret = uart_remove_one_port(&atmel_uart, port); 1759 1760 tasklet_kill(&atmel_port->tasklet); 1761 kfree(atmel_port->rx_ring.buf); 1762 1763 /* "port" is allocated statically, so we shouldn't free it */ 1764 1765 clk_put(atmel_port->clk); 1766 1767 return ret; 1768} 1769 1770static struct platform_driver atmel_serial_driver = { 1771 .probe = atmel_serial_probe, 1772 .remove = __devexit_p(atmel_serial_remove), 1773 .suspend = atmel_serial_suspend, 1774 .resume = atmel_serial_resume, 1775 .driver = { 1776 .name = "atmel_usart", 1777 .owner = THIS_MODULE, 1778 }, 1779}; 1780 1781static int __init atmel_serial_init(void) 1782{ 1783 int ret; 1784 1785 ret = uart_register_driver(&atmel_uart); 1786 if (ret) 1787 return ret; 1788 1789 ret = platform_driver_register(&atmel_serial_driver); 1790 if (ret) 1791 uart_unregister_driver(&atmel_uart); 1792 1793 return ret; 1794} 1795 1796static void __exit atmel_serial_exit(void) 1797{ 1798 platform_driver_unregister(&atmel_serial_driver); 1799 uart_unregister_driver(&atmel_uart); 1800} 1801 1802module_init(atmel_serial_init); 1803module_exit(atmel_serial_exit); 1804 1805MODULE_AUTHOR("Rick Bronson"); 1806MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); 1807MODULE_LICENSE("GPL"); 1808MODULE_ALIAS("platform:atmel_usart"); 1809