1/* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2006 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8#ifndef _QLA4X_FW_H 9#define _QLA4X_FW_H 10 11 12#define MAX_PRST_DEV_DB_ENTRIES 64 13#define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES 14#define MAX_DEV_DB_ENTRIES 512 15 16/************************************************************************* 17 * 18 * ISP 4010 I/O Register Set Structure and Definitions 19 * 20 *************************************************************************/ 21 22struct port_ctrl_stat_regs { 23 __le32 ext_hw_conf; /* 0x50 R/W */ 24 __le32 rsrvd0; /* 0x54 */ 25 __le32 port_ctrl; /* 0x58 */ 26 __le32 port_status; /* 0x5c */ 27 __le32 rsrvd1[32]; /* 0x60-0xdf */ 28 __le32 gp_out; /* 0xe0 */ 29 __le32 gp_in; /* 0xe4 */ 30 __le32 rsrvd2[5]; /* 0xe8-0xfb */ 31 __le32 port_err_status; /* 0xfc */ 32}; 33 34struct host_mem_cfg_regs { 35 __le32 rsrvd0[12]; /* 0x50-0x79 */ 36 __le32 req_q_out; /* 0x80 */ 37 __le32 rsrvd1[31]; /* 0x84-0xFF */ 38}; 39 40/* 41 * ISP 82xx I/O Register Set structure definitions. 42 */ 43struct device_reg_82xx { 44 __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */ 45 __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */ 46 __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */ 47 __le32 reserve2[63]; /* Response Queue In-Pointer. */ 48 __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */ 49 __le32 reserve3[63]; /* Response Queue Out-Pointer. */ 50 51 __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */ 52 __le32 reserve4[24]; 53 __le32 hint; /* 0x0380 (R/W): Host interrupt register */ 54#define HINT_MBX_INT_PENDING BIT_0 55 __le32 reserve5[31]; 56 __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */ 57 __le32 reserve6[56]; 58 59 __le32 host_status; /* Offset 0x500 (R): host status */ 60#define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ 61#define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */ 62 63 __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */ 64#define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ 65}; 66 67/* remote register set (access via PCI memory read/write) */ 68struct isp_reg { 69#define MBOX_REG_COUNT 8 70 __le32 mailbox[MBOX_REG_COUNT]; 71 72 __le32 flash_address; /* 0x20 */ 73 __le32 flash_data; 74 __le32 ctrl_status; 75 76 union { 77 struct { 78 __le32 nvram; 79 __le32 reserved1[2]; /* 0x30 */ 80 } __attribute__ ((packed)) isp4010; 81 struct { 82 __le32 intr_mask; 83 __le32 nvram; /* 0x30 */ 84 __le32 semaphore; 85 } __attribute__ ((packed)) isp4022; 86 } u1; 87 88 __le32 req_q_in; /* SCSI Request Queue Producer Index */ 89 __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */ 90 91 __le32 reserved2[4]; /* 0x40 */ 92 93 union { 94 struct { 95 __le32 ext_hw_conf; /* 0x50 */ 96 __le32 flow_ctrl; 97 __le32 port_ctrl; 98 __le32 port_status; 99 100 __le32 reserved3[8]; /* 0x60 */ 101 102 __le32 req_q_out; /* 0x80 */ 103 104 __le32 reserved4[23]; /* 0x84 */ 105 106 __le32 gp_out; /* 0xe0 */ 107 __le32 gp_in; 108 109 __le32 reserved5[5]; 110 111 __le32 port_err_status; /* 0xfc */ 112 } __attribute__ ((packed)) isp4010; 113 struct { 114 union { 115 struct port_ctrl_stat_regs p0; 116 struct host_mem_cfg_regs p1; 117 }; 118 } __attribute__ ((packed)) isp4022; 119 } u2; 120}; /* 256 x100 */ 121 122 123/* Semaphore Defines for 4010 */ 124#define QL4010_DRVR_SEM_BITS 0x00000030 125#define QL4010_GPIO_SEM_BITS 0x000000c0 126#define QL4010_SDRAM_SEM_BITS 0x00000300 127#define QL4010_PHY_SEM_BITS 0x00000c00 128#define QL4010_NVRAM_SEM_BITS 0x00003000 129#define QL4010_FLASH_SEM_BITS 0x0000c000 130 131#define QL4010_DRVR_SEM_MASK 0x00300000 132#define QL4010_GPIO_SEM_MASK 0x00c00000 133#define QL4010_SDRAM_SEM_MASK 0x03000000 134#define QL4010_PHY_SEM_MASK 0x0c000000 135#define QL4010_NVRAM_SEM_MASK 0x30000000 136#define QL4010_FLASH_SEM_MASK 0xc0000000 137 138/* Semaphore Defines for 4022 */ 139#define QL4022_RESOURCE_MASK_BASE_CODE 0x7 140#define QL4022_RESOURCE_BITS_BASE_CODE 0x4 141 142 143#define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16)) 144#define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16)) 145#define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16)) 146#define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16)) 147#define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16)) 148 149 150 151/* Page # defines for 4022 */ 152#define PORT_CTRL_STAT_PAGE 0 /* 4022 */ 153#define HOST_MEM_CFG_PAGE 1 /* 4022 */ 154#define LOCAL_RAM_CFG_PAGE 2 /* 4022 */ 155#define PROT_STAT_PAGE 3 /* 4022 */ 156 157/* Register Mask - sets corresponding mask bits in the upper word */ 158static inline uint32_t set_rmask(uint32_t val) 159{ 160 return (val & 0xffff) | (val << 16); 161} 162 163 164static inline uint32_t clr_rmask(uint32_t val) 165{ 166 return 0 | (val << 16); 167} 168 169/* ctrl_status definitions */ 170#define CSR_SCSI_PAGE_SELECT 0x00000003 171#define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */ 172#define CSR_SCSI_RESET_INTR 0x00000008 173#define CSR_SCSI_COMPLETION_INTR 0x00000010 174#define CSR_SCSI_PROCESSOR_INTR 0x00000020 175#define CSR_INTR_RISC 0x00000040 176#define CSR_BOOT_ENABLE 0x00000080 177#define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */ 178#define CSR_FUNC_NUM 0x00000700 /* 4022 */ 179#define CSR_NET_RESET_INTR 0x00000800 /* 4010 */ 180#define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */ 181#define CSR_FATAL_ERROR 0x00004000 182#define CSR_SOFT_RESET 0x00008000 183#define ISP_CONTROL_FN_MASK CSR_FUNC_NUM 184#define ISP_CONTROL_FN0_SCSI 0x0500 185#define ISP_CONTROL_FN1_SCSI 0x0700 186 187#define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\ 188 CSR_SCSI_PROCESSOR_INTR |\ 189 CSR_SCSI_RESET_INTR) 190 191/* ISP InterruptMask definitions */ 192#define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */ 193 194/* ISP 4022 nvram definitions */ 195#define NVR_WRITE_ENABLE 0x00000010 /* 4022 */ 196 197/* ISP port_status definitions */ 198 199/* ISP Semaphore definitions */ 200 201/* ISP General Purpose Output definitions */ 202#define GPOR_TOPCAT_RESET 0x00000004 203 204/* shadow registers (DMA'd from HA to system memory. read only) */ 205struct shadow_regs { 206 /* SCSI Request Queue Consumer Index */ 207 __le32 req_q_out; /* 0 x0 R */ 208 209 /* SCSI Completion Queue Producer Index */ 210 __le32 rsp_q_in; /* 4 x4 R */ 211}; /* 8 x8 */ 212 213 214/* External hardware configuration register */ 215union external_hw_config_reg { 216 struct { 217 __le32 bReserved0:1; 218 __le32 bSDRAMProtectionMethod:2; 219 __le32 bSDRAMBanks:1; 220 __le32 bSDRAMChipWidth:1; 221 __le32 bSDRAMChipSize:2; 222 __le32 bParityDisable:1; 223 __le32 bExternalMemoryType:1; 224 __le32 bFlashBIOSWriteEnable:1; 225 __le32 bFlashUpperBankSelect:1; 226 __le32 bWriteBurst:2; 227 __le32 bReserved1:3; 228 __le32 bMask:16; 229 }; 230 uint32_t Asuint32_t; 231}; 232 233/* 82XX Support start */ 234/* 82xx Default FLT Addresses */ 235#define FA_FLASH_LAYOUT_ADDR_82 0xFC400 236#define FA_FLASH_DESCR_ADDR_82 0xFC000 237#define FA_BOOT_LOAD_ADDR_82 0x04000 238#define FA_BOOT_CODE_ADDR_82 0x20000 239#define FA_RISC_CODE_ADDR_82 0x40000 240#define FA_GOLD_RISC_CODE_ADDR_82 0x80000 241 242/* Flash Description Table */ 243struct qla_fdt_layout { 244 uint8_t sig[4]; 245 uint16_t version; 246 uint16_t len; 247 uint16_t checksum; 248 uint8_t unused1[2]; 249 uint8_t model[16]; 250 uint16_t man_id; 251 uint16_t id; 252 uint8_t flags; 253 uint8_t erase_cmd; 254 uint8_t alt_erase_cmd; 255 uint8_t wrt_enable_cmd; 256 uint8_t wrt_enable_bits; 257 uint8_t wrt_sts_reg_cmd; 258 uint8_t unprotect_sec_cmd; 259 uint8_t read_man_id_cmd; 260 uint32_t block_size; 261 uint32_t alt_block_size; 262 uint32_t flash_size; 263 uint32_t wrt_enable_data; 264 uint8_t read_id_addr_len; 265 uint8_t wrt_disable_bits; 266 uint8_t read_dev_id_len; 267 uint8_t chip_erase_cmd; 268 uint16_t read_timeout; 269 uint8_t protect_sec_cmd; 270 uint8_t unused2[65]; 271}; 272 273/* Flash Layout Table */ 274 275struct qla_flt_location { 276 uint8_t sig[4]; 277 uint16_t start_lo; 278 uint16_t start_hi; 279 uint8_t version; 280 uint8_t unused[5]; 281 uint16_t checksum; 282}; 283 284struct qla_flt_header { 285 uint16_t version; 286 uint16_t length; 287 uint16_t checksum; 288 uint16_t unused; 289}; 290 291/* 82xx FLT Regions */ 292#define FLT_REG_FDT 0x1a 293#define FLT_REG_FLT 0x1c 294#define FLT_REG_BOOTLOAD_82 0x72 295#define FLT_REG_FW_82 0x74 296#define FLT_REG_GOLD_FW_82 0x75 297#define FLT_REG_BOOT_CODE_82 0x78 298 299struct qla_flt_region { 300 uint32_t code; 301 uint32_t size; 302 uint32_t start; 303 uint32_t end; 304}; 305 306/************************************************************************* 307 * 308 * Mailbox Commands Structures and Definitions 309 * 310 *************************************************************************/ 311 312/* Mailbox command definitions */ 313#define MBOX_CMD_ABOUT_FW 0x0009 314#define MBOX_CMD_PING 0x000B 315#define MBOX_CMD_ENABLE_INTRS 0x0010 316#define INTR_DISABLE 0 317#define INTR_ENABLE 1 318#define MBOX_CMD_STOP_FW 0x0014 319#define MBOX_CMD_ABORT_TASK 0x0015 320#define MBOX_CMD_LUN_RESET 0x0016 321#define MBOX_CMD_TARGET_WARM_RESET 0x0017 322#define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E 323#define MBOX_CMD_GET_FW_STATUS 0x001F 324#define MBOX_CMD_SET_ISNS_SERVICE 0x0021 325#define ISNS_DISABLE 0 326#define ISNS_ENABLE 1 327#define MBOX_CMD_COPY_FLASH 0x0024 328#define MBOX_CMD_WRITE_FLASH 0x0025 329#define MBOX_CMD_READ_FLASH 0x0026 330#define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031 331#define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056 332#define LOGOUT_OPTION_CLOSE_SESSION 0x01 333#define LOGOUT_OPTION_RELOGIN 0x02 334#define MBOX_CMD_EXECUTE_IOCB_A64 0x005A 335#define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060 336#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061 337#define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062 338#define MBOX_CMD_SET_DATABASE_ENTRY 0x0063 339#define MBOX_CMD_GET_DATABASE_ENTRY 0x0064 340#define DDB_DS_UNASSIGNED 0x00 341#define DDB_DS_NO_CONNECTION_ACTIVE 0x01 342#define DDB_DS_SESSION_ACTIVE 0x04 343#define DDB_DS_SESSION_FAILED 0x06 344#define DDB_DS_LOGIN_IN_PROCESS 0x07 345#define MBOX_CMD_GET_FW_STATE 0x0069 346#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A 347#define MBOX_CMD_GET_SYS_INFO 0x0078 348#define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087 349#define MBOX_CMD_SET_ACB 0x0088 350#define MBOX_CMD_GET_ACB 0x0089 351#define MBOX_CMD_DISABLE_ACB 0x008A 352#define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B 353#define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C 354#define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D 355#define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E 356#define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090 357#define MBOX_CMD_GET_IP_ADDR_STATE 0x0091 358#define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092 359#define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093 360 361/* Mailbox 1 */ 362#define FW_STATE_READY 0x0000 363#define FW_STATE_CONFIG_WAIT 0x0001 364#define FW_STATE_WAIT_AUTOCONNECT 0x0002 365#define FW_STATE_ERROR 0x0004 366#define FW_STATE_CONFIGURING_IP 0x0008 367 368/* Mailbox 3 */ 369#define FW_ADDSTATE_OPTICAL_MEDIA 0x0001 370#define FW_ADDSTATE_DHCPv4_ENABLED 0x0002 371#define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004 372#define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008 373#define FW_ADDSTATE_LINK_UP 0x0010 374#define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020 375#define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B 376#define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074 377#define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */ 378#define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077 379 380/* Mailbox status definitions */ 381#define MBOX_COMPLETION_STATUS 4 382#define MBOX_STS_BUSY 0x0007 383#define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000 384#define MBOX_STS_COMMAND_COMPLETE 0x4000 385#define MBOX_STS_COMMAND_ERROR 0x4005 386 387#define MBOX_ASYNC_EVENT_STATUS 8 388#define MBOX_ASTS_SYSTEM_ERROR 0x8002 389#define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003 390#define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004 391#define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005 392#define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006 393#define MBOX_ASTS_LINK_UP 0x8010 394#define MBOX_ASTS_LINK_DOWN 0x8011 395#define MBOX_ASTS_DATABASE_CHANGED 0x8014 396#define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015 397#define MBOX_ASTS_SELF_TEST_FAILED 0x8016 398#define MBOX_ASTS_LOGIN_FAILED 0x8017 399#define MBOX_ASTS_DNS 0x8018 400#define MBOX_ASTS_HEARTBEAT 0x8019 401#define MBOX_ASTS_NVRAM_INVALID 0x801A 402#define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B 403#define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C 404#define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D 405#define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F 406#define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021 407#define MBOX_ASTS_DUPLICATE_IP 0x8025 408#define MBOX_ASTS_ARP_COMPLETE 0x8026 409#define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 410#define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028 411#define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029 412#define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B 413#define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C 414#define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D 415#define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E 416 417#define ISNS_EVENT_DATA_RECEIVED 0x0000 418#define ISNS_EVENT_CONNECTION_OPENED 0x0001 419#define ISNS_EVENT_CONNECTION_FAILED 0x0002 420#define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022 421#define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 422 423/* ACB State Defines */ 424#define ACB_STATE_UNCONFIGURED 0x00 425#define ACB_STATE_INVALID 0x01 426#define ACB_STATE_ACQUIRING 0x02 427#define ACB_STATE_TENTATIVE 0x03 428#define ACB_STATE_DEPRICATED 0x04 429#define ACB_STATE_VALID 0x05 430#define ACB_STATE_DISABLING 0x06 431 432/*************************************************************************/ 433 434/* Host Adapter Initialization Control Block (from host) */ 435struct addr_ctrl_blk { 436 uint8_t version; /* 00 */ 437#define IFCB_VER_MIN 0x01 438#define IFCB_VER_MAX 0x02 439 uint8_t control; /* 01 */ 440 441 uint16_t fw_options; /* 02-03 */ 442#define FWOPT_HEARTBEAT_ENABLE 0x1000 443#define FWOPT_SESSION_MODE 0x0040 444#define FWOPT_INITIATOR_MODE 0x0020 445#define FWOPT_TARGET_MODE 0x0010 446 447 uint16_t exec_throttle; /* 04-05 */ 448 uint8_t zio_count; /* 06 */ 449 uint8_t res0; /* 07 */ 450 uint16_t eth_mtu_size; /* 08-09 */ 451 uint16_t add_fw_options; /* 0A-0B */ 452 453 uint8_t hb_interval; /* 0C */ 454 uint8_t inst_num; /* 0D */ 455 uint16_t res1; /* 0E-0F */ 456 uint16_t rqq_consumer_idx; /* 10-11 */ 457 uint16_t compq_producer_idx; /* 12-13 */ 458 uint16_t rqq_len; /* 14-15 */ 459 uint16_t compq_len; /* 16-17 */ 460 uint32_t rqq_addr_lo; /* 18-1B */ 461 uint32_t rqq_addr_hi; /* 1C-1F */ 462 uint32_t compq_addr_lo; /* 20-23 */ 463 uint32_t compq_addr_hi; /* 24-27 */ 464 uint32_t shdwreg_addr_lo; /* 28-2B */ 465 uint32_t shdwreg_addr_hi; /* 2C-2F */ 466 467 uint16_t iscsi_opts; /* 30-31 */ 468 uint16_t ipv4_tcp_opts; /* 32-33 */ 469 uint16_t ipv4_ip_opts; /* 34-35 */ 470#define IPOPT_IPv4_PROTOCOL_ENABLE 0x8000 471 472 uint16_t iscsi_max_pdu_size; /* 36-37 */ 473 uint8_t ipv4_tos; /* 38 */ 474 uint8_t ipv4_ttl; /* 39 */ 475 uint8_t acb_version; /* 3A */ 476#define ACB_NOT_SUPPORTED 0x00 477#define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2 478 Features */ 479 480 uint8_t res2; /* 3B */ 481 uint16_t def_timeout; /* 3C-3D */ 482 uint16_t iscsi_fburst_len; /* 3E-3F */ 483 uint16_t iscsi_def_time2wait; /* 40-41 */ 484 uint16_t iscsi_def_time2retain; /* 42-43 */ 485 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ 486 uint16_t conn_ka_timeout; /* 46-47 */ 487 uint16_t ipv4_port; /* 48-49 */ 488 uint16_t iscsi_max_burst_len; /* 4A-4B */ 489 uint32_t res5; /* 4C-4F */ 490 uint8_t ipv4_addr[4]; /* 50-53 */ 491 uint16_t ipv4_vlan_tag; /* 54-55 */ 492 uint8_t ipv4_addr_state; /* 56 */ 493 uint8_t ipv4_cacheid; /* 57 */ 494 uint8_t res6[8]; /* 58-5F */ 495 uint8_t ipv4_subnet[4]; /* 60-63 */ 496 uint8_t res7[12]; /* 64-6F */ 497 uint8_t ipv4_gw_addr[4]; /* 70-73 */ 498 uint8_t res8[0xc]; /* 74-7F */ 499 uint8_t pri_dns_srvr_ip[4];/* 80-83 */ 500 uint8_t sec_dns_srvr_ip[4];/* 84-87 */ 501 uint16_t min_eph_port; /* 88-89 */ 502 uint16_t max_eph_port; /* 8A-8B */ 503 uint8_t res9[4]; /* 8C-8F */ 504 uint8_t iscsi_alias[32];/* 90-AF */ 505 uint8_t res9_1[0x16]; /* B0-C5 */ 506 uint16_t tgt_portal_grp;/* C6-C7 */ 507 uint8_t abort_timer; /* C8 */ 508 uint8_t ipv4_tcp_wsf; /* C9 */ 509 uint8_t res10[6]; /* CA-CF */ 510 uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */ 511 uint8_t ipv4_dhcp_vid_len; /* D4 */ 512 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ 513 uint8_t res11[20]; /* E0-F3 */ 514 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ 515 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ 516 uint8_t iscsi_name[224]; /* 100-1DF */ 517 uint8_t res12[32]; /* 1E0-1FF */ 518 uint32_t cookie; /* 200-203 */ 519 uint16_t ipv6_port; /* 204-205 */ 520 uint16_t ipv6_opts; /* 206-207 */ 521#define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000 522 523 uint16_t ipv6_addtl_opts; /* 208-209 */ 524#define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB 525 Only */ 526#define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001 527 528 uint16_t ipv6_tcp_opts; /* 20A-20B */ 529 uint8_t ipv6_tcp_wsf; /* 20C */ 530 uint16_t ipv6_flow_lbl; /* 20D-20F */ 531 uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ 532 uint16_t ipv6_vlan_tag; /* 220-221 */ 533 uint8_t ipv6_lnk_lcl_addr_state;/* 222 */ 534 uint8_t ipv6_addr0_state; /* 223 */ 535 uint8_t ipv6_addr1_state; /* 224 */ 536#define IP_ADDRSTATE_UNCONFIGURED 0 537#define IP_ADDRSTATE_INVALID 1 538#define IP_ADDRSTATE_ACQUIRING 2 539#define IP_ADDRSTATE_TENTATIVE 3 540#define IP_ADDRSTATE_DEPRICATED 4 541#define IP_ADDRSTATE_PREFERRED 5 542#define IP_ADDRSTATE_DISABLING 6 543 544 uint8_t ipv6_dflt_rtr_state; /* 225 */ 545#define IPV6_RTRSTATE_UNKNOWN 0 546#define IPV6_RTRSTATE_MANUAL 1 547#define IPV6_RTRSTATE_ADVERTISED 3 548#define IPV6_RTRSTATE_STALE 4 549 550 uint8_t ipv6_traffic_class; /* 226 */ 551 uint8_t ipv6_hop_limit; /* 227 */ 552 uint8_t ipv6_if_id[8]; /* 228-22F */ 553 uint8_t ipv6_addr0[16]; /* 230-23F */ 554 uint8_t ipv6_addr1[16]; /* 240-24F */ 555 uint32_t ipv6_nd_reach_time; /* 250-253 */ 556 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ 557 uint32_t ipv6_nd_stale_timeout; /* 258-25B */ 558 uint8_t ipv6_dup_addr_detect_count; /* 25C */ 559 uint8_t ipv6_cache_id; /* 25D */ 560 uint8_t res13[18]; /* 25E-26F */ 561 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ 562 uint8_t res14[140]; /* 274-2FF */ 563}; 564 565struct init_fw_ctrl_blk { 566 struct addr_ctrl_blk pri; 567/* struct addr_ctrl_blk sec;*/ 568}; 569 570/*************************************************************************/ 571 572struct dev_db_entry { 573 uint16_t options; /* 00-01 */ 574#define DDB_OPT_DISC_SESSION 0x10 575#define DDB_OPT_TARGET 0x02 /* device is a target */ 576#define DDB_OPT_IPV6_DEVICE 0x100 577#define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */ 578#define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */ 579 580 uint16_t exec_throttle; /* 02-03 */ 581 uint16_t exec_count; /* 04-05 */ 582 uint16_t res0; /* 06-07 */ 583 uint16_t iscsi_options; /* 08-09 */ 584 uint16_t tcp_options; /* 0A-0B */ 585 uint16_t ip_options; /* 0C-0D */ 586 uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */ 587 uint32_t res1; /* 10-13 */ 588 uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */ 589 uint16_t iscsi_first_burst_len; /* 16-17 */ 590 uint16_t iscsi_def_time2wait; /* 18-19 */ 591 uint16_t iscsi_def_time2retain; /* 1A-1B */ 592 uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */ 593 uint16_t ka_timeout; /* 1E-1F */ 594 uint8_t isid[6]; /* 20-25 big-endian, must be converted 595 * to little-endian */ 596 uint16_t tsid; /* 26-27 */ 597 uint16_t port; /* 28-29 */ 598 uint16_t iscsi_max_burst_len; /* 2A-2B */ 599 uint16_t def_timeout; /* 2C-2D */ 600 uint16_t res2; /* 2E-2F */ 601 uint8_t ip_addr[0x10]; /* 30-3F */ 602 uint8_t iscsi_alias[0x20]; /* 40-5F */ 603 uint8_t tgt_addr[0x20]; /* 60-7F */ 604 uint16_t mss; /* 80-81 */ 605 uint16_t res3; /* 82-83 */ 606 uint16_t lcl_port; /* 84-85 */ 607 uint8_t ipv4_tos; /* 86 */ 608 uint16_t ipv6_flow_lbl; /* 87-89 */ 609 uint8_t res4[0x36]; /* 8A-BF */ 610 uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a 611 * pointer to a string so we 612 * don't have to reserve soooo 613 * much RAM */ 614 uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */ 615 uint8_t res5[0x10]; /* 1B0-1BF */ 616 uint16_t ddb_link; /* 1C0-1C1 */ 617 uint16_t chap_tbl_idx; /* 1C2-1C3 */ 618 uint16_t tgt_portal_grp; /* 1C4-1C5 */ 619 uint8_t tcp_xmt_wsf; /* 1C6 */ 620 uint8_t tcp_rcv_wsf; /* 1C7 */ 621 uint32_t stat_sn; /* 1C8-1CB */ 622 uint32_t exp_stat_sn; /* 1CC-1CF */ 623 uint8_t res6[0x30]; /* 1D0-1FF */ 624}; 625 626/*************************************************************************/ 627 628/* Flash definitions */ 629 630#define FLASH_OFFSET_SYS_INFO 0x02000000 631#define FLASH_DEFAULTBLOCKSIZE 0x20000 632#define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes 633 * for EOF 634 * signature */ 635 636struct sys_info_phys_addr { 637 uint8_t address[6]; /* 00-05 */ 638 uint8_t filler[2]; /* 06-07 */ 639}; 640 641struct flash_sys_info { 642 uint32_t cookie; /* 00-03 */ 643 uint32_t physAddrCount; /* 04-07 */ 644 struct sys_info_phys_addr physAddr[4]; /* 08-27 */ 645 uint8_t vendorId[128]; /* 28-A7 */ 646 uint8_t productId[128]; /* A8-127 */ 647 uint32_t serialNumber; /* 128-12B */ 648 649 /* PCI Configuration values */ 650 uint32_t pciDeviceVendor; /* 12C-12F */ 651 uint32_t pciDeviceId; /* 130-133 */ 652 uint32_t pciSubsysVendor; /* 134-137 */ 653 uint32_t pciSubsysId; /* 138-13B */ 654 655 /* This validates version 1. */ 656 uint32_t crumbs; /* 13C-13F */ 657 658 uint32_t enterpriseNumber; /* 140-143 */ 659 660 uint32_t mtu; /* 144-147 */ 661 uint32_t reserved0; /* 148-14b */ 662 uint32_t crumbs2; /* 14c-14f */ 663 uint8_t acSerialNumber[16]; /* 150-15f */ 664 uint32_t crumbs3; /* 160-16f */ 665 666 /* Leave this last in the struct so it is declared invalid if 667 * any new items are added. 668 */ 669 uint32_t reserved1[39]; /* 170-1ff */ 670}; /* 200 */ 671 672struct mbx_sys_info { 673 uint8_t board_id_str[16]; /* 0-f Keep board ID string first */ 674 /* in this structure for GUI. */ 675 uint16_t board_id; /* 10-11 board ID code */ 676 uint16_t phys_port_cnt; /* 12-13 number of physical network ports */ 677 uint16_t port_num; /* 14-15 network port for this PCI function */ 678 /* (port 0 is first port) */ 679 uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */ 680 uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */ 681 uint32_t pci_func; /* 20-23 this PCI function */ 682 unsigned char serial_number[16]; /* 24-33 serial number string */ 683 uint8_t reserved[12]; /* 34-3f */ 684}; 685 686struct crash_record { 687 uint16_t fw_major_version; /* 00 - 01 */ 688 uint16_t fw_minor_version; /* 02 - 03 */ 689 uint16_t fw_patch_version; /* 04 - 05 */ 690 uint16_t fw_build_version; /* 06 - 07 */ 691 692 uint8_t build_date[16]; /* 08 - 17 */ 693 uint8_t build_time[16]; /* 18 - 27 */ 694 uint8_t build_user[16]; /* 28 - 37 */ 695 uint8_t card_serial_num[16]; /* 38 - 47 */ 696 697 uint32_t time_of_crash_in_secs; /* 48 - 4B */ 698 uint32_t time_of_crash_in_ms; /* 4C - 4F */ 699 700 uint16_t out_RISC_sd_num_frames; /* 50 - 51 */ 701 uint16_t OAP_sd_num_words; /* 52 - 53 */ 702 uint16_t IAP_sd_num_frames; /* 54 - 55 */ 703 uint16_t in_RISC_sd_num_words; /* 56 - 57 */ 704 705 uint8_t reserved1[28]; /* 58 - 7F */ 706 707 uint8_t out_RISC_reg_dump[256]; /* 80 -17F */ 708 uint8_t in_RISC_reg_dump[256]; /*180 -27F */ 709 uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */ 710}; 711 712struct conn_event_log_entry { 713#define MAX_CONN_EVENT_LOG_ENTRIES 100 714 uint32_t timestamp_sec; /* 00 - 03 seconds since boot */ 715 uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */ 716 uint16_t device_index; /* 08 - 09 */ 717 uint16_t fw_conn_state; /* 0A - 0B */ 718 uint8_t event_type; /* 0C - 0C */ 719 uint8_t error_code; /* 0D - 0D */ 720 uint16_t error_code_detail; /* 0E - 0F */ 721 uint8_t num_consecutive_events; /* 10 - 10 */ 722 uint8_t rsvd[3]; /* 11 - 13 */ 723}; 724 725/************************************************************************* 726 * 727 * IOCB Commands Structures and Definitions 728 * 729 *************************************************************************/ 730#define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */ 731#define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */ 732#define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */ 733 734/* IOCB header structure */ 735struct qla4_header { 736 uint8_t entryType; 737#define ET_STATUS 0x03 738#define ET_MARKER 0x04 739#define ET_CONT_T1 0x0A 740#define ET_STATUS_CONTINUATION 0x10 741#define ET_CMND_T3 0x19 742#define ET_PASSTHRU0 0x3A 743#define ET_PASSTHRU_STATUS 0x3C 744 745 uint8_t entryStatus; 746 uint8_t systemDefined; 747 uint8_t entryCount; 748 749 /* SyetemDefined definition */ 750}; 751 752/* Generic queue entry structure*/ 753struct queue_entry { 754 uint8_t data[60]; 755 uint32_t signature; 756 757}; 758 759/* 64 bit addressing segment counts*/ 760 761#define COMMAND_SEG_A64 1 762#define CONTINUE_SEG_A64 5 763 764/* 64 bit addressing segment definition*/ 765 766struct data_seg_a64 { 767 struct { 768 uint32_t addrLow; 769 uint32_t addrHigh; 770 771 } base; 772 773 uint32_t count; 774 775}; 776 777/* Command Type 3 entry structure*/ 778 779struct command_t3_entry { 780 struct qla4_header hdr; /* 00-03 */ 781 782 uint32_t handle; /* 04-07 */ 783 uint16_t target; /* 08-09 */ 784 uint16_t connection_id; /* 0A-0B */ 785 786 uint8_t control_flags; /* 0C */ 787 788 /* data direction (bits 5-6) */ 789#define CF_WRITE 0x20 790#define CF_READ 0x40 791#define CF_NO_DATA 0x00 792 793 /* task attributes (bits 2-0) */ 794#define CF_HEAD_TAG 0x03 795#define CF_ORDERED_TAG 0x02 796#define CF_SIMPLE_TAG 0x01 797 798 /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS 799 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS 800 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET 801 * PROPERLY. 802 */ 803 uint8_t state_flags; /* 0D */ 804 uint8_t cmdRefNum; /* 0E */ 805 uint8_t reserved1; /* 0F */ 806 uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */ 807 struct scsi_lun lun; /* FCP LUN (BE). */ 808 uint32_t cmdSeqNum; /* 28-2B */ 809 uint16_t timeout; /* 2C-2D */ 810 uint16_t dataSegCnt; /* 2E-2F */ 811 uint32_t ttlByteCnt; /* 30-33 */ 812 struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */ 813 814}; 815 816 817/* Continuation Type 1 entry structure*/ 818struct continuation_t1_entry { 819 struct qla4_header hdr; 820 821 struct data_seg_a64 dataseg[CONTINUE_SEG_A64]; 822 823}; 824 825/* Parameterize for 64 or 32 bits */ 826#define COMMAND_SEG COMMAND_SEG_A64 827#define CONTINUE_SEG CONTINUE_SEG_A64 828 829#define ET_COMMAND ET_CMND_T3 830#define ET_CONTINUE ET_CONT_T1 831 832/* Marker entry structure*/ 833struct qla4_marker_entry { 834 struct qla4_header hdr; /* 00-03 */ 835 836 uint32_t system_defined; /* 04-07 */ 837 uint16_t target; /* 08-09 */ 838 uint16_t modifier; /* 0A-0B */ 839#define MM_LUN_RESET 0 840#define MM_TGT_WARM_RESET 1 841 842 uint16_t flags; /* 0C-0D */ 843 uint16_t reserved1; /* 0E-0F */ 844 struct scsi_lun lun; /* FCP LUN (BE). */ 845 uint64_t reserved2; /* 18-1F */ 846 uint64_t reserved3; /* 20-27 */ 847 uint64_t reserved4; /* 28-2F */ 848 uint64_t reserved5; /* 30-37 */ 849 uint64_t reserved6; /* 38-3F */ 850}; 851 852/* Status entry structure*/ 853struct status_entry { 854 struct qla4_header hdr; /* 00-03 */ 855 856 uint32_t handle; /* 04-07 */ 857 858 uint8_t scsiStatus; /* 08 */ 859#define SCSI_CHECK_CONDITION 0x02 860 861 uint8_t iscsiFlags; /* 09 */ 862#define ISCSI_FLAG_RESIDUAL_UNDER 0x02 863#define ISCSI_FLAG_RESIDUAL_OVER 0x04 864 865 uint8_t iscsiResponse; /* 0A */ 866 867 uint8_t completionStatus; /* 0B */ 868#define SCS_COMPLETE 0x00 869#define SCS_INCOMPLETE 0x01 870#define SCS_RESET_OCCURRED 0x04 871#define SCS_ABORTED 0x05 872#define SCS_TIMEOUT 0x06 873#define SCS_DATA_OVERRUN 0x07 874#define SCS_DATA_UNDERRUN 0x15 875#define SCS_QUEUE_FULL 0x1C 876#define SCS_DEVICE_UNAVAILABLE 0x28 877#define SCS_DEVICE_LOGGED_OUT 0x29 878 879 uint8_t reserved1; /* 0C */ 880 881 /* state_flags MUST be at the same location as state_flags in 882 * the Command_T3/4_Entry */ 883 uint8_t state_flags; /* 0D */ 884 885 uint16_t senseDataByteCnt; /* 0E-0F */ 886 uint32_t residualByteCnt; /* 10-13 */ 887 uint32_t bidiResidualByteCnt; /* 14-17 */ 888 uint32_t expSeqNum; /* 18-1B */ 889 uint32_t maxCmdSeqNum; /* 1C-1F */ 890 uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */ 891 892}; 893 894/* Status Continuation entry */ 895struct status_cont_entry { 896 struct qla4_header hdr; /* 00-03 */ 897 uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */ 898}; 899 900struct passthru0 { 901 struct qla4_header hdr; /* 00-03 */ 902 uint32_t handle; /* 04-07 */ 903 uint16_t target; /* 08-09 */ 904 uint16_t connectionID; /* 0A-0B */ 905#define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000) 906 907 uint16_t controlFlags; /* 0C-0D */ 908#define PT_FLAG_ETHERNET_FRAME 0x8000 909#define PT_FLAG_ISNS_PDU 0x8000 910#define PT_FLAG_SEND_BUFFER 0x0200 911#define PT_FLAG_WAIT_4_RESPONSE 0x0100 912 913 uint16_t timeout; /* 0E-0F */ 914#define PT_DEFAULT_TIMEOUT 30 /* seconds */ 915 916 struct data_seg_a64 outDataSeg64; /* 10-1B */ 917 uint32_t res1; /* 1C-1F */ 918 struct data_seg_a64 inDataSeg64; /* 20-2B */ 919 uint8_t res2[20]; /* 2C-3F */ 920}; 921 922struct passthru_status { 923 struct qla4_header hdr; /* 00-03 */ 924 uint32_t handle; /* 04-07 */ 925 uint16_t target; /* 08-09 */ 926 uint16_t connectionID; /* 0A-0B */ 927 928 uint8_t completionStatus; /* 0C */ 929#define PASSTHRU_STATUS_COMPLETE 0x01 930 931 uint8_t residualFlags; /* 0D */ 932 933 uint16_t timeout; /* 0E-0F */ 934 uint16_t portNumber; /* 10-11 */ 935 uint8_t res1[10]; /* 12-1B */ 936 uint32_t outResidual; /* 1C-1F */ 937 uint8_t res2[12]; /* 20-2B */ 938 uint32_t inResidual; /* 2C-2F */ 939 uint8_t res4[16]; /* 30-3F */ 940}; 941 942/* 943 * ISP queue - response queue entry definition. 944 */ 945struct response { 946 uint8_t data[60]; 947 uint32_t signature; 948#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 949}; 950 951#endif /* _QLA4X_FW_H */ 952