1/* 2 * Blackfin On-Chip Real Time Clock Driver 3 * Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x 4 * 5 * Copyright 2004-2009 Analog Devices Inc. 6 * 7 * Enter bugs at http://blackfin.uclinux.org/ 8 * 9 * Licensed under the GPL-2 or later. 10 */ 11 12/* The biggest issue we deal with in this driver is that register writes are 13 * synced to the RTC frequency of 1Hz. So if you write to a register and 14 * attempt to write again before the first write has completed, the new write 15 * is simply discarded. This can easily be troublesome if userspace disables 16 * one event (say periodic) and then right after enables an event (say alarm). 17 * Since all events are maintained in the same interrupt mask register, if 18 * we wrote to it to disable the first event and then wrote to it again to 19 * enable the second event, that second event would not be enabled as the 20 * write would be discarded and things quickly fall apart. 21 * 22 * To keep this delay from significantly degrading performance (we, in theory, 23 * would have to sleep for up to 1 second everytime we wanted to write a 24 * register), we only check the write pending status before we start to issue 25 * a new write. We bank on the idea that it doesnt matter when the sync 26 * happens so long as we don't attempt another write before it does. The only 27 * time userspace would take this penalty is when they try and do multiple 28 * operations right after another ... but in this case, they need to take the 29 * sync penalty, so we should be OK. 30 * 31 * Also note that the RTC_ISTAT register does not suffer this penalty; its 32 * writes to clear status registers complete immediately. 33 */ 34 35/* It may seem odd that there is no SWCNT code in here (which would be exposed 36 * via the periodic interrupt event, or PIE). Since the Blackfin RTC peripheral 37 * runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ 38 * (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs. 39 * The same exact behavior can be accomplished by using the update interrupt 40 * event (UIE). Maybe down the line the RTC peripheral will suck less in which 41 * case we can re-introduce PIE support. 42 */ 43 44#include <linux/bcd.h> 45#include <linux/completion.h> 46#include <linux/delay.h> 47#include <linux/init.h> 48#include <linux/interrupt.h> 49#include <linux/kernel.h> 50#include <linux/module.h> 51#include <linux/platform_device.h> 52#include <linux/rtc.h> 53#include <linux/seq_file.h> 54#include <linux/slab.h> 55 56#include <asm/blackfin.h> 57 58#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__) 59 60struct bfin_rtc { 61 struct rtc_device *rtc_dev; 62 struct rtc_time rtc_alarm; 63 u16 rtc_wrote_regs; 64}; 65 66/* Bit values for the ISTAT / ICTL registers */ 67#define RTC_ISTAT_WRITE_COMPLETE 0x8000 68#define RTC_ISTAT_WRITE_PENDING 0x4000 69#define RTC_ISTAT_ALARM_DAY 0x0040 70#define RTC_ISTAT_24HR 0x0020 71#define RTC_ISTAT_HOUR 0x0010 72#define RTC_ISTAT_MIN 0x0008 73#define RTC_ISTAT_SEC 0x0004 74#define RTC_ISTAT_ALARM 0x0002 75#define RTC_ISTAT_STOPWATCH 0x0001 76 77/* Shift values for RTC_STAT register */ 78#define DAY_BITS_OFF 17 79#define HOUR_BITS_OFF 12 80#define MIN_BITS_OFF 6 81#define SEC_BITS_OFF 0 82 83/* Some helper functions to convert between the common RTC notion of time 84 * and the internal Blackfin notion that is encoded in 32bits. 85 */ 86static inline u32 rtc_time_to_bfin(unsigned long now) 87{ 88 u32 sec = (now % 60); 89 u32 min = (now % (60 * 60)) / 60; 90 u32 hour = (now % (60 * 60 * 24)) / (60 * 60); 91 u32 days = (now / (60 * 60 * 24)); 92 return (sec << SEC_BITS_OFF) + 93 (min << MIN_BITS_OFF) + 94 (hour << HOUR_BITS_OFF) + 95 (days << DAY_BITS_OFF); 96} 97static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin) 98{ 99 return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) + 100 (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) + 101 (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) + 102 (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24); 103} 104static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm) 105{ 106 rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm); 107} 108 109/** 110 * bfin_rtc_sync_pending - make sure pending writes have complete 111 * 112 * Wait for the previous write to a RTC register to complete. 113 * Unfortunately, we can't sleep here as that introduces a race condition when 114 * turning on interrupt events. Consider this: 115 * - process sets alarm 116 * - process enables alarm 117 * - process sleeps while waiting for rtc write to sync 118 * - interrupt fires while process is sleeping 119 * - interrupt acks the event by writing to ISTAT 120 * - interrupt sets the WRITE PENDING bit 121 * - interrupt handler finishes 122 * - process wakes up, sees WRITE PENDING bit set, goes to sleep 123 * - interrupt fires while process is sleeping 124 * If anyone can point out the obvious solution here, i'm listening :). This 125 * shouldn't be an issue on an SMP or preempt system as this function should 126 * only be called with the rtc lock held. 127 * 128 * Other options: 129 * - disable PREN so the sync happens at 32.768kHZ ... but this changes the 130 * inc rate for all RTC registers from 1HZ to 32.768kHZ ... 131 * - use the write complete IRQ 132 */ 133/* 134static void bfin_rtc_sync_pending_polled(void) 135{ 136 while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE)) 137 if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)) 138 break; 139 bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE); 140} 141*/ 142static DECLARE_COMPLETION(bfin_write_complete); 143static void bfin_rtc_sync_pending(struct device *dev) 144{ 145 dev_dbg_stamp(dev); 146 while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING) 147 wait_for_completion_timeout(&bfin_write_complete, HZ * 5); 148 dev_dbg_stamp(dev); 149} 150 151/** 152 * bfin_rtc_reset - set RTC to sane/known state 153 * 154 * Initialize the RTC. Enable pre-scaler to scale RTC clock 155 * to 1Hz and clear interrupt/status registers. 156 */ 157static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl) 158{ 159 struct bfin_rtc *rtc = dev_get_drvdata(dev); 160 dev_dbg_stamp(dev); 161 bfin_rtc_sync_pending(dev); 162 bfin_write_RTC_PREN(0x1); 163 bfin_write_RTC_ICTL(rtc_ictl); 164 bfin_write_RTC_ALARM(0); 165 bfin_write_RTC_ISTAT(0xFFFF); 166 rtc->rtc_wrote_regs = 0; 167} 168 169/** 170 * bfin_rtc_interrupt - handle interrupt from RTC 171 * 172 * Since we handle all RTC events here, we have to make sure the requested 173 * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT) 174 * always gets updated regardless of the interrupt being enabled. So when one 175 * even we care about (e.g. stopwatch) goes off, we don't want to turn around 176 * and say that other events have happened as well (e.g. second). We do not 177 * have to worry about pending writes to the RTC_ICTL register as interrupts 178 * only fire if they are enabled in the RTC_ICTL register. 179 */ 180static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id) 181{ 182 struct device *dev = dev_id; 183 struct bfin_rtc *rtc = dev_get_drvdata(dev); 184 unsigned long events = 0; 185 bool write_complete = false; 186 u16 rtc_istat, rtc_ictl; 187 188 dev_dbg_stamp(dev); 189 190 rtc_istat = bfin_read_RTC_ISTAT(); 191 rtc_ictl = bfin_read_RTC_ICTL(); 192 193 if (rtc_istat & RTC_ISTAT_WRITE_COMPLETE) { 194 bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE); 195 write_complete = true; 196 complete(&bfin_write_complete); 197 } 198 199 if (rtc_ictl & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) { 200 if (rtc_istat & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) { 201 bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY); 202 events |= RTC_AF | RTC_IRQF; 203 } 204 } 205 206 if (rtc_ictl & RTC_ISTAT_SEC) { 207 if (rtc_istat & RTC_ISTAT_SEC) { 208 bfin_write_RTC_ISTAT(RTC_ISTAT_SEC); 209 events |= RTC_UF | RTC_IRQF; 210 } 211 } 212 213 if (events) 214 rtc_update_irq(rtc->rtc_dev, 1, events); 215 216 if (write_complete || events) 217 return IRQ_HANDLED; 218 else 219 return IRQ_NONE; 220} 221 222static void bfin_rtc_int_set(u16 rtc_int) 223{ 224 bfin_write_RTC_ISTAT(rtc_int); 225 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int); 226} 227static void bfin_rtc_int_clear(u16 rtc_int) 228{ 229 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int); 230} 231static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc) 232{ 233 /* Blackfin has different bits for whether the alarm is 234 * more than 24 hours away. 235 */ 236 bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY); 237} 238static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) 239{ 240 struct bfin_rtc *rtc = dev_get_drvdata(dev); 241 int ret = 0; 242 243 dev_dbg_stamp(dev); 244 245 bfin_rtc_sync_pending(dev); 246 247 switch (cmd) { 248 case RTC_UIE_ON: 249 dev_dbg_stamp(dev); 250 bfin_rtc_int_set(RTC_ISTAT_SEC); 251 break; 252 case RTC_UIE_OFF: 253 dev_dbg_stamp(dev); 254 bfin_rtc_int_clear(~RTC_ISTAT_SEC); 255 break; 256 257 case RTC_AIE_ON: 258 dev_dbg_stamp(dev); 259 bfin_rtc_int_set_alarm(rtc); 260 break; 261 case RTC_AIE_OFF: 262 dev_dbg_stamp(dev); 263 bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)); 264 break; 265 266 default: 267 dev_dbg_stamp(dev); 268 ret = -ENOIOCTLCMD; 269 } 270 271 return ret; 272} 273 274static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm) 275{ 276 struct bfin_rtc *rtc = dev_get_drvdata(dev); 277 278 dev_dbg_stamp(dev); 279 280 if (rtc->rtc_wrote_regs & 0x1) 281 bfin_rtc_sync_pending(dev); 282 283 rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm); 284 285 return 0; 286} 287 288static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm) 289{ 290 struct bfin_rtc *rtc = dev_get_drvdata(dev); 291 int ret; 292 unsigned long now; 293 294 dev_dbg_stamp(dev); 295 296 ret = rtc_tm_to_time(tm, &now); 297 if (ret == 0) { 298 if (rtc->rtc_wrote_regs & 0x1) 299 bfin_rtc_sync_pending(dev); 300 bfin_write_RTC_STAT(rtc_time_to_bfin(now)); 301 rtc->rtc_wrote_regs = 0x1; 302 } 303 304 return ret; 305} 306 307static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 308{ 309 struct bfin_rtc *rtc = dev_get_drvdata(dev); 310 dev_dbg_stamp(dev); 311 alrm->time = rtc->rtc_alarm; 312 bfin_rtc_sync_pending(dev); 313 alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)); 314 return 0; 315} 316 317static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 318{ 319 struct bfin_rtc *rtc = dev_get_drvdata(dev); 320 unsigned long rtc_alarm; 321 322 dev_dbg_stamp(dev); 323 324 if (rtc_tm_to_time(&alrm->time, &rtc_alarm)) 325 return -EINVAL; 326 327 rtc->rtc_alarm = alrm->time; 328 329 bfin_rtc_sync_pending(dev); 330 bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm)); 331 if (alrm->enabled) 332 bfin_rtc_int_set_alarm(rtc); 333 334 return 0; 335} 336 337static int bfin_rtc_proc(struct device *dev, struct seq_file *seq) 338{ 339#define yesno(x) ((x) ? "yes" : "no") 340 u16 ictl = bfin_read_RTC_ICTL(); 341 dev_dbg_stamp(dev); 342 seq_printf(seq, 343 "alarm_IRQ\t: %s\n" 344 "wkalarm_IRQ\t: %s\n" 345 "seconds_IRQ\t: %s\n", 346 yesno(ictl & RTC_ISTAT_ALARM), 347 yesno(ictl & RTC_ISTAT_ALARM_DAY), 348 yesno(ictl & RTC_ISTAT_SEC)); 349 return 0; 350#undef yesno 351} 352 353static struct rtc_class_ops bfin_rtc_ops = { 354 .ioctl = bfin_rtc_ioctl, 355 .read_time = bfin_rtc_read_time, 356 .set_time = bfin_rtc_set_time, 357 .read_alarm = bfin_rtc_read_alarm, 358 .set_alarm = bfin_rtc_set_alarm, 359 .proc = bfin_rtc_proc, 360}; 361 362static int __devinit bfin_rtc_probe(struct platform_device *pdev) 363{ 364 struct bfin_rtc *rtc; 365 struct device *dev = &pdev->dev; 366 int ret = 0; 367 unsigned long timeout = jiffies + HZ; 368 369 dev_dbg_stamp(dev); 370 371 /* Allocate memory for our RTC struct */ 372 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); 373 if (unlikely(!rtc)) 374 return -ENOMEM; 375 platform_set_drvdata(pdev, rtc); 376 device_init_wakeup(dev, 1); 377 378 /* Register our RTC with the RTC framework */ 379 rtc->rtc_dev = rtc_device_register(pdev->name, dev, &bfin_rtc_ops, 380 THIS_MODULE); 381 if (unlikely(IS_ERR(rtc->rtc_dev))) { 382 ret = PTR_ERR(rtc->rtc_dev); 383 goto err; 384 } 385 386 /* Grab the IRQ and init the hardware */ 387 ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, 0, pdev->name, dev); 388 if (unlikely(ret)) 389 goto err_reg; 390 /* sometimes the bootloader touched things, but the write complete was not 391 * enabled, so let's just do a quick timeout here since the IRQ will not fire ... 392 */ 393 while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING) 394 if (time_after(jiffies, timeout)) 395 break; 396 bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE); 397 bfin_write_RTC_SWCNT(0); 398 399 return 0; 400 401err_reg: 402 rtc_device_unregister(rtc->rtc_dev); 403err: 404 kfree(rtc); 405 return ret; 406} 407 408static int __devexit bfin_rtc_remove(struct platform_device *pdev) 409{ 410 struct bfin_rtc *rtc = platform_get_drvdata(pdev); 411 struct device *dev = &pdev->dev; 412 413 bfin_rtc_reset(dev, 0); 414 free_irq(IRQ_RTC, dev); 415 rtc_device_unregister(rtc->rtc_dev); 416 platform_set_drvdata(pdev, NULL); 417 kfree(rtc); 418 419 return 0; 420} 421 422#ifdef CONFIG_PM 423static int bfin_rtc_suspend(struct platform_device *pdev, pm_message_t state) 424{ 425 if (device_may_wakeup(&pdev->dev)) { 426 enable_irq_wake(IRQ_RTC); 427 bfin_rtc_sync_pending(&pdev->dev); 428 } else 429 bfin_rtc_int_clear(0); 430 431 return 0; 432} 433 434static int bfin_rtc_resume(struct platform_device *pdev) 435{ 436 if (device_may_wakeup(&pdev->dev)) 437 disable_irq_wake(IRQ_RTC); 438 439 /* 440 * Since only some of the RTC bits are maintained externally in the 441 * Vbat domain, we need to wait for the RTC MMRs to be synced into 442 * the core after waking up. This happens every RTC 1HZ. Once that 443 * has happened, we can go ahead and re-enable the important write 444 * complete interrupt event. 445 */ 446 while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC)) 447 continue; 448 bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE); 449 450 return 0; 451} 452#else 453# define bfin_rtc_suspend NULL 454# define bfin_rtc_resume NULL 455#endif 456 457static struct platform_driver bfin_rtc_driver = { 458 .driver = { 459 .name = "rtc-bfin", 460 .owner = THIS_MODULE, 461 }, 462 .probe = bfin_rtc_probe, 463 .remove = __devexit_p(bfin_rtc_remove), 464 .suspend = bfin_rtc_suspend, 465 .resume = bfin_rtc_resume, 466}; 467 468static int __init bfin_rtc_init(void) 469{ 470 return platform_driver_register(&bfin_rtc_driver); 471} 472 473static void __exit bfin_rtc_exit(void) 474{ 475 platform_driver_unregister(&bfin_rtc_driver); 476} 477 478module_init(bfin_rtc_init); 479module_exit(bfin_rtc_exit); 480 481MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver"); 482MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>"); 483MODULE_LICENSE("GPL"); 484MODULE_ALIAS("platform:rtc-bfin"); 485