1 2 3#include <linux/delay.h> 4#include <linux/types.h> 5#include <linux/kernel.h> 6#include <linux/spinlock.h> 7#include <linux/init.h> /* for __init and __devinit */ 8#include <linux/pci.h> 9#include <linux/ioport.h> 10#include <linux/slab.h> 11 12#include <asm/byteorder.h> 13#include <asm/pdc.h> 14#include <asm/pdcpat.h> 15#include <asm/page.h> 16#include <asm/system.h> 17 18#include <asm/ropes.h> 19#include <asm/hardware.h> /* for register_parisc_driver() stuff */ 20#include <asm/parisc-device.h> 21#include <asm/io.h> /* read/write stuff */ 22 23#undef DEBUG_LBA /* general stuff */ 24#undef DEBUG_LBA_PORT /* debug I/O Port access */ 25#undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */ 26#undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */ 27 28#undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */ 29 30 31#ifdef DEBUG_LBA 32#define DBG(x...) printk(x) 33#else 34#define DBG(x...) 35#endif 36 37#ifdef DEBUG_LBA_PORT 38#define DBG_PORT(x...) printk(x) 39#else 40#define DBG_PORT(x...) 41#endif 42 43#ifdef DEBUG_LBA_CFG 44#define DBG_CFG(x...) printk(x) 45#else 46#define DBG_CFG(x...) 47#endif 48 49#ifdef DEBUG_LBA_PAT 50#define DBG_PAT(x...) printk(x) 51#else 52#define DBG_PAT(x...) 53#endif 54 55 56/* 57** Config accessor functions only pass in the 8-bit bus number and not 58** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus 59** number based on what firmware wrote into the scratch register. 60** 61** The "secondary" bus number is set to this before calling 62** pci_register_ops(). If any PPB's are present, the scan will 63** discover them and update the "secondary" and "subordinate" 64** fields in the pci_bus structure. 65** 66** Changes in the configuration *may* result in a different 67** bus number for each LBA depending on what firmware does. 68*/ 69 70#define MODULE_NAME "LBA" 71 72/* non-postable I/O port space, densely packed */ 73#define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL) 74static void __iomem *astro_iop_base __read_mostly; 75 76static u32 lba_t32; 77 78/* lba flags */ 79#define LBA_FLAG_SKIP_PROBE 0x10 80 81#define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE) 82 83 84/* Looks nice and keeps the compiler happy */ 85#define LBA_DEV(d) ((struct lba_device *) (d)) 86 87 88/* 89** Only allow 8 subsidiary busses per LBA 90** Problem is the PCI bus numbering is globally shared. 91*/ 92#define LBA_MAX_NUM_BUSES 8 93 94/************************************ 95 * LBA register read and write support 96 * 97 * BE WARNED: register writes are posted. 98 * (ie follow writes which must reach HW with a read) 99 */ 100#define READ_U8(addr) __raw_readb(addr) 101#define READ_U16(addr) __raw_readw(addr) 102#define READ_U32(addr) __raw_readl(addr) 103#define WRITE_U8(value, addr) __raw_writeb(value, addr) 104#define WRITE_U16(value, addr) __raw_writew(value, addr) 105#define WRITE_U32(value, addr) __raw_writel(value, addr) 106 107#define READ_REG8(addr) readb(addr) 108#define READ_REG16(addr) readw(addr) 109#define READ_REG32(addr) readl(addr) 110#define READ_REG64(addr) readq(addr) 111#define WRITE_REG8(value, addr) writeb(value, addr) 112#define WRITE_REG16(value, addr) writew(value, addr) 113#define WRITE_REG32(value, addr) writel(value, addr) 114 115 116#define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8)) 117#define LBA_CFG_BUS(tok) ((u8) ((tok)>>16)) 118#define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f) 119#define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7) 120 121 122/* 123** Extract LBA (Rope) number from HPA 124** REVISIT: 16 ropes for Stretch/Ike? 125*/ 126#define ROPES_PER_IOC 8 127#define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1)) 128 129 130static void 131lba_dump_res(struct resource *r, int d) 132{ 133 int i; 134 135 if (NULL == r) 136 return; 137 138 printk(KERN_DEBUG "(%p)", r->parent); 139 for (i = d; i ; --i) printk(" "); 140 printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r, 141 (long)r->start, (long)r->end, r->flags); 142 lba_dump_res(r->child, d+2); 143 lba_dump_res(r->sibling, d); 144} 145 146 147 148static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d) 149{ 150 u8 first_bus = d->hba.hba_bus->secondary; 151 u8 last_sub_bus = d->hba.hba_bus->subordinate; 152 153 if ((bus < first_bus) || 154 (bus > last_sub_bus) || 155 ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) { 156 return 0; 157 } 158 159 return 1; 160} 161 162 163 164#define LBA_CFG_SETUP(d, tok) { \ 165 /* Save contents of error config register. */ \ 166 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \ 167\ 168 /* Save contents of status control register. */ \ 169 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \ 170\ 171 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \ 172 ** arbitration for full bus walks. \ 173 */ \ 174 /* Save contents of arb mask register. */ \ 175 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \ 176\ 177 /* \ 178 * Turn off all device arbitration bits (i.e. everything \ 179 * except arbitration enable bit). \ 180 */ \ 181 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \ 182\ 183 /* \ 184 * Set the smart mode bit so that master aborts don't cause \ 185 * LBA to go into PCI fatal mode (required). \ 186 */ \ 187 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \ 188} 189 190 191#define LBA_CFG_PROBE(d, tok) { \ 192 /* \ 193 * Setup Vendor ID write and read back the address register \ 194 * to make sure that LBA is the bus master. \ 195 */ \ 196 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\ 197 /* \ 198 * Read address register to ensure that LBA is the bus master, \ 199 * which implies that DMA traffic has stopped when DMA arb is off. \ 200 */ \ 201 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 202 /* \ 203 * Generate a cfg write cycle (will have no affect on \ 204 * Vendor ID register since read-only). \ 205 */ \ 206 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \ 207 /* \ 208 * Make sure write has completed before proceeding further, \ 209 * i.e. before setting clear enable. \ 210 */ \ 211 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 212} 213 214 215/* 216 * HPREVISIT: 217 * -- Can't tell if config cycle got the error. 218 * 219 * OV bit is broken until rev 4.0, so can't use OV bit and 220 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle. 221 * 222 * As of rev 4.0, no longer need the error check. 223 * 224 * -- Even if we could tell, we still want to return -1 225 * for **ANY** error (not just master abort). 226 * 227 * -- Only clear non-fatal errors (we don't want to bring 228 * LBA out of pci-fatal mode). 229 * 230 * Actually, there is still a race in which 231 * we could be clearing a fatal error. We will 232 * live with this during our initial bus walk 233 * until rev 4.0 (no driver activity during 234 * initial bus walk). The initial bus walk 235 * has race conditions concerning the use of 236 * smart mode as well. 237 */ 238 239#define LBA_MASTER_ABORT_ERROR 0xc 240#define LBA_FATAL_ERROR 0x10 241 242#define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \ 243 u32 error_status = 0; \ 244 /* \ 245 * Set clear enable (CE) bit. Unset by HW when new \ 246 * errors are logged -- LBA HW ERS section 14.3.3). \ 247 */ \ 248 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \ 249 error_status = READ_REG32(base + LBA_ERROR_STATUS); \ 250 if ((error_status & 0x1f) != 0) { \ 251 /* \ 252 * Fail the config read request. \ 253 */ \ 254 error = 1; \ 255 if ((error_status & LBA_FATAL_ERROR) == 0) { \ 256 /* \ 257 * Clear error status (if fatal bit not set) by setting \ 258 * clear error log bit (CL). \ 259 */ \ 260 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \ 261 } \ 262 } \ 263} 264 265#define LBA_CFG_TR4_ADDR_SETUP(d, addr) \ 266 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); 267 268#define LBA_CFG_ADDR_SETUP(d, addr) { \ 269 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 270 /* \ 271 * Read address register to ensure that LBA is the bus master, \ 272 * which implies that DMA traffic has stopped when DMA arb is off. \ 273 */ \ 274 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 275} 276 277 278#define LBA_CFG_RESTORE(d, base) { \ 279 /* \ 280 * Restore status control register (turn off clear enable). \ 281 */ \ 282 WRITE_REG32(status_control, base + LBA_STAT_CTL); \ 283 /* \ 284 * Restore error config register (turn off smart mode). \ 285 */ \ 286 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \ 287 /* \ 288 * Restore arb mask register (reenables DMA arbitration). \ 289 */ \ 290 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \ 291} 292 293 294 295static unsigned int 296lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size) 297{ 298 u32 data = ~0U; 299 int error = 0; 300 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */ 301 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */ 302 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */ 303 304 LBA_CFG_SETUP(d, tok); 305 LBA_CFG_PROBE(d, tok); 306 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 307 if (!error) { 308 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 309 310 LBA_CFG_ADDR_SETUP(d, tok | reg); 311 switch (size) { 312 case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break; 313 case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break; 314 case 4: data = READ_REG32(data_reg); break; 315 } 316 } 317 LBA_CFG_RESTORE(d, d->hba.base_addr); 318 return(data); 319} 320 321 322static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 323{ 324 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 325 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 326 u32 tok = LBA_CFG_TOK(local_bus, devfn); 327 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 328 329 if ((pos > 255) || (devfn > 255)) 330 return -EINVAL; 331 332 /* if (!LBA_SKIP_PROBE(d)) */ { 333 /* original - Generate config cycle on broken elroy 334 with risk we will miss PCI bus errors. */ 335 *data = lba_rd_cfg(d, tok, pos, size); 336 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data); 337 return 0; 338 } 339 340 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) { 341 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos); 342 /* either don't want to look or know device isn't present. */ 343 *data = ~0U; 344 return(0); 345 } 346 347 /* Basic Algorithm 348 ** Should only get here on fully working LBA rev. 349 ** This is how simple the code should have been. 350 */ 351 LBA_CFG_ADDR_SETUP(d, tok | pos); 352 switch(size) { 353 case 1: *data = READ_REG8 (data_reg + (pos & 3)); break; 354 case 2: *data = READ_REG16(data_reg + (pos & 2)); break; 355 case 4: *data = READ_REG32(data_reg); break; 356 } 357 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data); 358 return 0; 359} 360 361 362static void 363lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) 364{ 365 int error = 0; 366 u32 arb_mask = 0; 367 u32 error_config = 0; 368 u32 status_control = 0; 369 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 370 371 LBA_CFG_SETUP(d, tok); 372 LBA_CFG_ADDR_SETUP(d, tok | reg); 373 switch (size) { 374 case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break; 375 case 2: WRITE_REG16(data, data_reg + (reg & 2)); break; 376 case 4: WRITE_REG32(data, data_reg); break; 377 } 378 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 379 LBA_CFG_RESTORE(d, d->hba.base_addr); 380} 381 382 383/* 384 * LBA 4.0 config write code implements non-postable semantics 385 * by doing a read of CONFIG ADDR after the write. 386 */ 387 388static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 389{ 390 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 391 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 392 u32 tok = LBA_CFG_TOK(local_bus,devfn); 393 394 if ((pos > 255) || (devfn > 255)) 395 return -EINVAL; 396 397 if (!LBA_SKIP_PROBE(d)) { 398 lba_wr_cfg(d, tok, pos, (u32) data, size); 399 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__, tok, pos,data); 400 return 0; 401 } 402 403 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) { 404 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data); 405 return 1; 406 } 407 408 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__, tok, pos, data); 409 410 /* Basic Algorithm */ 411 LBA_CFG_ADDR_SETUP(d, tok | pos); 412 switch(size) { 413 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); 414 break; 415 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); 416 break; 417 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); 418 break; 419 } 420 /* flush posted write */ 421 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 422 return 0; 423} 424 425 426static struct pci_ops elroy_cfg_ops = { 427 .read = elroy_cfg_read, 428 .write = elroy_cfg_write, 429}; 430 431/* 432 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy 433 * TR4.0 as no additional bugs were found in this areea between Elroy and 434 * Mercury 435 */ 436 437static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 438{ 439 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 440 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 441 u32 tok = LBA_CFG_TOK(local_bus, devfn); 442 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 443 444 if ((pos > 255) || (devfn > 255)) 445 return -EINVAL; 446 447 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 448 switch(size) { 449 case 1: 450 *data = READ_REG8(data_reg + (pos & 3)); 451 break; 452 case 2: 453 *data = READ_REG16(data_reg + (pos & 2)); 454 break; 455 case 4: 456 *data = READ_REG32(data_reg); break; 457 break; 458 } 459 460 DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data); 461 return 0; 462} 463 464/* 465 * LBA 4.0 config write code implements non-postable semantics 466 * by doing a read of CONFIG ADDR after the write. 467 */ 468 469static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 470{ 471 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 472 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 473 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 474 u32 tok = LBA_CFG_TOK(local_bus,devfn); 475 476 if ((pos > 255) || (devfn > 255)) 477 return -EINVAL; 478 479 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data); 480 481 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 482 switch(size) { 483 case 1: 484 WRITE_REG8 (data, data_reg + (pos & 3)); 485 break; 486 case 2: 487 WRITE_REG16(data, data_reg + (pos & 2)); 488 break; 489 case 4: 490 WRITE_REG32(data, data_reg); 491 break; 492 } 493 494 /* flush posted write */ 495 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 496 return 0; 497} 498 499static struct pci_ops mercury_cfg_ops = { 500 .read = mercury_cfg_read, 501 .write = mercury_cfg_write, 502}; 503 504 505static void 506lba_bios_init(void) 507{ 508 DBG(MODULE_NAME ": lba_bios_init\n"); 509} 510 511 512#ifdef CONFIG_64BIT 513 514static unsigned long 515truncate_pat_collision(struct resource *root, struct resource *new) 516{ 517 unsigned long start = new->start; 518 unsigned long end = new->end; 519 struct resource *tmp = root->child; 520 521 if (end <= start || start < root->start || !tmp) 522 return 0; 523 524 /* find first overlap */ 525 while (tmp && tmp->end < start) 526 tmp = tmp->sibling; 527 528 /* no entries overlap */ 529 if (!tmp) return 0; 530 531 /* found one that starts behind the new one 532 ** Don't need to do anything. 533 */ 534 if (tmp->start >= end) return 0; 535 536 if (tmp->start <= start) { 537 /* "front" of new one overlaps */ 538 new->start = tmp->end + 1; 539 540 if (tmp->end >= end) { 541 /* AACCKK! totally overlaps! drop this range. */ 542 return 1; 543 } 544 } 545 546 if (tmp->end < end ) { 547 /* "end" of new one overlaps */ 548 new->end = tmp->start - 1; 549 } 550 551 printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] " 552 "to [%lx,%lx]\n", 553 start, end, 554 (long)new->start, (long)new->end ); 555 556 return 0; /* truncation successful */ 557} 558 559#else 560#define truncate_pat_collision(r,n) (0) 561#endif 562 563/* 564** The algorithm is generic code. 565** But it needs to access local data structures to get the IRQ base. 566** Could make this a "pci_fixup_irq(bus, region)" but not sure 567** it's worth it. 568** 569** Called by do_pci_scan_bus() immediately after each PCI bus is walked. 570** Resources aren't allocated until recursive buswalk below HBA is completed. 571*/ 572static void 573lba_fixup_bus(struct pci_bus *bus) 574{ 575 struct list_head *ln; 576#ifdef FBB_SUPPORT 577 u16 status; 578#endif 579 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge)); 580 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num); 581 582 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n", 583 bus, bus->secondary, bus->bridge->platform_data); 584 585 /* 586 ** Properly Setup MMIO resources for this bus. 587 ** pci_alloc_primary_bus() mangles this. 588 */ 589 if (bus->parent) { 590 int i; 591 /* PCI-PCI Bridge */ 592 pci_read_bridge_bases(bus); 593 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 594 pci_claim_resource(bus->self, i); 595 } 596 } else { 597 /* Host-PCI Bridge */ 598 int err, i; 599 600 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 601 ldev->hba.io_space.name, 602 ldev->hba.io_space.start, ldev->hba.io_space.end, 603 ldev->hba.io_space.flags); 604 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 605 ldev->hba.lmmio_space.name, 606 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end, 607 ldev->hba.lmmio_space.flags); 608 609 err = request_resource(&ioport_resource, &(ldev->hba.io_space)); 610 if (err < 0) { 611 lba_dump_res(&ioport_resource, 2); 612 BUG(); 613 } 614 /* advertize Host bridge resources to PCI bus */ 615 bus->resource[0] = &(ldev->hba.io_space); 616 i = 1; 617 618 if (ldev->hba.elmmio_space.start) { 619 err = request_resource(&iomem_resource, 620 &(ldev->hba.elmmio_space)); 621 if (err < 0) { 622 623 printk("FAILED: lba_fixup_bus() request for " 624 "elmmio_space [%lx/%lx]\n", 625 (long)ldev->hba.elmmio_space.start, 626 (long)ldev->hba.elmmio_space.end); 627 628 /* lba_dump_res(&iomem_resource, 2); */ 629 /* BUG(); */ 630 } else 631 bus->resource[i++] = &(ldev->hba.elmmio_space); 632 } 633 634 635 if (truncate_pat_collision(&iomem_resource, 636 &(ldev->hba.lmmio_space))) { 637 638 printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n", 639 (long)ldev->hba.lmmio_space.start, 640 (long)ldev->hba.lmmio_space.end); 641 } else { 642 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); 643 if (err < 0) { 644 printk(KERN_ERR "FAILED: lba_fixup_bus() request for " 645 "lmmio_space [%lx/%lx]\n", 646 (long)ldev->hba.lmmio_space.start, 647 (long)ldev->hba.lmmio_space.end); 648 } else 649 bus->resource[i++] = &(ldev->hba.lmmio_space); 650 } 651 652#ifdef CONFIG_64BIT 653 /* GMMIO is distributed range. Every LBA/Rope gets part it. */ 654 if (ldev->hba.gmmio_space.flags) { 655 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space)); 656 if (err < 0) { 657 printk("FAILED: lba_fixup_bus() request for " 658 "gmmio_space [%lx/%lx]\n", 659 (long)ldev->hba.gmmio_space.start, 660 (long)ldev->hba.gmmio_space.end); 661 lba_dump_res(&iomem_resource, 2); 662 BUG(); 663 } 664 bus->resource[i++] = &(ldev->hba.gmmio_space); 665 } 666#endif 667 668 } 669 670 list_for_each(ln, &bus->devices) { 671 int i; 672 struct pci_dev *dev = pci_dev_b(ln); 673 674 DBG("lba_fixup_bus() %s\n", pci_name(dev)); 675 676 /* Virtualize Device/Bridge Resources. */ 677 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 678 struct resource *res = &dev->resource[i]; 679 680 /* If resource not allocated - skip it */ 681 if (!res->start) 682 continue; 683 684 if (res->flags & IORESOURCE_IO) { 685 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ", 686 res->start, res->end); 687 res->start |= lba_portbase; 688 res->end |= lba_portbase; 689 DBG("[%lx/%lx]\n", res->start, res->end); 690 } else if (res->flags & IORESOURCE_MEM) { 691 /* 692 ** Convert PCI (IO_VIEW) addresses to 693 ** processor (PA_VIEW) addresses 694 */ 695 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ", 696 res->start, res->end); 697 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start); 698 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end); 699 DBG("[%lx/%lx]\n", res->start, res->end); 700 } else { 701 DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX", 702 res->flags, res->start, res->end); 703 } 704 705 pci_claim_resource(dev, i); 706 } 707 708#ifdef FBB_SUPPORT 709 /* 710 ** If one device does not support FBB transfers, 711 ** No one on the bus can be allowed to use them. 712 */ 713 (void) pci_read_config_word(dev, PCI_STATUS, &status); 714 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK); 715#endif 716 717 /* 718 ** P2PB's have no IRQs. ignore them. 719 */ 720 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 721 continue; 722 723 /* Adjust INTERRUPT_LINE for this dev */ 724 iosapic_fixup_irq(ldev->iosapic_obj, dev); 725 } 726 727#ifdef FBB_SUPPORT 728 if (fbb_enable) { 729 if (bus->parent) { 730 u8 control; 731 /* enable on PPB */ 732 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control); 733 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK); 734 735 } else { 736 /* enable on LBA */ 737 } 738 fbb_enable = PCI_COMMAND_FAST_BACK; 739 } 740 741 /* Lastly enable FBB/PERR/SERR on all devices too */ 742 list_for_each(ln, &bus->devices) { 743 (void) pci_read_config_word(dev, PCI_COMMAND, &status); 744 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable; 745 (void) pci_write_config_word(dev, PCI_COMMAND, status); 746 } 747#endif 748} 749 750 751static struct pci_bios_ops lba_bios_ops = { 752 .init = lba_bios_init, 753 .fixup_bus = lba_fixup_bus, 754}; 755 756 757 758 759/******************************************************* 760** 761** LBA Sprockets "I/O Port" Space Accessor Functions 762** 763** This set of accessor functions is intended for use with 764** "legacy firmware" (ie Sprockets on Allegro/Forte boxes). 765** 766** Many PCI devices don't require use of I/O port space (eg Tulip, 767** NCR720) since they export the same registers to both MMIO and 768** I/O port space. In general I/O port space is slower than 769** MMIO since drivers are designed so PIO writes can be posted. 770** 771********************************************************/ 772 773#define LBA_PORT_IN(size, mask) \ 774static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \ 775{ \ 776 u##size t; \ 777 t = READ_REG##size(astro_iop_base + addr); \ 778 DBG_PORT(" 0x%x\n", t); \ 779 return (t); \ 780} 781 782LBA_PORT_IN( 8, 3) 783LBA_PORT_IN(16, 2) 784LBA_PORT_IN(32, 0) 785 786 787 788#define LBA_PORT_OUT(size, mask) \ 789static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 790{ \ 791 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \ 792 WRITE_REG##size(val, astro_iop_base + addr); \ 793 if (LBA_DEV(d)->hw_rev < 3) \ 794 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \ 795} 796 797LBA_PORT_OUT( 8, 3) 798LBA_PORT_OUT(16, 2) 799LBA_PORT_OUT(32, 0) 800 801 802static struct pci_port_ops lba_astro_port_ops = { 803 .inb = lba_astro_in8, 804 .inw = lba_astro_in16, 805 .inl = lba_astro_in32, 806 .outb = lba_astro_out8, 807 .outw = lba_astro_out16, 808 .outl = lba_astro_out32 809}; 810 811 812#ifdef CONFIG_64BIT 813#define PIOP_TO_GMMIO(lba, addr) \ 814 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3)) 815 816/******************************************************* 817** 818** LBA PAT "I/O Port" Space Accessor Functions 819** 820** This set of accessor functions is intended for use with 821** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes). 822** 823** This uses the PIOP space located in the first 64MB of GMMIO. 824** Each rope gets a full 64*KB* (ie 4 bytes per page) this way. 825** bits 1:0 stay the same. bits 15:2 become 25:12. 826** Then add the base and we can generate an I/O Port cycle. 827********************************************************/ 828#undef LBA_PORT_IN 829#define LBA_PORT_IN(size, mask) \ 830static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \ 831{ \ 832 u##size t; \ 833 DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \ 834 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \ 835 DBG_PORT(" 0x%x\n", t); \ 836 return (t); \ 837} 838 839LBA_PORT_IN( 8, 3) 840LBA_PORT_IN(16, 2) 841LBA_PORT_IN(32, 0) 842 843 844#undef LBA_PORT_OUT 845#define LBA_PORT_OUT(size, mask) \ 846static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \ 847{ \ 848 void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \ 849 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \ 850 WRITE_REG##size(val, where); \ 851 /* flush the I/O down to the elroy at least */ \ 852 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \ 853} 854 855LBA_PORT_OUT( 8, 3) 856LBA_PORT_OUT(16, 2) 857LBA_PORT_OUT(32, 0) 858 859 860static struct pci_port_ops lba_pat_port_ops = { 861 .inb = lba_pat_in8, 862 .inw = lba_pat_in16, 863 .inl = lba_pat_in32, 864 .outb = lba_pat_out8, 865 .outw = lba_pat_out16, 866 .outl = lba_pat_out32 867}; 868 869 870 871/* 872** make range information from PDC available to PCI subsystem. 873** We make the PDC call here in order to get the PCI bus range 874** numbers. The rest will get forwarded in pcibios_fixup_bus(). 875** We don't have a struct pci_bus assigned to us yet. 876*/ 877static void 878lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 879{ 880 unsigned long bytecnt; 881 long io_count; 882 long status; /* PDC return status */ 883 long pa_count; 884 pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell; /* PA_VIEW */ 885 pdc_pat_cell_mod_maddr_block_t *io_pdc_cell; /* IO_VIEW */ 886 int i; 887 888 pa_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL); 889 if (!pa_pdc_cell) 890 return; 891 892 io_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL); 893 if (!io_pdc_cell) { 894 kfree(pa_pdc_cell); 895 return; 896 } 897 898 /* return cell module (IO view) */ 899 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 900 PA_VIEW, pa_pdc_cell); 901 pa_count = pa_pdc_cell->mod[1]; 902 903 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 904 IO_VIEW, io_pdc_cell); 905 io_count = io_pdc_cell->mod[1]; 906 907 /* We've already done this once for device discovery...*/ 908 if (status != PDC_OK) { 909 panic("pdc_pat_cell_module() call failed for LBA!\n"); 910 } 911 912 if (PAT_GET_ENTITY(pa_pdc_cell->mod_info) != PAT_ENTITY_LBA) { 913 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n"); 914 } 915 916 /* 917 ** Inspect the resources PAT tells us about 918 */ 919 for (i = 0; i < pa_count; i++) { 920 struct { 921 unsigned long type; 922 unsigned long start; 923 unsigned long end; /* aka finish */ 924 } *p, *io; 925 struct resource *r; 926 927 p = (void *) &(pa_pdc_cell->mod[2+i*3]); 928 io = (void *) &(io_pdc_cell->mod[2+i*3]); 929 930 /* Convert the PAT range data to PCI "struct resource" */ 931 switch(p->type & 0xff) { 932 case PAT_PBNUM: 933 lba_dev->hba.bus_num.start = p->start; 934 lba_dev->hba.bus_num.end = p->end; 935 break; 936 937 case PAT_LMMIO: 938 /* used to fix up pre-initialized MEM BARs */ 939 if (!lba_dev->hba.lmmio_space.start) { 940 sprintf(lba_dev->hba.lmmio_name, 941 "PCI%02x LMMIO", 942 (int)lba_dev->hba.bus_num.start); 943 lba_dev->hba.lmmio_space_offset = p->start - 944 io->start; 945 r = &lba_dev->hba.lmmio_space; 946 r->name = lba_dev->hba.lmmio_name; 947 } else if (!lba_dev->hba.elmmio_space.start) { 948 sprintf(lba_dev->hba.elmmio_name, 949 "PCI%02x ELMMIO", 950 (int)lba_dev->hba.bus_num.start); 951 r = &lba_dev->hba.elmmio_space; 952 r->name = lba_dev->hba.elmmio_name; 953 } else { 954 printk(KERN_WARNING MODULE_NAME 955 " only supports 2 LMMIO resources!\n"); 956 break; 957 } 958 959 r->start = p->start; 960 r->end = p->end; 961 r->flags = IORESOURCE_MEM; 962 r->parent = r->sibling = r->child = NULL; 963 break; 964 965 case PAT_GMMIO: 966 /* MMIO space > 4GB phys addr; for 64-bit BAR */ 967 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO", 968 (int)lba_dev->hba.bus_num.start); 969 r = &lba_dev->hba.gmmio_space; 970 r->name = lba_dev->hba.gmmio_name; 971 r->start = p->start; 972 r->end = p->end; 973 r->flags = IORESOURCE_MEM; 974 r->parent = r->sibling = r->child = NULL; 975 break; 976 977 case PAT_NPIOP: 978 printk(KERN_WARNING MODULE_NAME 979 " range[%d] : ignoring NPIOP (0x%lx)\n", 980 i, p->start); 981 break; 982 983 case PAT_PIOP: 984 /* 985 ** Postable I/O port space is per PCI host adapter. 986 ** base of 64MB PIOP region 987 */ 988 lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024); 989 990 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", 991 (int)lba_dev->hba.bus_num.start); 992 r = &lba_dev->hba.io_space; 993 r->name = lba_dev->hba.io_name; 994 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num); 995 r->end = r->start + HBA_PORT_SPACE_SIZE - 1; 996 r->flags = IORESOURCE_IO; 997 r->parent = r->sibling = r->child = NULL; 998 break; 999 1000 default: 1001 printk(KERN_WARNING MODULE_NAME 1002 " range[%d] : unknown pat range type (0x%lx)\n", 1003 i, p->type & 0xff); 1004 break; 1005 } 1006 } 1007 1008 kfree(pa_pdc_cell); 1009 kfree(io_pdc_cell); 1010} 1011#else 1012/* keep compiler from complaining about missing declarations */ 1013#define lba_pat_port_ops lba_astro_port_ops 1014#define lba_pat_resources(pa_dev, lba_dev) 1015#endif /* CONFIG_64BIT */ 1016 1017 1018extern void sba_distributed_lmmio(struct parisc_device *, struct resource *); 1019extern void sba_directed_lmmio(struct parisc_device *, struct resource *); 1020 1021 1022static void 1023lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 1024{ 1025 struct resource *r; 1026 int lba_num; 1027 1028 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND; 1029 1030 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); 1031 r = &(lba_dev->hba.bus_num); 1032 r->name = "LBA PCI Busses"; 1033 r->start = lba_num & 0xff; 1034 r->end = (lba_num>>8) & 0xff; 1035 1036 /* Set up local PCI Bus resources - we don't need them for 1037 ** Legacy boxes but it's nice to see in /proc/iomem. 1038 */ 1039 r = &(lba_dev->hba.lmmio_space); 1040 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO", 1041 (int)lba_dev->hba.bus_num.start); 1042 r->name = lba_dev->hba.lmmio_name; 1043 1044 /* We want the CPU -> IO routing of addresses. 1045 * The SBA BASE/MASK registers control CPU -> IO routing. 1046 * Ask SBA what is routed to this rope/LBA. 1047 */ 1048 sba_distributed_lmmio(pa_dev, r); 1049 1050 /* 1051 ** "Directed" ranges are used when the "distributed range" isn't 1052 ** sufficient for all devices below a given LBA. Typically devices 1053 ** like graphics cards or X25 may need a directed range when the 1054 ** bus has multiple slots (ie multiple devices) or the device 1055 ** needs more than the typical 4 or 8MB a distributed range offers. 1056 ** 1057 ** The main reason for ignoring it now frigging complications. 1058 ** Directed ranges may overlap (and have precedence) over 1059 ** distributed ranges. Or a distributed range assigned to a unused 1060 ** rope may be used by a directed range on a different rope. 1061 ** Support for graphics devices may require fixing this 1062 ** since they may be assigned a directed range which overlaps 1063 ** an existing (but unused portion of) distributed range. 1064 */ 1065 r = &(lba_dev->hba.elmmio_space); 1066 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO", 1067 (int)lba_dev->hba.bus_num.start); 1068 r->name = lba_dev->hba.elmmio_name; 1069 1070 /* See comment which precedes call to sba_directed_lmmio() */ 1071 sba_directed_lmmio(pa_dev, r); 1072 1073 r = &(lba_dev->hba.io_space); 1074 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", 1075 (int)lba_dev->hba.bus_num.start); 1076 r->name = lba_dev->hba.io_name; 1077 r->flags = IORESOURCE_IO; 1078 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; 1079 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1)); 1080 1081 /* Virtualize the I/O Port space ranges */ 1082 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); 1083 r->start |= lba_num; 1084 r->end |= lba_num; 1085} 1086 1087 1088 1089static int __init 1090lba_hw_init(struct lba_device *d) 1091{ 1092 u32 stat; 1093 u32 bus_reset; /* PDC_PAT_BUG */ 1094 1095 1096#ifdef CONFIG_64BIT 1097#endif 1098 1099 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */ 1100 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; 1101 if (bus_reset) { 1102 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n"); 1103 } 1104 1105 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); 1106 if (stat & LBA_SMART_MODE) { 1107 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n"); 1108 stat &= ~LBA_SMART_MODE; 1109 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); 1110 } 1111 1112 /* Set HF mode as the default (vs. -1 mode). */ 1113 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); 1114 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); 1115 1116 /* 1117 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal 1118 ** if it's not already set. If we just cleared the PCI Bus Reset 1119 ** signal, wait a bit for the PCI devices to recover and setup. 1120 */ 1121 if (bus_reset) 1122 mdelay(pci_post_reset_delay); 1123 1124 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { 1125 /* 1126 ** PDC_PAT_BUG: PDC rev 40.48 on L2000. 1127 ** B2000/C3600/J6000 also have this problem? 1128 ** 1129 ** Elroys with hot pluggable slots don't get configured 1130 ** correctly if the slot is empty. ARB_MASK is set to 0 1131 ** and we can't master transactions on the bus if it's 1132 ** not at least one. 0x3 enables elroy and first slot. 1133 */ 1134 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n"); 1135 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); 1136 } 1137 1138 return 0; 1139} 1140 1141/* 1142 * Unfortunately, when firmware numbers busses, it doesn't take into account 1143 * Cardbus bridges. So we have to renumber the busses to suit ourselves. 1144 * Elroy/Mercury don't actually know what bus number they're attached to; 1145 * we use bus 0 to indicate the directly attached bus and any other bus 1146 * number will be taken care of by the PCI-PCI bridge. 1147 */ 1148static unsigned int lba_next_bus = 0; 1149 1150/* 1151 * Determine if lba should claim this chip (return 0) or not (return 1). 1152 * If so, initialize the chip and tell other partners in crime they 1153 * have work to do. 1154 */ 1155static int __init 1156lba_driver_probe(struct parisc_device *dev) 1157{ 1158 struct lba_device *lba_dev; 1159 struct pci_bus *lba_bus; 1160 struct pci_ops *cfg_ops; 1161 u32 func_class; 1162 void *tmp_obj; 1163 char *version; 1164 void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096); 1165 1166 /* Read HW Rev First */ 1167 func_class = READ_REG32(addr + LBA_FCLASS); 1168 1169 if (IS_ELROY(dev)) { 1170 func_class &= 0xf; 1171 switch (func_class) { 1172 case 0: version = "TR1.0"; break; 1173 case 1: version = "TR2.0"; break; 1174 case 2: version = "TR2.1"; break; 1175 case 3: version = "TR2.2"; break; 1176 case 4: version = "TR3.0"; break; 1177 case 5: version = "TR4.0"; break; 1178 default: version = "TR4+"; 1179 } 1180 1181 printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n", 1182 version, func_class & 0xf, (long)dev->hpa.start); 1183 1184 if (func_class < 2) { 1185 printk(KERN_WARNING "Can't support LBA older than " 1186 "TR2.1 - continuing under adversity.\n"); 1187 } 1188 1189 { 1190 cfg_ops = &elroy_cfg_ops; 1191 } 1192 1193 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) { 1194 int major, minor; 1195 1196 func_class &= 0xff; 1197 major = func_class >> 4, minor = func_class & 0xf; 1198 1199 /* We could use one printk for both Elroy and Mercury, 1200 * but for the mask for func_class. 1201 */ 1202 printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n", 1203 IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major, 1204 minor, func_class, (long)dev->hpa.start); 1205 1206 cfg_ops = &mercury_cfg_ops; 1207 } else { 1208 printk(KERN_ERR "Unknown LBA found at 0x%lx\n", 1209 (long)dev->hpa.start); 1210 return -ENODEV; 1211 } 1212 1213 /* Tell I/O SAPIC driver we have a IRQ handler/region. */ 1214 tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE); 1215 1216 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't 1217 ** have an IRT entry will get NULL back from iosapic code. 1218 */ 1219 1220 lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL); 1221 if (!lba_dev) { 1222 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n"); 1223 return(1); 1224 } 1225 1226 1227 /* ---------- First : initialize data we already have --------- */ 1228 1229 lba_dev->hw_rev = func_class; 1230 lba_dev->hba.base_addr = addr; 1231 lba_dev->hba.dev = dev; 1232 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */ 1233 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ 1234 parisc_set_drvdata(dev, lba_dev); 1235 1236 /* ------------ Second : initialize common stuff ---------- */ 1237 pci_bios = &lba_bios_ops; 1238 pcibios_register_hba(HBA_DATA(lba_dev)); 1239 spin_lock_init(&lba_dev->lba_lock); 1240 1241 if (lba_hw_init(lba_dev)) 1242 return(1); 1243 1244 /* ---------- Third : setup I/O Port and MMIO resources --------- */ 1245 1246 if (is_pdc_pat()) { 1247 /* PDC PAT firmware uses PIOP region of GMMIO space. */ 1248 pci_port = &lba_pat_port_ops; 1249 /* Go ask PDC PAT what resources this LBA has */ 1250 lba_pat_resources(dev, lba_dev); 1251 } else { 1252 if (!astro_iop_base) { 1253 /* Sprockets PDC uses NPIOP region */ 1254 astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024); 1255 pci_port = &lba_astro_port_ops; 1256 } 1257 1258 /* Poke the chip a bit for /proc output */ 1259 lba_legacy_resources(dev, lba_dev); 1260 } 1261 1262 if (lba_dev->hba.bus_num.start < lba_next_bus) 1263 lba_dev->hba.bus_num.start = lba_next_bus; 1264 1265 dev->dev.platform_data = lba_dev; 1266 lba_bus = lba_dev->hba.hba_bus = 1267 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start, 1268 cfg_ops, NULL); 1269 1270 /* This is in lieu of calling pci_assign_unassigned_resources() */ 1271 if (is_pdc_pat()) { 1272 /* assign resources to un-initialized devices */ 1273 1274 DBG_PAT("LBA pci_bus_size_bridges()\n"); 1275 pci_bus_size_bridges(lba_bus); 1276 1277 DBG_PAT("LBA pci_bus_assign_resources()\n"); 1278 pci_bus_assign_resources(lba_bus); 1279 1280#ifdef DEBUG_LBA_PAT 1281 DBG_PAT("\nLBA PIOP resource tree\n"); 1282 lba_dump_res(&lba_dev->hba.io_space, 2); 1283 DBG_PAT("\nLBA LMMIO resource tree\n"); 1284 lba_dump_res(&lba_dev->hba.lmmio_space, 2); 1285#endif 1286 } 1287 pci_enable_bridges(lba_bus); 1288 1289 /* 1290 ** Once PCI register ops has walked the bus, access to config 1291 ** space is restricted. Avoids master aborts on config cycles. 1292 ** Early LBA revs go fatal on *any* master abort. 1293 */ 1294 if (cfg_ops == &elroy_cfg_ops) { 1295 lba_dev->flags |= LBA_FLAG_SKIP_PROBE; 1296 } 1297 1298 if (lba_bus) { 1299 lba_next_bus = lba_bus->subordinate + 1; 1300 pci_bus_add_devices(lba_bus); 1301 } 1302 1303 /* Whew! Finally done! Tell services we got this one covered. */ 1304 return 0; 1305} 1306 1307static struct parisc_device_id lba_tbl[] = { 1308 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa }, 1309 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa }, 1310 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa }, 1311 { 0, } 1312}; 1313 1314static struct parisc_driver lba_driver = { 1315 .name = MODULE_NAME, 1316 .id_table = lba_tbl, 1317 .probe = lba_driver_probe, 1318}; 1319 1320/* 1321** One time initialization to let the world know the LBA was found. 1322** Must be called exactly once before pci_init(). 1323*/ 1324void __init lba_init(void) 1325{ 1326 register_parisc_driver(&lba_driver); 1327} 1328 1329/* 1330** Initialize the IBASE/IMASK registers for LBA (Elroy). 1331** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA). 1332** sba_iommu is responsible for locking (none needed at init time). 1333*/ 1334void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask) 1335{ 1336 void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096); 1337 1338 imask <<= 2; /* adjust for hints - 2 more bits */ 1339 1340 /* Make sure we aren't trying to set bits that aren't writeable. */ 1341 WARN_ON((ibase & 0x001fffff) != 0); 1342 WARN_ON((imask & 0x001fffff) != 0); 1343 1344 DBG("%s() ibase 0x%x imask 0x%x\n", __func__, ibase, imask); 1345 WRITE_REG32( imask, base_addr + LBA_IMASK); 1346 WRITE_REG32( ibase, base_addr + LBA_IBASE); 1347 iounmap(base_addr); 1348} 1349