1/* 2** I/O Sapic Driver - PCI interrupt line support 3** 4** (c) Copyright 1999 Grant Grundler 5** (c) Copyright 1999 Hewlett-Packard Company 6** 7** This program is free software; you can redistribute it and/or modify 8** it under the terms of the GNU General Public License as published by 9** the Free Software Foundation; either version 2 of the License, or 10** (at your option) any later version. 11** 12** The I/O sapic driver manages the Interrupt Redirection Table which is 13** the control logic to convert PCI line based interrupts into a Message 14** Signaled Interrupt (aka Transaction Based Interrupt, TBI). 15** 16** Acronyms 17** -------- 18** HPA Hard Physical Address (aka MMIO address) 19** IRQ Interrupt ReQuest. Implies Line based interrupt. 20** IRT Interrupt Routing Table (provided by PAT firmware) 21** IRdT Interrupt Redirection Table. IRQ line to TXN ADDR/DATA 22** table which is implemented in I/O SAPIC. 23** ISR Interrupt Service Routine. aka Interrupt handler. 24** MSI Message Signaled Interrupt. PCI 2.2 functionality. 25** aka Transaction Based Interrupt (or TBI). 26** PA Precision Architecture. HP's RISC architecture. 27** RISC Reduced Instruction Set Computer. 28** 29** 30** What's a Message Signalled Interrupt? 31** ------------------------------------- 32** MSI is a write transaction which targets a processor and is similar 33** to a processor write to memory or MMIO. MSIs can be generated by I/O 34** devices as well as processors and require *architecture* to work. 35** 36** PA only supports MSI. So I/O subsystems must either natively generate 37** MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs 38** (e.g. PCI and EISA). IA64 supports MSIs via a "local SAPIC" which 39** acts on behalf of a processor. 40** 41** MSI allows any I/O device to interrupt any processor. This makes 42** load balancing of the interrupt processing possible on an SMP platform. 43** Interrupts are also ordered WRT to DMA data. It's possible on I/O 44** coherent systems to completely eliminate PIO reads from the interrupt 45** path. The device and driver must be designed and implemented to 46** guarantee all DMA has been issued (issues about atomicity here) 47** before the MSI is issued. I/O status can then safely be read from 48** DMA'd data by the ISR. 49** 50** 51** PA Firmware 52** ----------- 53** PA-RISC platforms have two fundamentally different types of firmware. 54** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register 55** and BARs similar to a traditional PC BIOS. 56** The newer "PAT" firmware supports PDC calls which return tables. 57** PAT firmware only initializes the PCI Console and Boot interface. 58** With these tables, the OS can program all other PCI devices. 59** 60** One such PAT PDC call returns the "Interrupt Routing Table" (IRT). 61** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC 62** input line. If the IRT is not available, this driver assumes 63** INTERRUPT_LINE register has been programmed by firmware. The latter 64** case also means online addition of PCI cards can NOT be supported 65** even if HW support is present. 66** 67** All platforms with PAT firmware to date (Oct 1999) use one Interrupt 68** Routing Table for the entire platform. 69** 70** Where's the iosapic? 71** -------------------- 72** I/O sapic is part of the "Core Electronics Complex". And on HP platforms 73** it's integrated as part of the PCI bus adapter, "lba". So no bus walk 74** will discover I/O Sapic. I/O Sapic driver learns about each device 75** when lba driver advertises the presence of the I/O sapic by calling 76** iosapic_register(). 77** 78** 79** IRQ handling notes 80** ------------------ 81** The IO-SAPIC can indicate to the CPU which interrupt was asserted. 82** So, unlike the GSC-ASIC and Dino, we allocate one CPU interrupt per 83** IO-SAPIC interrupt and call the device driver's handler directly. 84** The IO-SAPIC driver hijacks the CPU interrupt handler so it can 85** issue the End Of Interrupt command to the IO-SAPIC. 86** 87** Overview of exported iosapic functions 88** -------------------------------------- 89** (caveat: code isn't finished yet - this is just the plan) 90** 91** iosapic_init: 92** o initialize globals (lock, etc) 93** o try to read IRT. Presence of IRT determines if this is 94** a PAT platform or not. 95** 96** iosapic_register(): 97** o create iosapic_info instance data structure 98** o allocate vector_info array for this iosapic 99** o initialize vector_info - read corresponding IRdT? 100** 101** iosapic_xlate_pin: (only called by fixup_irq for PAT platform) 102** o intr_pin = read cfg (INTERRUPT_PIN); 103** o if (device under PCI-PCI bridge) 104** translate slot/pin 105** 106** iosapic_fixup_irq: 107** o if PAT platform (IRT present) 108** intr_pin = iosapic_xlate_pin(isi,pcidev): 109** intr_line = find IRT entry(isi, PCI_SLOT(pcidev), intr_pin) 110** save IRT entry into vector_info later 111** write cfg INTERRUPT_LINE (with intr_line)? 112** else 113** intr_line = pcidev->irq 114** IRT pointer = NULL 115** endif 116** o locate vector_info (needs: isi, intr_line) 117** o allocate processor "irq" and get txn_addr/data 118** o request_irq(processor_irq, iosapic_interrupt, vector_info,...) 119** 120** iosapic_enable_irq: 121** o clear any pending IRQ on that line 122** o enable IRdT - call enable_irq(vector[line]->processor_irq) 123** o write EOI in case line is already asserted. 124** 125** iosapic_disable_irq: 126** o disable IRdT - call disable_irq(vector[line]->processor_irq) 127*/ 128 129 130#include <linux/types.h> 131#include <linux/kernel.h> 132#include <linux/spinlock.h> 133#include <linux/pci.h> 134#include <linux/init.h> 135#include <linux/slab.h> 136#include <linux/interrupt.h> 137 138#include <asm/byteorder.h> /* get in-line asm for swab */ 139#include <asm/pdc.h> 140#include <asm/pdcpat.h> 141#include <asm/page.h> 142#include <asm/system.h> 143#include <asm/io.h> /* read/write functions */ 144#ifdef CONFIG_SUPERIO 145#include <asm/superio.h> 146#endif 147 148#include <asm/ropes.h> 149#include "./iosapic_private.h" 150 151#define MODULE_NAME "iosapic" 152 153/* "local" compile flags */ 154#undef PCI_BRIDGE_FUNCS 155#undef DEBUG_IOSAPIC 156#undef DEBUG_IOSAPIC_IRT 157 158 159#ifdef DEBUG_IOSAPIC 160#define DBG(x...) printk(x) 161#else /* DEBUG_IOSAPIC */ 162#define DBG(x...) 163#endif /* DEBUG_IOSAPIC */ 164 165#ifdef DEBUG_IOSAPIC_IRT 166#define DBG_IRT(x...) printk(x) 167#else 168#define DBG_IRT(x...) 169#endif 170 171#ifdef CONFIG_64BIT 172#define COMPARE_IRTE_ADDR(irte, hpa) ((irte)->dest_iosapic_addr == (hpa)) 173#else 174#define COMPARE_IRTE_ADDR(irte, hpa) \ 175 ((irte)->dest_iosapic_addr == ((hpa) | 0xffffffff00000000ULL)) 176#endif 177 178#define IOSAPIC_REG_SELECT 0x00 179#define IOSAPIC_REG_WINDOW 0x10 180#define IOSAPIC_REG_EOI 0x40 181 182#define IOSAPIC_REG_VERSION 0x1 183 184#define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2) 185#define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2) 186 187static inline unsigned int iosapic_read(void __iomem *iosapic, unsigned int reg) 188{ 189 writel(reg, iosapic + IOSAPIC_REG_SELECT); 190 return readl(iosapic + IOSAPIC_REG_WINDOW); 191} 192 193static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val) 194{ 195 writel(reg, iosapic + IOSAPIC_REG_SELECT); 196 writel(val, iosapic + IOSAPIC_REG_WINDOW); 197} 198 199#define IOSAPIC_VERSION_MASK 0x000000ff 200#define IOSAPIC_VERSION(ver) ((int) (ver & IOSAPIC_VERSION_MASK)) 201 202#define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000 203#define IOSAPIC_MAX_ENTRY_SHIFT 0x10 204#define IOSAPIC_IRDT_MAX_ENTRY(ver) \ 205 (int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT) 206 207/* bits in the "low" I/O Sapic IRdT entry */ 208#define IOSAPIC_IRDT_ENABLE 0x10000 209#define IOSAPIC_IRDT_PO_LOW 0x02000 210#define IOSAPIC_IRDT_LEVEL_TRIG 0x08000 211#define IOSAPIC_IRDT_MODE_LPRI 0x00100 212 213/* bits in the "high" I/O Sapic IRdT entry */ 214#define IOSAPIC_IRDT_ID_EID_SHIFT 0x10 215 216 217static DEFINE_SPINLOCK(iosapic_lock); 218 219static inline void iosapic_eoi(void __iomem *addr, unsigned int data) 220{ 221 __raw_writel(data, addr); 222} 223 224/* 225** REVISIT: future platforms may have more than one IRT. 226** If so, the following three fields form a structure which 227** then be linked into a list. Names are chosen to make searching 228** for them easy - not necessarily accurate (eg "cell"). 229** 230** Alternative: iosapic_info could point to the IRT it's in. 231** iosapic_register() could search a list of IRT's. 232*/ 233static struct irt_entry *irt_cell; 234static size_t irt_num_entry; 235 236static struct irt_entry *iosapic_alloc_irt(int num_entries) 237{ 238 unsigned long a; 239 240 /* The IRT needs to be 8-byte aligned for the PDC call. 241 * Normally kmalloc would guarantee larger alignment, but 242 * if CONFIG_DEBUG_SLAB is enabled, then we can get only 243 * 4-byte alignment on 32-bit kernels 244 */ 245 a = (unsigned long)kmalloc(sizeof(struct irt_entry) * num_entries + 8, GFP_KERNEL); 246 a = (a + 7UL) & ~7UL; 247 return (struct irt_entry *)a; 248} 249 250/** 251 * iosapic_load_irt - Fill in the interrupt routing table 252 * @cell_num: The cell number of the CPU we're currently executing on 253 * @irt: The address to place the new IRT at 254 * @return The number of entries found 255 * 256 * The "Get PCI INT Routing Table Size" option returns the number of 257 * entries in the PCI interrupt routing table for the cell specified 258 * in the cell_number argument. The cell number must be for a cell 259 * within the caller's protection domain. 260 * 261 * The "Get PCI INT Routing Table" option returns, for the cell 262 * specified in the cell_number argument, the PCI interrupt routing 263 * table in the caller allocated memory pointed to by mem_addr. 264 * We assume the IRT only contains entries for I/O SAPIC and 265 * calculate the size based on the size of I/O sapic entries. 266 * 267 * The PCI interrupt routing table entry format is derived from the 268 * IA64 SAL Specification 2.4. The PCI interrupt routing table defines 269 * the routing of PCI interrupt signals between the PCI device output 270 * "pins" and the IO SAPICs' input "lines" (including core I/O PCI 271 * devices). This table does NOT include information for devices/slots 272 * behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec. 273 * for the architected method of routing of IRQ's behind PPB's. 274 */ 275 276 277static int __init 278iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt) 279{ 280 long status; /* PDC return value status */ 281 struct irt_entry *table; /* start of interrupt routing tbl */ 282 unsigned long num_entries = 0UL; 283 284 BUG_ON(!irt); 285 286 if (is_pdc_pat()) { 287 /* Use pat pdc routine to get interrupt routing table size */ 288 DBG("calling get_irt_size (cell %ld)\n", cell_num); 289 status = pdc_pat_get_irt_size(&num_entries, cell_num); 290 DBG("get_irt_size: %ld\n", status); 291 292 BUG_ON(status != PDC_OK); 293 BUG_ON(num_entries == 0); 294 295 /* 296 ** allocate memory for interrupt routing table 297 ** This interface isn't really right. We are assuming 298 ** the contents of the table are exclusively 299 ** for I/O sapic devices. 300 */ 301 table = iosapic_alloc_irt(num_entries); 302 if (table == NULL) { 303 printk(KERN_WARNING MODULE_NAME ": read_irt : can " 304 "not alloc mem for IRT\n"); 305 return 0; 306 } 307 308 /* get PCI INT routing table */ 309 status = pdc_pat_get_irt(table, cell_num); 310 DBG("pdc_pat_get_irt: %ld\n", status); 311 WARN_ON(status != PDC_OK); 312 } else { 313 /* 314 ** C3000/J5000 (and similar) platforms with Sprockets PDC 315 ** will return exactly one IRT for all iosapics. 316 ** So if we have one, don't need to get it again. 317 */ 318 if (irt_cell) 319 return 0; 320 321 /* Should be using the Elroy's HPA, but it's ignored anyway */ 322 status = pdc_pci_irt_size(&num_entries, 0); 323 DBG("pdc_pci_irt_size: %ld\n", status); 324 325 if (status != PDC_OK) { 326 /* Not a "legacy" system with I/O SAPIC either */ 327 return 0; 328 } 329 330 BUG_ON(num_entries == 0); 331 332 table = iosapic_alloc_irt(num_entries); 333 if (!table) { 334 printk(KERN_WARNING MODULE_NAME ": read_irt : can " 335 "not alloc mem for IRT\n"); 336 return 0; 337 } 338 339 /* HPA ignored by this call too. */ 340 status = pdc_pci_irt(num_entries, 0, table); 341 BUG_ON(status != PDC_OK); 342 } 343 344 /* return interrupt table address */ 345 *irt = table; 346 347#ifdef DEBUG_IOSAPIC_IRT 348{ 349 struct irt_entry *p = table; 350 int i; 351 352 printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num); 353 printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n", 354 table, 355 num_entries, 356 (int) sizeof(struct irt_entry)); 357 358 for (i = 0 ; i < num_entries ; i++, p++) { 359 printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n", 360 p->entry_type, p->entry_length, p->interrupt_type, 361 p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id, 362 p->src_seg_id, p->dest_iosapic_intin, 363 ((u32 *) p)[2], 364 ((u32 *) p)[3] 365 ); 366 } 367} 368#endif /* DEBUG_IOSAPIC_IRT */ 369 370 return num_entries; 371} 372 373 374 375void __init iosapic_init(void) 376{ 377 unsigned long cell = 0; 378 379 DBG("iosapic_init()\n"); 380 381#ifdef __LP64__ 382 if (is_pdc_pat()) { 383 int status; 384 struct pdc_pat_cell_num cell_info; 385 386 status = pdc_pat_cell_get_number(&cell_info); 387 if (status == PDC_OK) { 388 cell = cell_info.cell_num; 389 } 390 } 391#endif 392 393 /* get interrupt routing table for this cell */ 394 irt_num_entry = iosapic_load_irt(cell, &irt_cell); 395 if (irt_num_entry == 0) 396 irt_cell = NULL; /* old PDC w/o iosapic */ 397} 398 399 400/* 401** Return the IRT entry in case we need to look something else up. 402*/ 403static struct irt_entry * 404irt_find_irqline(struct iosapic_info *isi, u8 slot, u8 intr_pin) 405{ 406 struct irt_entry *i = irt_cell; 407 int cnt; /* track how many entries we've looked at */ 408 u8 irq_devno = (slot << IRT_DEV_SHIFT) | (intr_pin-1); 409 410 DBG_IRT("irt_find_irqline() SLOT %d pin %d\n", slot, intr_pin); 411 412 for (cnt=0; cnt < irt_num_entry; cnt++, i++) { 413 414 /* 415 ** Validate: entry_type, entry_length, interrupt_type 416 ** 417 ** Difference between validate vs compare is the former 418 ** should print debug info and is not expected to "fail" 419 ** on current platforms. 420 */ 421 if (i->entry_type != IRT_IOSAPIC_TYPE) { 422 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d type %d\n", i, cnt, i->entry_type); 423 continue; 424 } 425 426 if (i->entry_length != IRT_IOSAPIC_LENGTH) { 427 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d length %d\n", i, cnt, i->entry_length); 428 continue; 429 } 430 431 if (i->interrupt_type != IRT_VECTORED_INTR) { 432 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d interrupt_type %d\n", i, cnt, i->interrupt_type); 433 continue; 434 } 435 436 if (!COMPARE_IRTE_ADDR(i, isi->isi_hpa)) 437 continue; 438 439 if ((i->src_bus_irq_devno & IRT_IRQ_DEVNO_MASK) != irq_devno) 440 continue; 441 442 /* 443 ** Ignore: src_bus_id and rc_seg_id correlate with 444 ** iosapic_info->isi_hpa on HP platforms. 445 ** If needed, pass in "PFA" (aka config space addr) 446 ** instead of slot. 447 */ 448 449 /* Found it! */ 450 return i; 451 } 452 453 printk(KERN_WARNING MODULE_NAME ": 0x%lx : no IRT entry for slot %d, pin %d\n", 454 isi->isi_hpa, slot, intr_pin); 455 return NULL; 456} 457 458 459/* 460** xlate_pin() supports the skewing of IRQ lines done by subsidiary bridges. 461** Legacy PDC already does this translation for us and stores it in INTR_LINE. 462** 463** PAT PDC needs to basically do what legacy PDC does: 464** o read PIN 465** o adjust PIN in case device is "behind" a PPB 466** (eg 4-port 100BT and SCSI/LAN "Combo Card") 467** o convert slot/pin to I/O SAPIC input line. 468** 469** HP platforms only support: 470** o one level of skewing for any number of PPBs 471** o only support PCI-PCI Bridges. 472*/ 473static struct irt_entry * 474iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev) 475{ 476 u8 intr_pin, intr_slot; 477 478 pci_read_config_byte(pcidev, PCI_INTERRUPT_PIN, &intr_pin); 479 480 DBG_IRT("iosapic_xlate_pin(%s) SLOT %d pin %d\n", 481 pcidev->slot_name, PCI_SLOT(pcidev->devfn), intr_pin); 482 483 if (intr_pin == 0) { 484 /* The device does NOT support/use IRQ lines. */ 485 return NULL; 486 } 487 488 /* Check if pcidev behind a PPB */ 489 if (pcidev->bus->parent) { 490 /* Convert pcidev INTR_PIN into something we 491 ** can lookup in the IRT. 492 */ 493#ifdef PCI_BRIDGE_FUNCS 494 /* 495 ** Proposal #1: 496 ** 497 ** call implementation specific translation function 498 ** This is architecturally "cleaner". HP-UX doesn't 499 ** support other secondary bus types (eg. E/ISA) directly. 500 ** May be needed for other processor (eg IA64) architectures 501 ** or by some ambitous soul who wants to watch TV. 502 */ 503 if (pci_bridge_funcs->xlate_intr_line) { 504 intr_pin = pci_bridge_funcs->xlate_intr_line(pcidev); 505 } 506#else /* PCI_BRIDGE_FUNCS */ 507 struct pci_bus *p = pcidev->bus; 508 /* 509 ** Proposal #2: 510 ** The "pin" is skewed ((pin + dev - 1) % 4). 511 ** 512 ** This isn't very clean since I/O SAPIC must assume: 513 ** - all platforms only have PCI busses. 514 ** - only PCI-PCI bridge (eg not PCI-EISA, PCI-PCMCIA) 515 ** - IRQ routing is only skewed once regardless of 516 ** the number of PPB's between iosapic and device. 517 ** (Bit3 expansion chassis follows this rule) 518 ** 519 ** Advantage is it's really easy to implement. 520 */ 521 intr_pin = pci_swizzle_interrupt_pin(pcidev, intr_pin); 522#endif /* PCI_BRIDGE_FUNCS */ 523 524 /* 525 * Locate the host slot of the PPB. 526 */ 527 while (p->parent->parent) 528 p = p->parent; 529 530 intr_slot = PCI_SLOT(p->self->devfn); 531 } else { 532 intr_slot = PCI_SLOT(pcidev->devfn); 533 } 534 DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n", 535 pcidev->bus->secondary, intr_slot, intr_pin); 536 537 return irt_find_irqline(isi, intr_slot, intr_pin); 538} 539 540static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1) 541{ 542 struct iosapic_info *isp = vi->iosapic; 543 u8 idx = vi->irqline; 544 545 *dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx)); 546 *dp1 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY_HI(idx)); 547} 548 549 550static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1) 551{ 552 struct iosapic_info *isp = vi->iosapic; 553 554 DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %lx 0x%x 0x%x\n", 555 vi->irqline, isp->isi_hpa, dp0, dp1); 556 557 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0); 558 559 /* Read the window register to flush the writes down to HW */ 560 dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW); 561 562 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1); 563 564 /* Read the window register to flush the writes down to HW */ 565 dp1 = readl(isp->addr+IOSAPIC_REG_WINDOW); 566} 567 568/* 569** set_irt prepares the data (dp0, dp1) according to the vector_info 570** and target cpu (id_eid). dp0/dp1 are then used to program I/O SAPIC 571** IRdT for the given "vector" (aka IRQ line). 572*/ 573static void 574iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1) 575{ 576 u32 mode = 0; 577 struct irt_entry *p = vi->irte; 578 579 if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO) 580 mode |= IOSAPIC_IRDT_PO_LOW; 581 582 if (((p->polarity_trigger >> IRT_EL_SHIFT) & IRT_EL_MASK) == IRT_LEVEL_TRIG) 583 mode |= IOSAPIC_IRDT_LEVEL_TRIG; 584 585 /* 586 ** IA64 REVISIT 587 ** PA doesn't support EXTINT or LPRIO bits. 588 */ 589 590 *dp0 = mode | (u32) vi->txn_data; 591 592 /* 593 ** Extracting id_eid isn't a real clean way of getting it. 594 ** But the encoding is the same for both PA and IA64 platforms. 595 */ 596 if (is_pdc_pat()) { 597 /* 598 ** PAT PDC just hands it to us "right". 599 ** txn_addr comes from cpu_data[x].txn_addr. 600 */ 601 *dp1 = (u32) (vi->txn_addr); 602 } else { 603 /* 604 ** eg if base_addr == 0xfffa0000), 605 ** we want to get 0xa0ff0000. 606 ** 607 ** eid 0x0ff00000 -> 0x00ff0000 608 ** id 0x000ff000 -> 0xff000000 609 */ 610 *dp1 = (((u32)vi->txn_addr & 0x0ff00000) >> 4) | 611 (((u32)vi->txn_addr & 0x000ff000) << 12); 612 } 613 DBG_IRT("iosapic_set_irt_data(): 0x%x 0x%x\n", *dp0, *dp1); 614} 615 616 617static struct vector_info *iosapic_get_vector(unsigned int irq) 618{ 619 struct irq_desc *desc = irq_to_desc(irq); 620 621 return desc->chip_data; 622} 623 624static void iosapic_disable_irq(unsigned int irq) 625{ 626 unsigned long flags; 627 struct vector_info *vi = iosapic_get_vector(irq); 628 u32 d0, d1; 629 630 spin_lock_irqsave(&iosapic_lock, flags); 631 iosapic_rd_irt_entry(vi, &d0, &d1); 632 d0 |= IOSAPIC_IRDT_ENABLE; 633 iosapic_wr_irt_entry(vi, d0, d1); 634 spin_unlock_irqrestore(&iosapic_lock, flags); 635} 636 637static void iosapic_enable_irq(unsigned int irq) 638{ 639 struct vector_info *vi = iosapic_get_vector(irq); 640 u32 d0, d1; 641 642 /* data is initialized by fixup_irq */ 643 WARN_ON(vi->txn_irq == 0); 644 645 iosapic_set_irt_data(vi, &d0, &d1); 646 iosapic_wr_irt_entry(vi, d0, d1); 647 648#ifdef DEBUG_IOSAPIC_IRT 649{ 650 u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL); 651 printk("iosapic_enable_irq(): regs %p", vi->eoi_addr); 652 for ( ; t < vi->eoi_addr; t++) 653 printk(" %x", readl(t)); 654 printk("\n"); 655} 656 657printk("iosapic_enable_irq(): sel "); 658{ 659 struct iosapic_info *isp = vi->iosapic; 660 661 for (d0=0x10; d0<0x1e; d0++) { 662 d1 = iosapic_read(isp->addr, d0); 663 printk(" %x", d1); 664 } 665} 666printk("\n"); 667#endif 668 669 /* 670 * Issuing I/O SAPIC an EOI causes an interrupt IFF IRQ line is 671 * asserted. IRQ generally should not be asserted when a driver 672 * enables their IRQ. It can lead to "interesting" race conditions 673 * in the driver initialization sequence. 674 */ 675 DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", irq, 676 vi->eoi_addr, vi->eoi_data); 677 iosapic_eoi(vi->eoi_addr, vi->eoi_data); 678} 679 680/* 681 * PARISC only supports PCI devices below I/O SAPIC. 682 * PCI only supports level triggered in order to share IRQ lines. 683 * ergo I/O SAPIC must always issue EOI on parisc. 684 * 685 * i386/ia64 support ISA devices and have to deal with 686 * edge-triggered interrupts too. 687 */ 688static void iosapic_end_irq(unsigned int irq) 689{ 690 struct vector_info *vi = iosapic_get_vector(irq); 691 DBG(KERN_DEBUG "end_irq(%d): eoi(%p, 0x%x)\n", irq, 692 vi->eoi_addr, vi->eoi_data); 693 iosapic_eoi(vi->eoi_addr, vi->eoi_data); 694 cpu_end_irq(irq); 695} 696 697static unsigned int iosapic_startup_irq(unsigned int irq) 698{ 699 iosapic_enable_irq(irq); 700 return 0; 701} 702 703#ifdef CONFIG_SMP 704static int iosapic_set_affinity_irq(unsigned int irq, 705 const struct cpumask *dest) 706{ 707 struct vector_info *vi = iosapic_get_vector(irq); 708 u32 d0, d1, dummy_d0; 709 unsigned long flags; 710 int dest_cpu; 711 712 dest_cpu = cpu_check_affinity(irq, dest); 713 if (dest_cpu < 0) 714 return -1; 715 716 cpumask_copy(irq_desc[irq].affinity, cpumask_of(dest_cpu)); 717 vi->txn_addr = txn_affinity_addr(irq, dest_cpu); 718 719 spin_lock_irqsave(&iosapic_lock, flags); 720 /* d1 contains the destination CPU, so only want to set that 721 * entry */ 722 iosapic_rd_irt_entry(vi, &d0, &d1); 723 iosapic_set_irt_data(vi, &dummy_d0, &d1); 724 iosapic_wr_irt_entry(vi, d0, d1); 725 spin_unlock_irqrestore(&iosapic_lock, flags); 726 727 return 0; 728} 729#endif 730 731static struct irq_chip iosapic_interrupt_type = { 732 .name = "IO-SAPIC-level", 733 .startup = iosapic_startup_irq, 734 .shutdown = iosapic_disable_irq, 735 .enable = iosapic_enable_irq, 736 .disable = iosapic_disable_irq, 737 .ack = cpu_ack_irq, 738 .end = iosapic_end_irq, 739#ifdef CONFIG_SMP 740 .set_affinity = iosapic_set_affinity_irq, 741#endif 742}; 743 744int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev) 745{ 746 struct iosapic_info *isi = isi_obj; 747 struct irt_entry *irte = NULL; /* only used if PAT PDC */ 748 struct vector_info *vi; 749 int isi_line; /* line used by device */ 750 751 if (!isi) { 752 printk(KERN_WARNING MODULE_NAME ": hpa not registered for %s\n", 753 pci_name(pcidev)); 754 return -1; 755 } 756 757#ifdef CONFIG_SUPERIO 758 /* 759 * HACK ALERT! (non-compliant PCI device support) 760 * 761 * All SuckyIO interrupts are routed through the PIC's on function 1. 762 * But SuckyIO OHCI USB controller gets an IRT entry anyway because 763 * it advertises INT D for INT_PIN. Use that IRT entry to get the 764 * SuckyIO interrupt routing for PICs on function 1 (*BLEECCHH*). 765 */ 766 if (is_superio_device(pcidev)) { 767 /* We must call superio_fixup_irq() to register the pdev */ 768 pcidev->irq = superio_fixup_irq(pcidev); 769 770 /* Don't return if need to program the IOSAPIC's IRT... */ 771 if (PCI_FUNC(pcidev->devfn) != SUPERIO_USB_FN) 772 return pcidev->irq; 773 } 774#endif /* CONFIG_SUPERIO */ 775 776 /* lookup IRT entry for isi/slot/pin set */ 777 irte = iosapic_xlate_pin(isi, pcidev); 778 if (!irte) { 779 printk("iosapic: no IRTE for %s (IRQ not connected?)\n", 780 pci_name(pcidev)); 781 return -1; 782 } 783 DBG_IRT("iosapic_fixup_irq(): irte %p %x %x %x %x %x %x %x %x\n", 784 irte, 785 irte->entry_type, 786 irte->entry_length, 787 irte->polarity_trigger, 788 irte->src_bus_irq_devno, 789 irte->src_bus_id, 790 irte->src_seg_id, 791 irte->dest_iosapic_intin, 792 (u32) irte->dest_iosapic_addr); 793 isi_line = irte->dest_iosapic_intin; 794 795 /* get vector info for this input line */ 796 vi = isi->isi_vector + isi_line; 797 DBG_IRT("iosapic_fixup_irq: line %d vi 0x%p\n", isi_line, vi); 798 799 /* If this IRQ line has already been setup, skip it */ 800 if (vi->irte) 801 goto out; 802 803 vi->irte = irte; 804 805 vi->txn_irq = txn_alloc_irq(8); 806 807 if (vi->txn_irq < 0) 808 panic("I/O sapic: couldn't get TXN IRQ\n"); 809 810 /* enable_irq() will use txn_* to program IRdT */ 811 vi->txn_addr = txn_alloc_addr(vi->txn_irq); 812 vi->txn_data = txn_alloc_data(vi->txn_irq); 813 814 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI; 815 vi->eoi_data = cpu_to_le32(vi->txn_data); 816 817 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi); 818 819 out: 820 pcidev->irq = vi->txn_irq; 821 822 DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n", 823 PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn), 824 pcidev->vendor, pcidev->device, isi_line, pcidev->irq); 825 826 return pcidev->irq; 827} 828 829 830/* 831** squirrel away the I/O Sapic Version 832*/ 833static unsigned int 834iosapic_rd_version(struct iosapic_info *isi) 835{ 836 return iosapic_read(isi->addr, IOSAPIC_REG_VERSION); 837} 838 839 840/* 841** iosapic_register() is called by "drivers" with an integrated I/O SAPIC. 842** Caller must be certain they have an I/O SAPIC and know its MMIO address. 843** 844** o allocate iosapic_info and add it to the list 845** o read iosapic version and squirrel that away 846** o read size of IRdT. 847** o allocate and initialize isi_vector[] 848** o allocate irq region 849*/ 850void *iosapic_register(unsigned long hpa) 851{ 852 struct iosapic_info *isi = NULL; 853 struct irt_entry *irte = irt_cell; 854 struct vector_info *vip; 855 int cnt; /* track how many entries we've looked at */ 856 857 /* 858 * Astro based platforms can only support PCI OLARD if they implement 859 * PAT PDC. Legacy PDC omits LBAs with no PCI devices from the IRT. 860 * Search the IRT and ignore iosapic's which aren't in the IRT. 861 */ 862 for (cnt=0; cnt < irt_num_entry; cnt++, irte++) { 863 WARN_ON(IRT_IOSAPIC_TYPE != irte->entry_type); 864 if (COMPARE_IRTE_ADDR(irte, hpa)) 865 break; 866 } 867 868 if (cnt >= irt_num_entry) { 869 DBG("iosapic_register() ignoring 0x%lx (NOT FOUND)\n", hpa); 870 return NULL; 871 } 872 873 isi = kzalloc(sizeof(struct iosapic_info), GFP_KERNEL); 874 if (!isi) { 875 BUG(); 876 return NULL; 877 } 878 879 isi->addr = ioremap_nocache(hpa, 4096); 880 isi->isi_hpa = hpa; 881 isi->isi_version = iosapic_rd_version(isi); 882 isi->isi_num_vectors = IOSAPIC_IRDT_MAX_ENTRY(isi->isi_version) + 1; 883 884 vip = isi->isi_vector = (struct vector_info *) 885 kzalloc(sizeof(struct vector_info) * isi->isi_num_vectors, GFP_KERNEL); 886 if (vip == NULL) { 887 kfree(isi); 888 return NULL; 889 } 890 891 for (cnt=0; cnt < isi->isi_num_vectors; cnt++, vip++) { 892 vip->irqline = (unsigned char) cnt; 893 vip->iosapic = isi; 894 } 895 return isi; 896} 897 898 899#ifdef DEBUG_IOSAPIC 900 901static void 902iosapic_prt_irt(void *irt, long num_entry) 903{ 904 unsigned int i, *irp = (unsigned int *) irt; 905 906 907 printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry); 908 909 for (i=0; i<num_entry; i++, irp += 4) { 910 printk(KERN_DEBUG "%p : %2d %.8x %.8x %.8x %.8x\n", 911 irp, i, irp[0], irp[1], irp[2], irp[3]); 912 } 913} 914 915 916static void 917iosapic_prt_vi(struct vector_info *vi) 918{ 919 printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi); 920 printk(KERN_DEBUG "\t\tstatus: %.4x\n", vi->status); 921 printk(KERN_DEBUG "\t\ttxn_irq: %d\n", vi->txn_irq); 922 printk(KERN_DEBUG "\t\ttxn_addr: %lx\n", vi->txn_addr); 923 printk(KERN_DEBUG "\t\ttxn_data: %lx\n", vi->txn_data); 924 printk(KERN_DEBUG "\t\teoi_addr: %p\n", vi->eoi_addr); 925 printk(KERN_DEBUG "\t\teoi_data: %x\n", vi->eoi_data); 926} 927 928 929static void 930iosapic_prt_isi(struct iosapic_info *isi) 931{ 932 printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi); 933 printk(KERN_DEBUG "\t\tisi_hpa: %lx\n", isi->isi_hpa); 934 printk(KERN_DEBUG "\t\tisi_status: %x\n", isi->isi_status); 935 printk(KERN_DEBUG "\t\tisi_version: %x\n", isi->isi_version); 936 printk(KERN_DEBUG "\t\tisi_vector: %p\n", isi->isi_vector); 937} 938#endif /* DEBUG_IOSAPIC */ 939