1/****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 22 * USA 23 * 24 * The full GNU General Public License is included in this distribution 25 * in the file called LICENSE.GPL. 26 * 27 * Contact Information: 28 * Intel Linux Wireless <ilw@linux.intel.com> 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 30 * 31 * BSD LICENSE 32 * 33 * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 40 * * Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * * Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in 44 * the documentation and/or other materials provided with the 45 * distribution. 46 * * Neither the name Intel Corporation nor the names of its 47 * contributors may be used to endorse or promote products derived 48 * from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 *****************************************************************************/ 63/* 64 * Please use this file (iwl-3945-hw.h) only for hardware-related definitions. 65 * Please use iwl-3945-commands.h for uCode API definitions. 66 * Please use iwl-3945.h for driver implementation definitions. 67 */ 68 69#ifndef __iwl_3945_hw__ 70#define __iwl_3945_hw__ 71 72#include "iwl-eeprom.h" 73 74/* RSSI to dBm */ 75#define IWL39_RSSI_OFFSET 95 76 77#define IWL_DEFAULT_TX_POWER 0x0F 78 79/* 80 * EEPROM related constants, enums, and structures. 81 */ 82#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) 83 84/* 85 * Mapping of a Tx power level, at factory calibration temperature, 86 * to a radio/DSP gain table index. 87 * One for each of 5 "sample" power levels in each band. 88 * v_det is measured at the factory, using the 3945's built-in power amplifier 89 * (PA) output voltage detector. This same detector is used during Tx of 90 * long packets in normal operation to provide feedback as to proper output 91 * level. 92 * Data copied from EEPROM. 93 * DO NOT ALTER THIS STRUCTURE!!! 94 */ 95struct iwl3945_eeprom_txpower_sample { 96 u8 gain_index; /* index into power (gain) setup table ... */ 97 s8 power; /* ... for this pwr level for this chnl group */ 98 u16 v_det; /* PA output voltage */ 99} __packed; 100 101/* 102 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes. 103 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). 104 * Tx power setup code interpolates between the 5 "sample" power levels 105 * to determine the nominal setup for a requested power level. 106 * Data copied from EEPROM. 107 * DO NOT ALTER THIS STRUCTURE!!! 108 */ 109struct iwl3945_eeprom_txpower_group { 110 struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ 111 s32 a, b, c, d, e; /* coefficients for voltage->power 112 * formula (signed) */ 113 s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on 114 * frequency (signed) */ 115 s8 saturation_power; /* highest power possible by h/w in this 116 * band */ 117 u8 group_channel; /* "representative" channel # in this band */ 118 s16 temperature; /* h/w temperature at factory calib this band 119 * (signed) */ 120} __packed; 121 122/* 123 * Temperature-based Tx-power compensation data, not band-specific. 124 * These coefficients are use to modify a/b/c/d/e coeffs based on 125 * difference between current temperature and factory calib temperature. 126 * Data copied from EEPROM. 127 */ 128struct iwl3945_eeprom_temperature_corr { 129 u32 Ta; 130 u32 Tb; 131 u32 Tc; 132 u32 Td; 133 u32 Te; 134} __packed; 135 136/* 137 * EEPROM map 138 */ 139struct iwl3945_eeprom { 140 u8 reserved0[16]; 141 u16 device_id; /* abs.ofs: 16 */ 142 u8 reserved1[2]; 143 u16 pmc; /* abs.ofs: 20 */ 144 u8 reserved2[20]; 145 u8 mac_address[6]; /* abs.ofs: 42 */ 146 u8 reserved3[58]; 147 u16 board_revision; /* abs.ofs: 106 */ 148 u8 reserved4[11]; 149 u8 board_pba_number[9]; /* abs.ofs: 119 */ 150 u8 reserved5[8]; 151 u16 version; /* abs.ofs: 136 */ 152 u8 sku_cap; /* abs.ofs: 138 */ 153 u8 leds_mode; /* abs.ofs: 139 */ 154 u16 oem_mode; 155 u16 wowlan_mode; /* abs.ofs: 142 */ 156 u16 leds_time_interval; /* abs.ofs: 144 */ 157 u8 leds_off_time; /* abs.ofs: 146 */ 158 u8 leds_on_time; /* abs.ofs: 147 */ 159 u8 almgor_m_version; /* abs.ofs: 148 */ 160 u8 antenna_switch_type; /* abs.ofs: 149 */ 161 u8 reserved6[42]; 162 u8 sku_id[4]; /* abs.ofs: 192 */ 163 164/* 165 * Per-channel regulatory data. 166 * 167 * Each channel that *might* be supported by 3945 or 4965 has a fixed location 168 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory 169 * txpower (MSB). 170 * 171 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz) 172 * channels (only for 4965, not supported by 3945) appear later in the EEPROM. 173 * 174 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 175 */ 176 u16 band_1_count; /* abs.ofs: 196 */ 177 struct iwl_eeprom_channel band_1_channels[14]; /* abs.ofs: 198 */ 178 179/* 180 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, 181 * 5.0 GHz channels 7, 8, 11, 12, 16 182 * (4915-5080MHz) (none of these is ever supported) 183 */ 184 u16 band_2_count; /* abs.ofs: 226 */ 185 struct iwl_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ 186 187/* 188 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 189 * (5170-5320MHz) 190 */ 191 u16 band_3_count; /* abs.ofs: 254 */ 192 struct iwl_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ 193 194/* 195 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 196 * (5500-5700MHz) 197 */ 198 u16 band_4_count; /* abs.ofs: 280 */ 199 struct iwl_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ 200 201/* 202 * 5.7 GHz channels 145, 149, 153, 157, 161, 165 203 * (5725-5825MHz) 204 */ 205 u16 band_5_count; /* abs.ofs: 304 */ 206 struct iwl_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ 207 208 u8 reserved9[194]; 209 210/* 211 * 3945 Txpower calibration data. 212 */ 213#define IWL_NUM_TX_CALIB_GROUPS 5 214 struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS]; 215/* abs.ofs: 512 */ 216 struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ 217 u8 reserved16[172]; /* fill out to full 1024 byte block */ 218} __packed; 219 220#define IWL3945_EEPROM_IMG_SIZE 1024 221 222/* End of EEPROM */ 223 224#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ 225#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ 226 227/* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */ 228#define IWL39_NUM_QUEUES 5 229 230#define IWL_DEFAULT_TX_RETRY 15 231 232/*********************************************/ 233 234#define RFD_SIZE 4 235#define NUM_TFD_CHUNKS 4 236 237#define RX_QUEUE_SIZE 256 238#define RX_QUEUE_MASK 255 239#define RX_QUEUE_SIZE_LOG 8 240 241#define U32_PAD(n) ((4-(n))&0x3) 242 243#define TFD_CTL_COUNT_SET(n) (n << 24) 244#define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7) 245#define TFD_CTL_PAD_SET(n) (n << 28) 246#define TFD_CTL_PAD_GET(ctl) (ctl >> 28) 247 248/* Sizes and addresses for instruction and data memory (SRAM) in 249 * 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ 250#define IWL39_RTC_INST_LOWER_BOUND (0x000000) 251#define IWL39_RTC_INST_UPPER_BOUND (0x014000) 252 253#define IWL39_RTC_DATA_LOWER_BOUND (0x800000) 254#define IWL39_RTC_DATA_UPPER_BOUND (0x808000) 255 256#define IWL39_RTC_INST_SIZE (IWL39_RTC_INST_UPPER_BOUND - \ 257 IWL39_RTC_INST_LOWER_BOUND) 258#define IWL39_RTC_DATA_SIZE (IWL39_RTC_DATA_UPPER_BOUND - \ 259 IWL39_RTC_DATA_LOWER_BOUND) 260 261#define IWL39_MAX_INST_SIZE IWL39_RTC_INST_SIZE 262#define IWL39_MAX_DATA_SIZE IWL39_RTC_DATA_SIZE 263 264/* Size of uCode instruction memory in bootstrap state machine */ 265#define IWL39_MAX_BSM_SIZE IWL39_RTC_INST_SIZE 266 267static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr) 268{ 269 return (addr >= IWL39_RTC_DATA_LOWER_BOUND) && 270 (addr < IWL39_RTC_DATA_UPPER_BOUND); 271} 272 273/* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE 274 * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */ 275struct iwl3945_shared { 276 __le32 tx_base_ptr[8]; 277} __packed; 278 279static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags) 280{ 281 return le16_to_cpu(rate_n_flags) & 0xFF; 282} 283 284static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags) 285{ 286 return le16_to_cpu(rate_n_flags); 287} 288 289static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags) 290{ 291 return cpu_to_le16((u16)rate|flags); 292} 293#endif 294