1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef MAC_H 18#define MAC_H 19 20#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \ 21 MS(ads->ds_rxstatus0, AR_RxRate) : \ 22 (ads->ds_rxstatus3 >> 2) & 0xFF) 23 24#define set11nTries(_series, _index) \ 25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 26 27#define set11nRate(_series, _index) \ 28 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 29 30#define set11nPktDurRTSCTS(_series, _index) \ 31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ 32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ 33 AR_RTSCTSQual##_index : 0)) 34 35#define set11nRateFlags(_series, _index) \ 36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 37 AR_2040_##_index : 0) \ 38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 39 AR_GI##_index : 0) \ 40 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \ 41 AR_STBC##_index : 0) \ 42 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 43 44#define CCK_SIFS_TIME 10 45#define CCK_PREAMBLE_BITS 144 46#define CCK_PLCP_BITS 48 47 48#define OFDM_SIFS_TIME 16 49#define OFDM_PREAMBLE_TIME 20 50#define OFDM_PLCP_BITS 22 51#define OFDM_SYMBOL_TIME 4 52 53#define OFDM_SIFS_TIME_HALF 32 54#define OFDM_PREAMBLE_TIME_HALF 40 55#define OFDM_PLCP_BITS_HALF 22 56#define OFDM_SYMBOL_TIME_HALF 8 57 58#define OFDM_SIFS_TIME_QUARTER 64 59#define OFDM_PREAMBLE_TIME_QUARTER 80 60#define OFDM_PLCP_BITS_QUARTER 22 61#define OFDM_SYMBOL_TIME_QUARTER 16 62 63#define INIT_AIFS 2 64#define INIT_CWMIN 15 65#define INIT_CWMIN_11B 31 66#define INIT_CWMAX 1023 67#define INIT_SH_RETRY 10 68#define INIT_LG_RETRY 10 69#define INIT_SSH_RETRY 32 70#define INIT_SLG_RETRY 32 71 72#define ATH9K_SLOT_TIME_6 6 73#define ATH9K_SLOT_TIME_9 9 74#define ATH9K_SLOT_TIME_20 20 75 76#define ATH9K_TXERR_XRETRY 0x01 77#define ATH9K_TXERR_FILT 0x02 78#define ATH9K_TXERR_FIFO 0x04 79#define ATH9K_TXERR_XTXOP 0x08 80#define ATH9K_TXERR_TIMER_EXPIRED 0x10 81#define ATH9K_TX_ACKED 0x20 82#define ATH9K_TXERR_MASK \ 83 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \ 84 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED) 85 86#define ATH9K_TX_BA 0x01 87#define ATH9K_TX_PWRMGMT 0x02 88#define ATH9K_TX_DESC_CFG_ERR 0x04 89#define ATH9K_TX_DATA_UNDERRUN 0x08 90#define ATH9K_TX_DELIM_UNDERRUN 0x10 91#define ATH9K_TX_SW_FILTERED 0x80 92 93/* 64 bytes */ 94#define MIN_TX_FIFO_THRESHOLD 0x1 95 96#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 97 98struct ath_tx_status { 99 u32 ts_tstamp; 100 u16 ts_seqnum; 101 u8 ts_status; 102 u8 ts_ratecode; 103 u8 ts_rateindex; 104 int8_t ts_rssi; 105 u8 ts_shortretry; 106 u8 ts_longretry; 107 u8 ts_virtcol; 108 u8 ts_antenna; 109 u8 ts_flags; 110 int8_t ts_rssi_ctl0; 111 int8_t ts_rssi_ctl1; 112 int8_t ts_rssi_ctl2; 113 int8_t ts_rssi_ext0; 114 int8_t ts_rssi_ext1; 115 int8_t ts_rssi_ext2; 116 u8 qid; 117 u16 desc_id; 118 u8 tid; 119 u8 pad[2]; 120 u32 ba_low; 121 u32 ba_high; 122 u32 evm0; 123 u32 evm1; 124 u32 evm2; 125}; 126 127struct ath_rx_status { 128 u32 rs_tstamp; 129 u16 rs_datalen; 130 u8 rs_status; 131 u8 rs_phyerr; 132 int8_t rs_rssi; 133 u8 rs_keyix; 134 u8 rs_rate; 135 u8 rs_antenna; 136 u8 rs_more; 137 int8_t rs_rssi_ctl0; 138 int8_t rs_rssi_ctl1; 139 int8_t rs_rssi_ctl2; 140 int8_t rs_rssi_ext0; 141 int8_t rs_rssi_ext1; 142 int8_t rs_rssi_ext2; 143 u8 rs_isaggr; 144 u8 rs_moreaggr; 145 u8 rs_num_delims; 146 u8 rs_flags; 147 u32 evm0; 148 u32 evm1; 149 u32 evm2; 150 u32 evm3; 151 u32 evm4; 152}; 153 154struct ath_htc_rx_status { 155 __be64 rs_tstamp; 156 __be16 rs_datalen; 157 u8 rs_status; 158 u8 rs_phyerr; 159 int8_t rs_rssi; 160 int8_t rs_rssi_ctl0; 161 int8_t rs_rssi_ctl1; 162 int8_t rs_rssi_ctl2; 163 int8_t rs_rssi_ext0; 164 int8_t rs_rssi_ext1; 165 int8_t rs_rssi_ext2; 166 u8 rs_keyix; 167 u8 rs_rate; 168 u8 rs_antenna; 169 u8 rs_more; 170 u8 rs_isaggr; 171 u8 rs_moreaggr; 172 u8 rs_num_delims; 173 u8 rs_flags; 174 u8 rs_dummy; 175 __be32 evm0; 176 __be32 evm1; 177 __be32 evm2; 178}; 179 180#define ATH9K_RXERR_CRC 0x01 181#define ATH9K_RXERR_PHY 0x02 182#define ATH9K_RXERR_FIFO 0x04 183#define ATH9K_RXERR_DECRYPT 0x08 184#define ATH9K_RXERR_MIC 0x10 185 186#define ATH9K_RX_MORE 0x01 187#define ATH9K_RX_MORE_AGGR 0x02 188#define ATH9K_RX_GI 0x04 189#define ATH9K_RX_2040 0x08 190#define ATH9K_RX_DELIM_CRC_PRE 0x10 191#define ATH9K_RX_DELIM_CRC_POST 0x20 192#define ATH9K_RX_DECRYPT_BUSY 0x40 193 194#define ATH9K_RXKEYIX_INVALID ((u8)-1) 195#define ATH9K_TXKEYIX_INVALID ((u32)-1) 196 197enum ath9k_phyerr { 198 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 199 ATH9K_PHYERR_TIMING = 1, /* Timing error */ 200 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */ 201 ATH9K_PHYERR_RATE = 3, /* Illegal rate */ 202 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */ 203 ATH9K_PHYERR_RADAR = 5, /* Radar detect */ 204 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */ 205 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */ 206 207 ATH9K_PHYERR_OFDM_TIMING = 17, 208 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18, 209 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19, 210 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20, 211 ATH9K_PHYERR_OFDM_POWER_DROP = 21, 212 ATH9K_PHYERR_OFDM_SERVICE = 22, 213 ATH9K_PHYERR_OFDM_RESTART = 23, 214 ATH9K_PHYERR_FALSE_RADAR_EXT = 24, 215 216 ATH9K_PHYERR_CCK_TIMING = 25, 217 ATH9K_PHYERR_CCK_HEADER_CRC = 26, 218 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27, 219 ATH9K_PHYERR_CCK_SERVICE = 30, 220 ATH9K_PHYERR_CCK_RESTART = 31, 221 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32, 222 ATH9K_PHYERR_CCK_POWER_DROP = 33, 223 224 ATH9K_PHYERR_HT_CRC_ERROR = 34, 225 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35, 226 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36, 227 228 ATH9K_PHYERR_MAX = 37, 229}; 230 231struct ath_desc { 232 u32 ds_link; 233 u32 ds_data; 234 u32 ds_ctl0; 235 u32 ds_ctl1; 236 u32 ds_hw[20]; 237 void *ds_vdata; 238} __packed; 239 240#define ATH9K_TXDESC_CLRDMASK 0x0001 241#define ATH9K_TXDESC_NOACK 0x0002 242#define ATH9K_TXDESC_RTSENA 0x0004 243#define ATH9K_TXDESC_CTSENA 0x0008 244/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for 245 * the descriptor its marked on. We take a tx interrupt to reap 246 * descriptors when the h/w hits an EOL condition or 247 * when the descriptor is specifically marked to generate 248 * an interrupt with this flag. Descriptors should be 249 * marked periodically to insure timely replenishing of the 250 * supply needed for sending frames. Defering interrupts 251 * reduces system load and potentially allows more concurrent 252 * work to be done but if done to aggressively can cause 253 * senders to backup. When the hardware queue is left too 254 * large rate control information may also be too out of 255 * date. An Alternative for this is TX interrupt mitigation 256 * but this needs more testing. */ 257#define ATH9K_TXDESC_INTREQ 0x0010 258#define ATH9K_TXDESC_VEOL 0x0020 259#define ATH9K_TXDESC_EXT_ONLY 0x0040 260#define ATH9K_TXDESC_EXT_AND_CTL 0x0080 261#define ATH9K_TXDESC_VMF 0x0100 262#define ATH9K_TXDESC_FRAG_IS_ON 0x0200 263#define ATH9K_TXDESC_LOWRXCHAIN 0x0400 264#define ATH9K_TXDESC_LDPC 0x00010000 265 266#define ATH9K_RXDESC_INTREQ 0x0020 267 268struct ar5416_desc { 269 u32 ds_link; 270 u32 ds_data; 271 u32 ds_ctl0; 272 u32 ds_ctl1; 273 union { 274 struct { 275 u32 ctl2; 276 u32 ctl3; 277 u32 ctl4; 278 u32 ctl5; 279 u32 ctl6; 280 u32 ctl7; 281 u32 ctl8; 282 u32 ctl9; 283 u32 ctl10; 284 u32 ctl11; 285 u32 status0; 286 u32 status1; 287 u32 status2; 288 u32 status3; 289 u32 status4; 290 u32 status5; 291 u32 status6; 292 u32 status7; 293 u32 status8; 294 u32 status9; 295 } tx; 296 struct { 297 u32 status0; 298 u32 status1; 299 u32 status2; 300 u32 status3; 301 u32 status4; 302 u32 status5; 303 u32 status6; 304 u32 status7; 305 u32 status8; 306 } rx; 307 } u; 308} __packed; 309 310#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) 311#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) 312 313#define ds_ctl2 u.tx.ctl2 314#define ds_ctl3 u.tx.ctl3 315#define ds_ctl4 u.tx.ctl4 316#define ds_ctl5 u.tx.ctl5 317#define ds_ctl6 u.tx.ctl6 318#define ds_ctl7 u.tx.ctl7 319#define ds_ctl8 u.tx.ctl8 320#define ds_ctl9 u.tx.ctl9 321#define ds_ctl10 u.tx.ctl10 322#define ds_ctl11 u.tx.ctl11 323 324#define ds_txstatus0 u.tx.status0 325#define ds_txstatus1 u.tx.status1 326#define ds_txstatus2 u.tx.status2 327#define ds_txstatus3 u.tx.status3 328#define ds_txstatus4 u.tx.status4 329#define ds_txstatus5 u.tx.status5 330#define ds_txstatus6 u.tx.status6 331#define ds_txstatus7 u.tx.status7 332#define ds_txstatus8 u.tx.status8 333#define ds_txstatus9 u.tx.status9 334 335#define ds_rxstatus0 u.rx.status0 336#define ds_rxstatus1 u.rx.status1 337#define ds_rxstatus2 u.rx.status2 338#define ds_rxstatus3 u.rx.status3 339#define ds_rxstatus4 u.rx.status4 340#define ds_rxstatus5 u.rx.status5 341#define ds_rxstatus6 u.rx.status6 342#define ds_rxstatus7 u.rx.status7 343#define ds_rxstatus8 u.rx.status8 344 345#define AR_FrameLen 0x00000fff 346#define AR_VirtMoreFrag 0x00001000 347#define AR_TxCtlRsvd00 0x0000e000 348#define AR_XmitPower 0x003f0000 349#define AR_XmitPower_S 16 350#define AR_RTSEnable 0x00400000 351#define AR_VEOL 0x00800000 352#define AR_ClrDestMask 0x01000000 353#define AR_TxCtlRsvd01 0x1e000000 354#define AR_TxIntrReq 0x20000000 355#define AR_DestIdxValid 0x40000000 356#define AR_CTSEnable 0x80000000 357 358#define AR_TxMore 0x00001000 359#define AR_DestIdx 0x000fe000 360#define AR_DestIdx_S 13 361#define AR_FrameType 0x00f00000 362#define AR_FrameType_S 20 363#define AR_NoAck 0x01000000 364#define AR_InsertTS 0x02000000 365#define AR_CorruptFCS 0x04000000 366#define AR_ExtOnly 0x08000000 367#define AR_ExtAndCtl 0x10000000 368#define AR_MoreAggr 0x20000000 369#define AR_IsAggr 0x40000000 370 371#define AR_BurstDur 0x00007fff 372#define AR_BurstDur_S 0 373#define AR_DurUpdateEna 0x00008000 374#define AR_XmitDataTries0 0x000f0000 375#define AR_XmitDataTries0_S 16 376#define AR_XmitDataTries1 0x00f00000 377#define AR_XmitDataTries1_S 20 378#define AR_XmitDataTries2 0x0f000000 379#define AR_XmitDataTries2_S 24 380#define AR_XmitDataTries3 0xf0000000 381#define AR_XmitDataTries3_S 28 382 383#define AR_XmitRate0 0x000000ff 384#define AR_XmitRate0_S 0 385#define AR_XmitRate1 0x0000ff00 386#define AR_XmitRate1_S 8 387#define AR_XmitRate2 0x00ff0000 388#define AR_XmitRate2_S 16 389#define AR_XmitRate3 0xff000000 390#define AR_XmitRate3_S 24 391 392#define AR_PacketDur0 0x00007fff 393#define AR_PacketDur0_S 0 394#define AR_RTSCTSQual0 0x00008000 395#define AR_PacketDur1 0x7fff0000 396#define AR_PacketDur1_S 16 397#define AR_RTSCTSQual1 0x80000000 398 399#define AR_PacketDur2 0x00007fff 400#define AR_PacketDur2_S 0 401#define AR_RTSCTSQual2 0x00008000 402#define AR_PacketDur3 0x7fff0000 403#define AR_PacketDur3_S 16 404#define AR_RTSCTSQual3 0x80000000 405 406#define AR_AggrLen 0x0000ffff 407#define AR_AggrLen_S 0 408#define AR_TxCtlRsvd60 0x00030000 409#define AR_PadDelim 0x03fc0000 410#define AR_PadDelim_S 18 411#define AR_EncrType 0x0c000000 412#define AR_EncrType_S 26 413#define AR_TxCtlRsvd61 0xf0000000 414#define AR_LDPC 0x80000000 415 416#define AR_2040_0 0x00000001 417#define AR_GI0 0x00000002 418#define AR_ChainSel0 0x0000001c 419#define AR_ChainSel0_S 2 420#define AR_2040_1 0x00000020 421#define AR_GI1 0x00000040 422#define AR_ChainSel1 0x00000380 423#define AR_ChainSel1_S 7 424#define AR_2040_2 0x00000400 425#define AR_GI2 0x00000800 426#define AR_ChainSel2 0x00007000 427#define AR_ChainSel2_S 12 428#define AR_2040_3 0x00008000 429#define AR_GI3 0x00010000 430#define AR_ChainSel3 0x000e0000 431#define AR_ChainSel3_S 17 432#define AR_RTSCTSRate 0x0ff00000 433#define AR_RTSCTSRate_S 20 434#define AR_STBC0 0x10000000 435#define AR_STBC1 0x20000000 436#define AR_STBC2 0x40000000 437#define AR_STBC3 0x80000000 438 439#define AR_TxRSSIAnt00 0x000000ff 440#define AR_TxRSSIAnt00_S 0 441#define AR_TxRSSIAnt01 0x0000ff00 442#define AR_TxRSSIAnt01_S 8 443#define AR_TxRSSIAnt02 0x00ff0000 444#define AR_TxRSSIAnt02_S 16 445#define AR_TxStatusRsvd00 0x3f000000 446#define AR_TxBaStatus 0x40000000 447#define AR_TxStatusRsvd01 0x80000000 448 449/* 450 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was 451 * transmitted successfully. If clear, no ACK or BA was received to indicate 452 * successful transmission when we were expecting an ACK or BA. 453 */ 454#define AR_FrmXmitOK 0x00000001 455#define AR_ExcessiveRetries 0x00000002 456#define AR_FIFOUnderrun 0x00000004 457#define AR_Filtered 0x00000008 458#define AR_RTSFailCnt 0x000000f0 459#define AR_RTSFailCnt_S 4 460#define AR_DataFailCnt 0x00000f00 461#define AR_DataFailCnt_S 8 462#define AR_VirtRetryCnt 0x0000f000 463#define AR_VirtRetryCnt_S 12 464#define AR_TxDelimUnderrun 0x00010000 465#define AR_TxDataUnderrun 0x00020000 466#define AR_DescCfgErr 0x00040000 467#define AR_TxTimerExpired 0x00080000 468#define AR_TxStatusRsvd10 0xfff00000 469 470#define AR_SendTimestamp ds_txstatus2 471#define AR_BaBitmapLow ds_txstatus3 472#define AR_BaBitmapHigh ds_txstatus4 473 474#define AR_TxRSSIAnt10 0x000000ff 475#define AR_TxRSSIAnt10_S 0 476#define AR_TxRSSIAnt11 0x0000ff00 477#define AR_TxRSSIAnt11_S 8 478#define AR_TxRSSIAnt12 0x00ff0000 479#define AR_TxRSSIAnt12_S 16 480#define AR_TxRSSICombined 0xff000000 481#define AR_TxRSSICombined_S 24 482 483#define AR_TxTid 0xf0000000 484#define AR_TxTid_S 28 485 486#define AR_TxEVM0 ds_txstatus5 487#define AR_TxEVM1 ds_txstatus6 488#define AR_TxEVM2 ds_txstatus7 489 490#define AR_TxDone 0x00000001 491#define AR_SeqNum 0x00001ffe 492#define AR_SeqNum_S 1 493#define AR_TxStatusRsvd80 0x0001e000 494#define AR_TxOpExceeded 0x00020000 495#define AR_TxStatusRsvd81 0x001c0000 496#define AR_FinalTxIdx 0x00600000 497#define AR_FinalTxIdx_S 21 498#define AR_TxStatusRsvd82 0x01800000 499#define AR_PowerMgmt 0x02000000 500#define AR_TxStatusRsvd83 0xfc000000 501 502#define AR_RxCTLRsvd00 0xffffffff 503 504#define AR_RxCtlRsvd00 0x00001000 505#define AR_RxIntrReq 0x00002000 506#define AR_RxCtlRsvd01 0xffffc000 507 508#define AR_RxRSSIAnt00 0x000000ff 509#define AR_RxRSSIAnt00_S 0 510#define AR_RxRSSIAnt01 0x0000ff00 511#define AR_RxRSSIAnt01_S 8 512#define AR_RxRSSIAnt02 0x00ff0000 513#define AR_RxRSSIAnt02_S 16 514#define AR_RxRate 0xff000000 515#define AR_RxRate_S 24 516#define AR_RxStatusRsvd00 0xff000000 517 518#define AR_DataLen 0x00000fff 519#define AR_RxMore 0x00001000 520#define AR_NumDelim 0x003fc000 521#define AR_NumDelim_S 14 522#define AR_RxStatusRsvd10 0xff800000 523 524#define AR_RcvTimestamp ds_rxstatus2 525 526#define AR_GI 0x00000001 527#define AR_2040 0x00000002 528#define AR_Parallel40 0x00000004 529#define AR_Parallel40_S 2 530#define AR_RxStatusRsvd30 0x000000f8 531#define AR_RxAntenna 0xffffff00 532#define AR_RxAntenna_S 8 533 534#define AR_RxRSSIAnt10 0x000000ff 535#define AR_RxRSSIAnt10_S 0 536#define AR_RxRSSIAnt11 0x0000ff00 537#define AR_RxRSSIAnt11_S 8 538#define AR_RxRSSIAnt12 0x00ff0000 539#define AR_RxRSSIAnt12_S 16 540#define AR_RxRSSICombined 0xff000000 541#define AR_RxRSSICombined_S 24 542 543#define AR_RxEVM0 ds_rxstatus4 544#define AR_RxEVM1 ds_rxstatus5 545#define AR_RxEVM2 ds_rxstatus6 546 547#define AR_RxDone 0x00000001 548#define AR_RxFrameOK 0x00000002 549#define AR_CRCErr 0x00000004 550#define AR_DecryptCRCErr 0x00000008 551#define AR_PHYErr 0x00000010 552#define AR_MichaelErr 0x00000020 553#define AR_PreDelimCRCErr 0x00000040 554#define AR_RxStatusRsvd70 0x00000080 555#define AR_RxKeyIdxValid 0x00000100 556#define AR_KeyIdx 0x0000fe00 557#define AR_KeyIdx_S 9 558#define AR_PHYErrCode 0x0000ff00 559#define AR_PHYErrCode_S 8 560#define AR_RxMoreAggr 0x00010000 561#define AR_RxAggr 0x00020000 562#define AR_PostDelimCRCErr 0x00040000 563#define AR_RxStatusRsvd71 0x3ff80000 564#define AR_DecryptBusyErr 0x40000000 565#define AR_KeyMiss 0x80000000 566 567enum ath9k_tx_queue { 568 ATH9K_TX_QUEUE_INACTIVE = 0, 569 ATH9K_TX_QUEUE_DATA, 570 ATH9K_TX_QUEUE_BEACON, 571 ATH9K_TX_QUEUE_CAB, 572 ATH9K_TX_QUEUE_UAPSD, 573 ATH9K_TX_QUEUE_PSPOLL 574}; 575 576#define ATH9K_NUM_TX_QUEUES 10 577 578/* Used as a queue subtype instead of a WMM AC */ 579#define ATH9K_WME_UPSD 4 580 581enum ath9k_tx_queue_flags { 582 TXQ_FLAG_TXOKINT_ENABLE = 0x0001, 583 TXQ_FLAG_TXERRINT_ENABLE = 0x0001, 584 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, 585 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, 586 TXQ_FLAG_TXURNINT_ENABLE = 0x0008, 587 TXQ_FLAG_BACKOFF_DISABLE = 0x0010, 588 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, 589 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, 590 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, 591}; 592 593#define ATH9K_TXQ_USEDEFAULT ((u32) -1) 594#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 595 596#define ATH9K_DECOMP_MASK_SIZE 128 597#define ATH9K_READY_TIME_LO_BOUND 50 598#define ATH9K_READY_TIME_HI_BOUND 96 599 600enum ath9k_pkt_type { 601 ATH9K_PKT_TYPE_NORMAL = 0, 602 ATH9K_PKT_TYPE_ATIM, 603 ATH9K_PKT_TYPE_PSPOLL, 604 ATH9K_PKT_TYPE_BEACON, 605 ATH9K_PKT_TYPE_PROBE_RESP, 606 ATH9K_PKT_TYPE_CHIRP, 607 ATH9K_PKT_TYPE_GRP_POLL, 608}; 609 610struct ath9k_tx_queue_info { 611 u32 tqi_ver; 612 enum ath9k_tx_queue tqi_type; 613 int tqi_subtype; 614 enum ath9k_tx_queue_flags tqi_qflags; 615 u32 tqi_priority; 616 u32 tqi_aifs; 617 u32 tqi_cwmin; 618 u32 tqi_cwmax; 619 u16 tqi_shretry; 620 u16 tqi_lgretry; 621 u32 tqi_cbrPeriod; 622 u32 tqi_cbrOverflowLimit; 623 u32 tqi_burstTime; 624 u32 tqi_readyTime; 625 u32 tqi_physCompBuf; 626 u32 tqi_intFlags; 627}; 628 629enum ath9k_rx_filter { 630 ATH9K_RX_FILTER_UCAST = 0x00000001, 631 ATH9K_RX_FILTER_MCAST = 0x00000002, 632 ATH9K_RX_FILTER_BCAST = 0x00000004, 633 ATH9K_RX_FILTER_CONTROL = 0x00000008, 634 ATH9K_RX_FILTER_BEACON = 0x00000010, 635 ATH9K_RX_FILTER_PROM = 0x00000020, 636 ATH9K_RX_FILTER_PROBEREQ = 0x00000080, 637 ATH9K_RX_FILTER_PHYERR = 0x00000100, 638 ATH9K_RX_FILTER_MYBEACON = 0x00000200, 639 ATH9K_RX_FILTER_COMP_BAR = 0x00000400, 640 ATH9K_RX_FILTER_PSPOLL = 0x00004000, 641 ATH9K_RX_FILTER_PHYRADAR = 0x00002000, 642 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 643}; 644 645#define ATH9K_RATESERIES_RTS_CTS 0x0001 646#define ATH9K_RATESERIES_2040 0x0002 647#define ATH9K_RATESERIES_HALFGI 0x0004 648#define ATH9K_RATESERIES_STBC 0x0008 649 650struct ath9k_11n_rate_series { 651 u32 Tries; 652 u32 Rate; 653 u32 PktDuration; 654 u32 ChSel; 655 u32 RateFlags; 656}; 657 658struct ath9k_keyval { 659 u8 kv_type; 660 u8 kv_pad; 661 u16 kv_len; 662 u8 kv_val[16]; /* TK */ 663 u8 kv_mic[8]; /* Michael MIC key */ 664 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware 665 * supports both MIC keys in the same key cache entry; 666 * in that case, kv_mic is the RX key) */ 667}; 668 669enum ath9k_key_type { 670 ATH9K_KEY_TYPE_CLEAR, 671 ATH9K_KEY_TYPE_WEP, 672 ATH9K_KEY_TYPE_AES, 673 ATH9K_KEY_TYPE_TKIP, 674}; 675 676enum ath9k_cipher { 677 ATH9K_CIPHER_WEP = 0, 678 ATH9K_CIPHER_AES_OCB = 1, 679 ATH9K_CIPHER_AES_CCM = 2, 680 ATH9K_CIPHER_CKIP = 3, 681 ATH9K_CIPHER_TKIP = 4, 682 ATH9K_CIPHER_CLR = 5, 683 ATH9K_CIPHER_MIC = 127 684}; 685 686struct ath_hw; 687struct ath9k_channel; 688 689u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 690void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 691void ath9k_hw_txstart(struct ath_hw *ah, u32 q); 692void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds); 693u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); 694bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); 695bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q); 696void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); 697bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 698 const struct ath9k_tx_queue_info *qinfo); 699bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 700 struct ath9k_tx_queue_info *qinfo); 701int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 702 const struct ath9k_tx_queue_info *qinfo); 703bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); 704bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); 705int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 706 struct ath_rx_status *rs, u64 tsf); 707void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 708 u32 size, u32 flags); 709bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); 710void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 711void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning); 712void ath9k_hw_stoppcurecv(struct ath_hw *ah); 713void ath9k_hw_abortpcurecv(struct ath_hw *ah); 714bool ath9k_hw_stopdmarecv(struct ath_hw *ah); 715int ath9k_hw_beaconq_setup(struct ath_hw *ah); 716 717/* Interrupt Handling */ 718bool ath9k_hw_intrpend(struct ath_hw *ah); 719enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, 720 enum ath9k_int ints); 721 722void ar9002_hw_attach_mac_ops(struct ath_hw *ah); 723 724#endif /* MAC_H */ 725