1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "hw.h" 18 19static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 20{ 21 if (fbin == AR5416_BCHAN_UNUSED) 22 return fbin; 23 24 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 25} 26 27void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val) 28{ 29 REG_WRITE(ah, reg, val); 30 31 if (ah->config.analog_shiftreg) 32 udelay(100); 33} 34 35void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, 36 u32 shift, u32 val) 37{ 38 u32 regVal; 39 40 regVal = REG_READ(ah, reg) & ~mask; 41 regVal |= (val << shift) & mask; 42 43 REG_WRITE(ah, reg, regVal); 44 45 if (ah->config.analog_shiftreg) 46 udelay(100); 47} 48 49int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, 50 int16_t targetLeft, int16_t targetRight) 51{ 52 int16_t rv; 53 54 if (srcRight == srcLeft) { 55 rv = targetLeft; 56 } else { 57 rv = (int16_t) (((target - srcLeft) * targetRight + 58 (srcRight - target) * targetLeft) / 59 (srcRight - srcLeft)); 60 } 61 return rv; 62} 63 64bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 65 u16 *indexL, u16 *indexR) 66{ 67 u16 i; 68 69 if (target <= pList[0]) { 70 *indexL = *indexR = 0; 71 return true; 72 } 73 if (target >= pList[listSize - 1]) { 74 *indexL = *indexR = (u16) (listSize - 1); 75 return true; 76 } 77 78 for (i = 0; i < listSize - 1; i++) { 79 if (pList[i] == target) { 80 *indexL = *indexR = i; 81 return true; 82 } 83 if (target < pList[i + 1]) { 84 *indexL = i; 85 *indexR = (u16) (i + 1); 86 return false; 87 } 88 } 89 return false; 90} 91 92bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data) 93{ 94 return common->bus_ops->eeprom_read(common, off, data); 95} 96 97void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 98 u8 *pVpdList, u16 numIntercepts, 99 u8 *pRetVpdList) 100{ 101 u16 i, k; 102 u8 currPwr = pwrMin; 103 u16 idxL = 0, idxR = 0; 104 105 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { 106 ath9k_hw_get_lower_upper_index(currPwr, pPwrList, 107 numIntercepts, &(idxL), 108 &(idxR)); 109 if (idxR < 1) 110 idxR = 1; 111 if (idxL == numIntercepts - 1) 112 idxL = (u16) (numIntercepts - 2); 113 if (pPwrList[idxL] == pPwrList[idxR]) 114 k = pVpdList[idxL]; 115 else 116 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + 117 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / 118 (pPwrList[idxR] - pPwrList[idxL])); 119 pRetVpdList[i] = (u8) k; 120 currPwr += 2; 121 } 122} 123 124void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 125 struct ath9k_channel *chan, 126 struct cal_target_power_leg *powInfo, 127 u16 numChannels, 128 struct cal_target_power_leg *pNewPower, 129 u16 numRates, bool isExtTarget) 130{ 131 struct chan_centers centers; 132 u16 clo, chi; 133 int i; 134 int matchIndex = -1, lowIndex = -1; 135 u16 freq; 136 137 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 138 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center; 139 140 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, 141 IS_CHAN_2GHZ(chan))) { 142 matchIndex = 0; 143 } else { 144 for (i = 0; (i < numChannels) && 145 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 146 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, 147 IS_CHAN_2GHZ(chan))) { 148 matchIndex = i; 149 break; 150 } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, 151 IS_CHAN_2GHZ(chan)) && i > 0 && 152 freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, 153 IS_CHAN_2GHZ(chan))) { 154 lowIndex = i - 1; 155 break; 156 } 157 } 158 if ((matchIndex == -1) && (lowIndex == -1)) 159 matchIndex = i - 1; 160 } 161 162 if (matchIndex != -1) { 163 *pNewPower = powInfo[matchIndex]; 164 } else { 165 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, 166 IS_CHAN_2GHZ(chan)); 167 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, 168 IS_CHAN_2GHZ(chan)); 169 170 for (i = 0; i < numRates; i++) { 171 pNewPower->tPow2x[i] = 172 (u8)ath9k_hw_interpolate(freq, clo, chi, 173 powInfo[lowIndex].tPow2x[i], 174 powInfo[lowIndex + 1].tPow2x[i]); 175 } 176 } 177} 178 179void ath9k_hw_get_target_powers(struct ath_hw *ah, 180 struct ath9k_channel *chan, 181 struct cal_target_power_ht *powInfo, 182 u16 numChannels, 183 struct cal_target_power_ht *pNewPower, 184 u16 numRates, bool isHt40Target) 185{ 186 struct chan_centers centers; 187 u16 clo, chi; 188 int i; 189 int matchIndex = -1, lowIndex = -1; 190 u16 freq; 191 192 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 193 freq = isHt40Target ? centers.synth_center : centers.ctl_center; 194 195 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { 196 matchIndex = 0; 197 } else { 198 for (i = 0; (i < numChannels) && 199 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 200 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, 201 IS_CHAN_2GHZ(chan))) { 202 matchIndex = i; 203 break; 204 } else 205 if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, 206 IS_CHAN_2GHZ(chan)) && i > 0 && 207 freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, 208 IS_CHAN_2GHZ(chan))) { 209 lowIndex = i - 1; 210 break; 211 } 212 } 213 if ((matchIndex == -1) && (lowIndex == -1)) 214 matchIndex = i - 1; 215 } 216 217 if (matchIndex != -1) { 218 *pNewPower = powInfo[matchIndex]; 219 } else { 220 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, 221 IS_CHAN_2GHZ(chan)); 222 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, 223 IS_CHAN_2GHZ(chan)); 224 225 for (i = 0; i < numRates; i++) { 226 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq, 227 clo, chi, 228 powInfo[lowIndex].tPow2x[i], 229 powInfo[lowIndex + 1].tPow2x[i]); 230 } 231 } 232} 233 234u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 235 bool is2GHz, int num_band_edges) 236{ 237 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 238 int i; 239 240 for (i = 0; (i < num_band_edges) && 241 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 242 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { 243 twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl); 244 break; 245 } else if ((i > 0) && 246 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, 247 is2GHz))) { 248 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel, 249 is2GHz) < freq && 250 CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) { 251 twiceMaxEdgePower = 252 CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl); 253 } 254 break; 255 } 256 } 257 258 return twiceMaxEdgePower; 259} 260 261void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah) 262{ 263 struct ath_common *common = ath9k_hw_common(ah); 264 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 265 266 switch (ar5416_get_ntxchains(ah->txchainmask)) { 267 case 1: 268 break; 269 case 2: 270 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN; 271 break; 272 case 3: 273 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 274 break; 275 default: 276 ath_print(common, ATH_DBG_EEPROM, 277 "Invalid chainmask configuration\n"); 278 break; 279 } 280} 281 282int ath9k_hw_eeprom_init(struct ath_hw *ah) 283{ 284 int status; 285 286 if (AR_SREV_9300_20_OR_LATER(ah)) 287 ah->eep_ops = &eep_ar9300_ops; 288 else if (AR_SREV_9287(ah)) { 289 ah->eep_ops = &eep_ar9287_ops; 290 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) { 291 ah->eep_ops = &eep_4k_ops; 292 } else { 293 ah->eep_ops = &eep_def_ops; 294 } 295 296 if (!ah->eep_ops->fill_eeprom(ah)) 297 return -EIO; 298 299 status = ah->eep_ops->check_eeprom(ah); 300 301 return status; 302} 303