1/* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16#ifndef AR9002_PHY_H 17#define AR9002_PHY_H 18 19#define AR_PHY_TEST 0x9800 20#define PHY_AGC_CLR 0x10000000 21#define RFSILENT_BB 0x00002000 22 23#define AR_PHY_TURBO 0x9804 24#define AR_PHY_FC_TURBO_MODE 0x00000001 25#define AR_PHY_FC_TURBO_SHORT 0x00000002 26#define AR_PHY_FC_DYN2040_EN 0x00000004 27#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 28#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 29/* For 25 MHz channel spacing -- not used but supported by hw */ 30#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 31#define AR_PHY_FC_HT_EN 0x00000040 32#define AR_PHY_FC_SHORT_GI_40 0x00000080 33#define AR_PHY_FC_WALSH 0x00000100 34#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 35#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 36 37#define AR_PHY_TEST2 0x9808 38 39#define AR_PHY_TIMING2 0x9810 40#define AR_PHY_TIMING3 0x9814 41#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 42#define AR_PHY_TIMING3_DSC_MAN_S 17 43#define AR_PHY_TIMING3_DSC_EXP 0x0001E000 44#define AR_PHY_TIMING3_DSC_EXP_S 13 45 46#define AR_PHY_CHIP_ID_REV_0 0x80 47#define AR_PHY_CHIP_ID_REV_1 0x81 48#define AR_PHY_CHIP_ID_9160_REV_0 0xb0 49 50#define AR_PHY_ACTIVE 0x981C 51#define AR_PHY_ACTIVE_EN 0x00000001 52#define AR_PHY_ACTIVE_DIS 0x00000000 53 54#define AR_PHY_RF_CTL2 0x9824 55#define AR_PHY_TX_END_DATA_START 0x000000FF 56#define AR_PHY_TX_END_DATA_START_S 0 57#define AR_PHY_TX_END_PA_ON 0x0000FF00 58#define AR_PHY_TX_END_PA_ON_S 8 59 60#define AR_PHY_RF_CTL3 0x9828 61#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 62#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 63 64#define AR_PHY_ADC_CTL 0x982C 65#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 66#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 67#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 68#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 69#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 70#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 71#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 72 73#define AR_PHY_ADC_SERIAL_CTL 0x9830 74#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 75#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 76 77#define AR_PHY_RF_CTL4 0x9834 78#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 79#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 80#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 81#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 82#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 83#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 84#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 85#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 86 87#define AR_PHY_TSTDAC_CONST 0x983c 88 89#define AR_PHY_SETTLING 0x9844 90#define AR_PHY_SETTLING_SWITCH 0x00003F80 91#define AR_PHY_SETTLING_SWITCH_S 7 92 93#define AR_PHY_RXGAIN 0x9848 94#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 95#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 96#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 97#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 98#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 99#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 100#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 101#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 102 103#define AR_PHY_DESIRED_SZ 0x9850 104#define AR_PHY_DESIRED_SZ_ADC 0x000000FF 105#define AR_PHY_DESIRED_SZ_ADC_S 0 106#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 107#define AR_PHY_DESIRED_SZ_PGA_S 8 108#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 109#define AR_PHY_DESIRED_SZ_TOT_DES_S 20 110 111#define AR_PHY_FIND_SIG 0x9858 112#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 113#define AR_PHY_FIND_SIG_FIRSTEP_S 12 114#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 115#define AR_PHY_FIND_SIG_FIRPWR_S 18 116 117#define AR_PHY_FIND_SIG_LOW 0x9840 118#define AR_PHY_FIND_SIG_FIRSTEP_LOW 0x00000FC0L 119#define AR_PHY_FIND_SIG_FIRSTEP_LOW_S 6 120 121#define AR_PHY_AGC_CTL1 0x985C 122#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 123#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 124#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 125#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 126 127#define AR_PHY_CCA 0x9864 128#define AR_PHY_MINCCA_PWR 0x0FF80000 129#define AR_PHY_MINCCA_PWR_S 19 130#define AR_PHY_CCA_THRESH62 0x0007F000 131#define AR_PHY_CCA_THRESH62_S 12 132#define AR9280_PHY_MINCCA_PWR 0x1FF00000 133#define AR9280_PHY_MINCCA_PWR_S 20 134#define AR9280_PHY_CCA_THRESH62 0x000FF000 135#define AR9280_PHY_CCA_THRESH62_S 12 136 137#define AR_PHY_SFCORR_LOW 0x986C 138#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 139#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 140#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 141#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 142#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 143#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 144#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 145 146#define AR_PHY_SFCORR 0x9868 147#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 148#define AR_PHY_SFCORR_M2COUNT_THR_S 0 149#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 150#define AR_PHY_SFCORR_M1_THRESH_S 17 151#define AR_PHY_SFCORR_M2_THRESH 0x7F000000 152#define AR_PHY_SFCORR_M2_THRESH_S 24 153 154#define AR_PHY_SLEEP_CTR_CONTROL 0x9870 155#define AR_PHY_SLEEP_CTR_LIMIT 0x9874 156#define AR_PHY_SYNTH_CONTROL 0x9874 157#define AR_PHY_SLEEP_SCAL 0x9878 158 159#define AR_PHY_PLL_CTL 0x987c 160#define AR_PHY_PLL_CTL_40 0xaa 161#define AR_PHY_PLL_CTL_40_5413 0x04 162#define AR_PHY_PLL_CTL_44 0xab 163#define AR_PHY_PLL_CTL_44_2133 0xeb 164#define AR_PHY_PLL_CTL_40_2133 0xea 165 166#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */ 167#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1 168#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */ 169#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */ 170#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/ 171#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/ 172#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/ 173#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 174#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/ 175#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 176#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/ 177#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 178#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/ 179#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/ 180 181#define AR_PHY_RX_DELAY 0x9914 182#define AR_PHY_SEARCH_START_DELAY 0x9918 183#define AR_PHY_RX_DELAY_DELAY 0x00003FFF 184 185#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) 186#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F 187#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 188#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 189#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 190#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 191#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 192#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 193#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 194 195#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 196#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 197#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 198#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 199 200#define AR_PHY_TIMING5 0x9924 201#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 202#define AR_PHY_TIMING5_CYCPWR_THR1_S 1 203 204#define AR_PHY_POWER_TX_RATE1 0x9934 205#define AR_PHY_POWER_TX_RATE2 0x9938 206#define AR_PHY_POWER_TX_RATE_MAX 0x993c 207#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 208 209#define AR_PHY_FRAME_CTL 0x9944 210#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 211#define AR_PHY_FRAME_CTL_TX_CLIP_S 3 212 213#define AR_PHY_TXPWRADJ 0x994C 214#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 215#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 216#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 217#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 218 219#define AR_PHY_RADAR_EXT 0x9940 220#define AR_PHY_RADAR_EXT_ENA 0x00004000 221 222#define AR_PHY_RADAR_0 0x9954 223#define AR_PHY_RADAR_0_ENA 0x00000001 224#define AR_PHY_RADAR_0_FFT_ENA 0x80000000 225#define AR_PHY_RADAR_0_INBAND 0x0000003e 226#define AR_PHY_RADAR_0_INBAND_S 1 227#define AR_PHY_RADAR_0_PRSSI 0x00000FC0 228#define AR_PHY_RADAR_0_PRSSI_S 6 229#define AR_PHY_RADAR_0_HEIGHT 0x0003F000 230#define AR_PHY_RADAR_0_HEIGHT_S 12 231#define AR_PHY_RADAR_0_RRSSI 0x00FC0000 232#define AR_PHY_RADAR_0_RRSSI_S 18 233#define AR_PHY_RADAR_0_FIRPWR 0x7F000000 234#define AR_PHY_RADAR_0_FIRPWR_S 24 235 236#define AR_PHY_RADAR_1 0x9958 237#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 238#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 239#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 240#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 241#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 242#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 243#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 244#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 245#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 246#define AR_PHY_RADAR_1_MAXLEN 0x000000FF 247#define AR_PHY_RADAR_1_MAXLEN_S 0 248 249#define AR_PHY_SWITCH_CHAIN_0 0x9960 250#define AR_PHY_SWITCH_COM 0x9964 251 252#define AR_PHY_SIGMA_DELTA 0x996C 253#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 254#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 255#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 256#define AR_PHY_SIGMA_DELTA_FILT2_S 3 257#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 258#define AR_PHY_SIGMA_DELTA_FILT1_S 8 259#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 260#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 261 262#define AR_PHY_RESTART 0x9970 263#define AR_PHY_RESTART_DIV_GC 0x001C0000 264#define AR_PHY_RESTART_DIV_GC_S 18 265 266#define AR_PHY_RFBUS_REQ 0x997C 267#define AR_PHY_RFBUS_REQ_EN 0x00000001 268 269#define AR_PHY_TIMING7 0x9980 270#define AR_PHY_TIMING8 0x9984 271#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF 272#define AR_PHY_TIMING8_PILOT_MASK_2_S 0 273 274#define AR_PHY_BIN_MASK2_1 0x9988 275#define AR_PHY_BIN_MASK2_2 0x998c 276#define AR_PHY_BIN_MASK2_3 0x9990 277#define AR_PHY_BIN_MASK2_4 0x9994 278 279#define AR_PHY_BIN_MASK_1 0x9900 280#define AR_PHY_BIN_MASK_2 0x9904 281#define AR_PHY_BIN_MASK_3 0x9908 282 283#define AR_PHY_MASK_CTL 0x990c 284 285#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF 286#define AR_PHY_BIN_MASK2_4_MASK_4_S 0 287 288#define AR_PHY_TIMING9 0x9998 289#define AR_PHY_TIMING10 0x999c 290#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF 291#define AR_PHY_TIMING10_PILOT_MASK_2_S 0 292 293#define AR_PHY_TIMING11 0x99a0 294#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 295#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 296#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 297#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 298 299#define AR_PHY_RX_CHAINMASK 0x99a4 300#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 301#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 302#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 303 304#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 305#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000 306#define AR_PHY_9285_ANT_DIV_CTL 0x01000000 307#define AR_PHY_9285_ANT_DIV_CTL_S 24 308#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000 309#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25 310#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000 311#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27 312#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000 313#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 314#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 315#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 316#define AR_PHY_9285_ANT_DIV_LNA1 2 317#define AR_PHY_9285_ANT_DIV_LNA2 1 318#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3 319#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0 320#define AR_PHY_9285_ANT_DIV_GAINTB_0 0 321#define AR_PHY_9285_ANT_DIV_GAINTB_1 1 322 323#define AR_PHY_EXT_CCA0 0x99b8 324#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 325#define AR_PHY_EXT_CCA0_THRESH62_S 0 326 327#define AR_PHY_EXT_CCA 0x99bc 328#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 329#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 330#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 331#define AR_PHY_EXT_CCA_THRESH62_S 16 332#define AR_PHY_EXT_TIMING5_CYCPWR_THR1 0x0000FE00L 333#define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9 334 335#define AR_PHY_EXT_MINCCA_PWR 0xFF800000 336#define AR_PHY_EXT_MINCCA_PWR_S 23 337#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 338#define AR9280_PHY_EXT_MINCCA_PWR_S 16 339 340#define AR_PHY_SFCORR_EXT 0x99c0 341#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 342#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 343#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 344#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 345#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 346#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 347#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 348#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 349#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 350 351#define AR_PHY_HALFGI 0x99D0 352#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 353#define AR_PHY_HALFGI_DSC_MAN_S 4 354#define AR_PHY_HALFGI_DSC_EXP 0x0000000F 355#define AR_PHY_HALFGI_DSC_EXP_S 0 356 357#define AR_PHY_CHAN_INFO_MEMORY 0x99DC 358#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 359 360#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 361 362#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC 363#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000 364 365#define AR_PHY_M_SLEEP 0x99f0 366#define AR_PHY_REFCLKDLY 0x99f4 367#define AR_PHY_REFCLKPD 0x99f8 368 369#define AR_PHY_CALMODE 0x99f0 370 371#define AR_PHY_CALMODE_IQ 0x00000000 372#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 373#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 374#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 375 376#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 377#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 378#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 379#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 380 381#define AR_PHY_CURRENT_RSSI 0x9c1c 382#define AR9280_PHY_CURRENT_RSSI 0x9c3c 383 384#define AR_PHY_RFBUS_GRANT 0x9C20 385#define AR_PHY_RFBUS_GRANT_EN 0x00000001 386 387#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4 388#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 389 390#define AR_PHY_CHAN_INFO_GAIN 0x9CFC 391 392#define AR_PHY_MODE 0xA200 393#define AR_PHY_MODE_ASYNCFIFO 0x80 394#define AR_PHY_MODE_AR2133 0x08 395#define AR_PHY_MODE_AR5111 0x00 396#define AR_PHY_MODE_AR5112 0x08 397#define AR_PHY_MODE_DYNAMIC 0x04 398#define AR_PHY_MODE_RF2GHZ 0x02 399#define AR_PHY_MODE_RF5GHZ 0x00 400#define AR_PHY_MODE_CCK 0x01 401#define AR_PHY_MODE_OFDM 0x00 402#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100 403 404#define AR_PHY_CCK_TX_CTRL 0xA204 405#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 406#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C 407#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 408 409#define AR_PHY_CCK_DETECT 0xA208 410#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 411#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 412/* [12:6] settling time for antenna switch */ 413#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 414#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 415#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 416#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 417 418#define AR_PHY_GAIN_2GHZ 0xA20C 419#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 420#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 421#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 422#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 423#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 424#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 425 426#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 427#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 428#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 429#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 430#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 431#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 432#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F 433#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 434 435#define AR_PHY_CCK_RXCTRL4 0xA21C 436#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 437#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 438 439#define AR_PHY_DAG_CTRLCCK 0xA228 440#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 441#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 442#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 443 444#define AR_PHY_FORCE_CLKEN_CCK 0xA22C 445#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 446 447#define AR_PHY_POWER_TX_RATE3 0xA234 448#define AR_PHY_POWER_TX_RATE4 0xA238 449 450#define AR_PHY_SCRM_SEQ_XR 0xA23C 451#define AR_PHY_HEADER_DETECT_XR 0xA240 452#define AR_PHY_CHIRP_DETECTED_XR 0xA244 453#define AR_PHY_BLUETOOTH 0xA254 454 455#define AR_PHY_TPCRG1 0xA258 456#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 457#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 458 459#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 460#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 461#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 462#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 463#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 464#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 465 466#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 467#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 468 469#define AR_PHY_TX_PWRCTRL4 0xa264 470#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 471#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 472#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE 473#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 474 475#define AR_PHY_TX_PWRCTRL6_0 0xa270 476#define AR_PHY_TX_PWRCTRL6_1 0xb270 477#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000 478#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 479 480#define AR_PHY_TX_PWRCTRL7 0xa274 481#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000 482#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 483 484#define AR_PHY_TX_PWRCTRL9 0xa27C 485#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 486#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 487#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 488#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 489 490#define AR_PHY_TX_GAIN_TBL1 0xa300 491#define AR_PHY_TX_GAIN 0x0007F000 492#define AR_PHY_TX_GAIN_S 12 493 494#define AR_PHY_CH0_TX_PWRCTRL11 0xa398 495#define AR_PHY_CH1_TX_PWRCTRL11 0xb398 496#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00 497#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10 498 499#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 500#define AR_PHY_MASK2_M_31_45 0xa3a4 501#define AR_PHY_MASK2_M_16_30 0xa3a8 502#define AR_PHY_MASK2_M_00_15 0xa3ac 503#define AR_PHY_MASK2_P_15_01 0xa3b8 504#define AR_PHY_MASK2_P_30_16 0xa3bc 505#define AR_PHY_MASK2_P_45_31 0xa3c0 506#define AR_PHY_MASK2_P_61_45 0xa3c4 507#define AR_PHY_SPUR_REG 0x994c 508 509#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 510#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 511 512#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 513#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) 514#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 515#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 516#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 517#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 518 519#define AR_PHY_PILOT_MASK_01_30 0xa3b0 520#define AR_PHY_PILOT_MASK_31_60 0xa3b4 521 522#define AR_PHY_CHANNEL_MASK_01_30 0x99d4 523#define AR_PHY_CHANNEL_MASK_31_60 0x99d8 524 525#define AR_PHY_ANALOG_SWAP 0xa268 526#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 527 528#define AR_PHY_TPCRG5 0xA26C 529#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 530#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 531#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 532#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 533#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 534#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 535#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 536#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 537#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 538#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 539 540/* Carrier leak calibration control, do it after AGC calibration */ 541#define AR_PHY_CL_CAL_CTL 0xA358 542#define AR_PHY_CL_CAL_ENABLE 0x00000002 543#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 544 545#define AR_PHY_POWER_TX_RATE5 0xA38C 546#define AR_PHY_POWER_TX_RATE6 0xA390 547 548#define AR_PHY_CAL_CHAINMASK 0xA39C 549 550#define AR_PHY_POWER_TX_SUB 0xA3C8 551#define AR_PHY_POWER_TX_RATE7 0xA3CC 552#define AR_PHY_POWER_TX_RATE8 0xA3D0 553#define AR_PHY_POWER_TX_RATE9 0xA3D4 554 555#define AR_PHY_XPA_CFG 0xA3D8 556#define AR_PHY_FORCE_XPA_CFG 0x000000001 557#define AR_PHY_FORCE_XPA_CFG_S 0 558 559#define AR_PHY_CH1_CCA 0xa864 560#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 561#define AR_PHY_CH1_MINCCA_PWR_S 19 562#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 563#define AR9280_PHY_CH1_MINCCA_PWR_S 20 564 565#define AR_PHY_CH2_CCA 0xb864 566#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 567#define AR_PHY_CH2_MINCCA_PWR_S 19 568 569#define AR_PHY_CH1_EXT_CCA 0xa9bc 570#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 571#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 572#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 573#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 574 575#define AR_PHY_CH2_EXT_CCA 0xb9bc 576#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 577#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 578 579#define AR_PHY_CCA_NOM_VAL_5416_2GHZ -90 580#define AR_PHY_CCA_NOM_VAL_5416_5GHZ -100 581#define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ -100 582#define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ -110 583#define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80 584#define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90 585 586#define AR_PHY_CCA_NOM_VAL_9280_2GHZ -112 587#define AR_PHY_CCA_NOM_VAL_9280_5GHZ -112 588#define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ -127 589#define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ -122 590#define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ -97 591#define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ -102 592 593#define AR_PHY_CCA_NOM_VAL_9285_2GHZ -118 594#define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ -127 595#define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ -108 596 597#define AR_PHY_CCA_NOM_VAL_9271_2GHZ -118 598#define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ -127 599#define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ -116 600 601#define AR_PHY_CCA_NOM_VAL_9287_2GHZ -120 602#define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ -127 603#define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ -110 604 605#endif 606