1/**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2009 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11/* Common definitions for all Efx net driver code */ 12 13#ifndef EFX_NET_DRIVER_H 14#define EFX_NET_DRIVER_H 15 16#if defined(EFX_ENABLE_DEBUG) && !defined(DEBUG) 17#define DEBUG 18#endif 19 20#include <linux/version.h> 21#include <linux/netdevice.h> 22#include <linux/etherdevice.h> 23#include <linux/ethtool.h> 24#include <linux/if_vlan.h> 25#include <linux/timer.h> 26#include <linux/mdio.h> 27#include <linux/list.h> 28#include <linux/pci.h> 29#include <linux/device.h> 30#include <linux/highmem.h> 31#include <linux/workqueue.h> 32#include <linux/i2c.h> 33 34#include "enum.h" 35#include "bitfield.h" 36 37/************************************************************************** 38 * 39 * Build definitions 40 * 41 **************************************************************************/ 42 43#define EFX_DRIVER_VERSION "3.0" 44 45#ifdef EFX_ENABLE_DEBUG 46#define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 47#define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 48#else 49#define EFX_BUG_ON_PARANOID(x) do {} while (0) 50#define EFX_WARN_ON_PARANOID(x) do {} while (0) 51#endif 52 53/************************************************************************** 54 * 55 * Efx data structures 56 * 57 **************************************************************************/ 58 59#define EFX_MAX_CHANNELS 32 60#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 61 62/* Checksum generation is a per-queue option in hardware, so each 63 * queue visible to the networking core is backed by two hardware TX 64 * queues. */ 65#define EFX_MAX_CORE_TX_QUEUES EFX_MAX_CHANNELS 66#define EFX_TXQ_TYPE_OFFLOAD 1 67#define EFX_TXQ_TYPES 2 68#define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES) 69 70/** 71 * struct efx_special_buffer - An Efx special buffer 72 * @addr: CPU base address of the buffer 73 * @dma_addr: DMA base address of the buffer 74 * @len: Buffer length, in bytes 75 * @index: Buffer index within controller;s buffer table 76 * @entries: Number of buffer table entries 77 * 78 * Special buffers are used for the event queues and the TX and RX 79 * descriptor queues for each channel. They are *not* used for the 80 * actual transmit and receive buffers. 81 */ 82struct efx_special_buffer { 83 void *addr; 84 dma_addr_t dma_addr; 85 unsigned int len; 86 int index; 87 int entries; 88}; 89 90enum efx_flush_state { 91 FLUSH_NONE, 92 FLUSH_PENDING, 93 FLUSH_FAILED, 94 FLUSH_DONE, 95}; 96 97/** 98 * struct efx_tx_buffer - An Efx TX buffer 99 * @skb: The associated socket buffer. 100 * Set only on the final fragment of a packet; %NULL for all other 101 * fragments. When this fragment completes, then we can free this 102 * skb. 103 * @tsoh: The associated TSO header structure, or %NULL if this 104 * buffer is not a TSO header. 105 * @dma_addr: DMA address of the fragment. 106 * @len: Length of this fragment. 107 * This field is zero when the queue slot is empty. 108 * @continuation: True if this fragment is not the end of a packet. 109 * @unmap_single: True if pci_unmap_single should be used. 110 * @unmap_len: Length of this fragment to unmap 111 */ 112struct efx_tx_buffer { 113 const struct sk_buff *skb; 114 struct efx_tso_header *tsoh; 115 dma_addr_t dma_addr; 116 unsigned short len; 117 bool continuation; 118 bool unmap_single; 119 unsigned short unmap_len; 120}; 121 122/** 123 * struct efx_tx_queue - An Efx TX queue 124 * 125 * This is a ring buffer of TX fragments. 126 * Since the TX completion path always executes on the same 127 * CPU and the xmit path can operate on different CPUs, 128 * performance is increased by ensuring that the completion 129 * path and the xmit path operate on different cache lines. 130 * This is particularly important if the xmit path is always 131 * executing on one CPU which is different from the completion 132 * path. There is also a cache line for members which are 133 * read but not written on the fast path. 134 * 135 * @efx: The associated Efx NIC 136 * @queue: DMA queue number 137 * @channel: The associated channel 138 * @buffer: The software buffer ring 139 * @txd: The hardware descriptor ring 140 * @flushed: Used when handling queue flushing 141 * @read_count: Current read pointer. 142 * This is the number of buffers that have been removed from both rings. 143 * @stopped: Stopped count. 144 * Set if this TX queue is currently stopping its port. 145 * @insert_count: Current insert pointer 146 * This is the number of buffers that have been added to the 147 * software ring. 148 * @write_count: Current write pointer 149 * This is the number of buffers that have been added to the 150 * hardware ring. 151 * @old_read_count: The value of read_count when last checked. 152 * This is here for performance reasons. The xmit path will 153 * only get the up-to-date value of read_count if this 154 * variable indicates that the queue is full. This is to 155 * avoid cache-line ping-pong between the xmit path and the 156 * completion path. 157 * @tso_headers_free: A list of TSO headers allocated for this TX queue 158 * that are not in use, and so available for new TSO sends. The list 159 * is protected by the TX queue lock. 160 * @tso_bursts: Number of times TSO xmit invoked by kernel 161 * @tso_long_headers: Number of packets with headers too long for standard 162 * blocks 163 * @tso_packets: Number of packets via the TSO xmit path 164 */ 165struct efx_tx_queue { 166 /* Members which don't change on the fast path */ 167 struct efx_nic *efx ____cacheline_aligned_in_smp; 168 unsigned queue; 169 struct efx_channel *channel; 170 struct efx_nic *nic; 171 struct efx_tx_buffer *buffer; 172 struct efx_special_buffer txd; 173 enum efx_flush_state flushed; 174 175 /* Members used mainly on the completion path */ 176 unsigned int read_count ____cacheline_aligned_in_smp; 177 int stopped; 178 179 /* Members used only on the xmit path */ 180 unsigned int insert_count ____cacheline_aligned_in_smp; 181 unsigned int write_count; 182 unsigned int old_read_count; 183 struct efx_tso_header *tso_headers_free; 184 unsigned int tso_bursts; 185 unsigned int tso_long_headers; 186 unsigned int tso_packets; 187}; 188 189/** 190 * struct efx_rx_buffer - An Efx RX data buffer 191 * @dma_addr: DMA base address of the buffer 192 * @skb: The associated socket buffer, if any. 193 * If both this and page are %NULL, the buffer slot is currently free. 194 * @page: The associated page buffer, if any. 195 * If both this and skb are %NULL, the buffer slot is currently free. 196 * @data: Pointer to ethernet header 197 * @len: Buffer length, in bytes. 198 */ 199struct efx_rx_buffer { 200 dma_addr_t dma_addr; 201 struct sk_buff *skb; 202 struct page *page; 203 char *data; 204 unsigned int len; 205}; 206 207/** 208 * struct efx_rx_page_state - Page-based rx buffer state 209 * 210 * Inserted at the start of every page allocated for receive buffers. 211 * Used to facilitate sharing dma mappings between recycled rx buffers 212 * and those passed up to the kernel. 213 * 214 * @refcnt: Number of struct efx_rx_buffer's referencing this page. 215 * When refcnt falls to zero, the page is unmapped for dma 216 * @dma_addr: The dma address of this page. 217 */ 218struct efx_rx_page_state { 219 unsigned refcnt; 220 dma_addr_t dma_addr; 221 222 unsigned int __pad[0] ____cacheline_aligned; 223}; 224 225/** 226 * struct efx_rx_queue - An Efx RX queue 227 * @efx: The associated Efx NIC 228 * @queue: DMA queue number 229 * @channel: The associated channel 230 * @buffer: The software buffer ring 231 * @rxd: The hardware descriptor ring 232 * @added_count: Number of buffers added to the receive queue. 233 * @notified_count: Number of buffers given to NIC (<= @added_count). 234 * @removed_count: Number of buffers removed from the receive queue. 235 * @max_fill: RX descriptor maximum fill level (<= ring size) 236 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 237 * (<= @max_fill) 238 * @fast_fill_limit: The level to which a fast fill will fill 239 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill) 240 * @min_fill: RX descriptor minimum non-zero fill level. 241 * This records the minimum fill level observed when a ring 242 * refill was triggered. 243 * @min_overfill: RX descriptor minimum overflow fill level. 244 * This records the minimum fill level at which RX queue 245 * overflow was observed. It should never be set. 246 * @alloc_page_count: RX allocation strategy counter. 247 * @alloc_skb_count: RX allocation strategy counter. 248 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 249 * @flushed: Use when handling queue flushing 250 */ 251struct efx_rx_queue { 252 struct efx_nic *efx; 253 int queue; 254 struct efx_channel *channel; 255 struct efx_rx_buffer *buffer; 256 struct efx_special_buffer rxd; 257 258 int added_count; 259 int notified_count; 260 int removed_count; 261 unsigned int max_fill; 262 unsigned int fast_fill_trigger; 263 unsigned int fast_fill_limit; 264 unsigned int min_fill; 265 unsigned int min_overfill; 266 unsigned int alloc_page_count; 267 unsigned int alloc_skb_count; 268 struct timer_list slow_fill; 269 unsigned int slow_fill_count; 270 271 enum efx_flush_state flushed; 272}; 273 274/** 275 * struct efx_buffer - An Efx general-purpose buffer 276 * @addr: host base address of the buffer 277 * @dma_addr: DMA base address of the buffer 278 * @len: Buffer length, in bytes 279 * 280 * The NIC uses these buffers for its interrupt status registers and 281 * MAC stats dumps. 282 */ 283struct efx_buffer { 284 void *addr; 285 dma_addr_t dma_addr; 286 unsigned int len; 287}; 288 289 290enum efx_rx_alloc_method { 291 RX_ALLOC_METHOD_AUTO = 0, 292 RX_ALLOC_METHOD_SKB = 1, 293 RX_ALLOC_METHOD_PAGE = 2, 294}; 295 296/** 297 * struct efx_channel - An Efx channel 298 * 299 * A channel comprises an event queue, at least one TX queue, at least 300 * one RX queue, and an associated tasklet for processing the event 301 * queue. 302 * 303 * @efx: Associated Efx NIC 304 * @channel: Channel instance number 305 * @name: Name for channel and IRQ 306 * @enabled: Channel enabled indicator 307 * @irq: IRQ number (MSI and MSI-X only) 308 * @irq_moderation: IRQ moderation value (in hardware ticks) 309 * @napi_dev: Net device used with NAPI 310 * @napi_str: NAPI control structure 311 * @reset_work: Scheduled reset work thread 312 * @work_pending: Is work pending via NAPI? 313 * @eventq: Event queue buffer 314 * @eventq_read_ptr: Event queue read pointer 315 * @last_eventq_read_ptr: Last event queue read pointer value. 316 * @magic_count: Event queue test event count 317 * @irq_count: Number of IRQs since last adaptive moderation decision 318 * @irq_mod_score: IRQ moderation score 319 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors 320 * and diagnostic counters 321 * @rx_alloc_push_pages: RX allocation method currently in use for pushing 322 * descriptors 323 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 324 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 325 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 326 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 327 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 328 * @n_rx_overlength: Count of RX_OVERLENGTH errors 329 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 330 * @tx_queue: Pointer to first TX queue, or %NULL if not used for TX 331 * @tx_stop_count: Core TX queue stop count 332 * @tx_stop_lock: Core TX queue stop lock 333 */ 334struct efx_channel { 335 struct efx_nic *efx; 336 int channel; 337 char name[IFNAMSIZ + 6]; 338 bool enabled; 339 int irq; 340 unsigned int irq_moderation; 341 struct net_device *napi_dev; 342 struct napi_struct napi_str; 343 bool work_pending; 344 struct efx_special_buffer eventq; 345 unsigned int eventq_read_ptr; 346 unsigned int last_eventq_read_ptr; 347 unsigned int magic_count; 348 349 unsigned int irq_count; 350 unsigned int irq_mod_score; 351 352 int rx_alloc_level; 353 int rx_alloc_push_pages; 354 355 unsigned n_rx_tobe_disc; 356 unsigned n_rx_ip_hdr_chksum_err; 357 unsigned n_rx_tcp_udp_chksum_err; 358 unsigned n_rx_mcast_mismatch; 359 unsigned n_rx_frm_trunc; 360 unsigned n_rx_overlength; 361 unsigned n_skbuff_leaks; 362 363 /* Used to pipeline received packets in order to optimise memory 364 * access with prefetches. 365 */ 366 struct efx_rx_buffer *rx_pkt; 367 bool rx_pkt_csummed; 368 369 struct efx_tx_queue *tx_queue; 370 atomic_t tx_stop_count; 371 spinlock_t tx_stop_lock; 372}; 373 374enum efx_led_mode { 375 EFX_LED_OFF = 0, 376 EFX_LED_ON = 1, 377 EFX_LED_DEFAULT = 2 378}; 379 380#define STRING_TABLE_LOOKUP(val, member) \ 381 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 382 383extern const char *efx_loopback_mode_names[]; 384extern const unsigned int efx_loopback_mode_max; 385#define LOOPBACK_MODE(efx) \ 386 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 387 388extern const char *efx_interrupt_mode_names[]; 389extern const unsigned int efx_interrupt_mode_max; 390#define INT_MODE(efx) \ 391 STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode) 392 393extern const char *efx_reset_type_names[]; 394extern const unsigned int efx_reset_type_max; 395#define RESET_TYPE(type) \ 396 STRING_TABLE_LOOKUP(type, efx_reset_type) 397 398enum efx_int_mode { 399 /* Be careful if altering to correct macro below */ 400 EFX_INT_MODE_MSIX = 0, 401 EFX_INT_MODE_MSI = 1, 402 EFX_INT_MODE_LEGACY = 2, 403 EFX_INT_MODE_MAX /* Insert any new items before this */ 404}; 405#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 406 407#define EFX_IS10G(efx) ((efx)->link_state.speed == 10000) 408 409enum nic_state { 410 STATE_INIT = 0, 411 STATE_RUNNING = 1, 412 STATE_FINI = 2, 413 STATE_DISABLED = 3, 414 STATE_MAX, 415}; 416 417/* 418 * Alignment of page-allocated RX buffers 419 * 420 * Controls the number of bytes inserted at the start of an RX buffer. 421 * This is the equivalent of NET_IP_ALIGN [which controls the alignment 422 * of the skb->head for hardware DMA]. 423 */ 424#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 425#define EFX_PAGE_IP_ALIGN 0 426#else 427#define EFX_PAGE_IP_ALIGN NET_IP_ALIGN 428#endif 429 430/* 431 * Alignment of the skb->head which wraps a page-allocated RX buffer 432 * 433 * The skb allocated to wrap an rx_buffer can have this alignment. Since 434 * the data is memcpy'd from the rx_buf, it does not need to be equal to 435 * EFX_PAGE_IP_ALIGN. 436 */ 437#define EFX_PAGE_SKB_ALIGN 2 438 439/* Forward declaration */ 440struct efx_nic; 441 442/* Pseudo bit-mask flow control field */ 443enum efx_fc_type { 444 EFX_FC_RX = FLOW_CTRL_RX, 445 EFX_FC_TX = FLOW_CTRL_TX, 446 EFX_FC_AUTO = 4, 447}; 448 449/** 450 * struct efx_link_state - Current state of the link 451 * @up: Link is up 452 * @fd: Link is full-duplex 453 * @fc: Actual flow control flags 454 * @speed: Link speed (Mbps) 455 */ 456struct efx_link_state { 457 bool up; 458 bool fd; 459 enum efx_fc_type fc; 460 unsigned int speed; 461}; 462 463static inline bool efx_link_state_equal(const struct efx_link_state *left, 464 const struct efx_link_state *right) 465{ 466 return left->up == right->up && left->fd == right->fd && 467 left->fc == right->fc && left->speed == right->speed; 468} 469 470/** 471 * struct efx_mac_operations - Efx MAC operations table 472 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock 473 * @update_stats: Update statistics 474 * @check_fault: Check fault state. True if fault present. 475 */ 476struct efx_mac_operations { 477 int (*reconfigure) (struct efx_nic *efx); 478 void (*update_stats) (struct efx_nic *efx); 479 bool (*check_fault)(struct efx_nic *efx); 480}; 481 482/** 483 * struct efx_phy_operations - Efx PHY operations table 484 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 485 * efx->loopback_modes. 486 * @init: Initialise PHY 487 * @fini: Shut down PHY 488 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 489 * @poll: Update @link_state and report whether it changed. 490 * Serialised by the mac_lock. 491 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 492 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 493 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 494 * (only needed where AN bit is set in mmds) 495 * @test_alive: Test that PHY is 'alive' (online) 496 * @test_name: Get the name of a PHY-specific test/result 497 * @run_tests: Run tests and record results as appropriate (offline). 498 * Flags are the ethtool tests flags. 499 */ 500struct efx_phy_operations { 501 int (*probe) (struct efx_nic *efx); 502 int (*init) (struct efx_nic *efx); 503 void (*fini) (struct efx_nic *efx); 504 void (*remove) (struct efx_nic *efx); 505 int (*reconfigure) (struct efx_nic *efx); 506 bool (*poll) (struct efx_nic *efx); 507 void (*get_settings) (struct efx_nic *efx, 508 struct ethtool_cmd *ecmd); 509 int (*set_settings) (struct efx_nic *efx, 510 struct ethtool_cmd *ecmd); 511 void (*set_npage_adv) (struct efx_nic *efx, u32); 512 int (*test_alive) (struct efx_nic *efx); 513 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 514 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 515}; 516 517/** 518 * @enum efx_phy_mode - PHY operating mode flags 519 * @PHY_MODE_NORMAL: on and should pass traffic 520 * @PHY_MODE_TX_DISABLED: on with TX disabled 521 * @PHY_MODE_LOW_POWER: set to low power through MDIO 522 * @PHY_MODE_OFF: switched off through external control 523 * @PHY_MODE_SPECIAL: on but will not pass traffic 524 */ 525enum efx_phy_mode { 526 PHY_MODE_NORMAL = 0, 527 PHY_MODE_TX_DISABLED = 1, 528 PHY_MODE_LOW_POWER = 2, 529 PHY_MODE_OFF = 4, 530 PHY_MODE_SPECIAL = 8, 531}; 532 533static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 534{ 535 return !!(mode & ~PHY_MODE_TX_DISABLED); 536} 537 538/* 539 * Efx extended statistics 540 * 541 * Not all statistics are provided by all supported MACs. The purpose 542 * is this structure is to contain the raw statistics provided by each 543 * MAC. 544 */ 545struct efx_mac_stats { 546 u64 tx_bytes; 547 u64 tx_good_bytes; 548 u64 tx_bad_bytes; 549 unsigned long tx_packets; 550 unsigned long tx_bad; 551 unsigned long tx_pause; 552 unsigned long tx_control; 553 unsigned long tx_unicast; 554 unsigned long tx_multicast; 555 unsigned long tx_broadcast; 556 unsigned long tx_lt64; 557 unsigned long tx_64; 558 unsigned long tx_65_to_127; 559 unsigned long tx_128_to_255; 560 unsigned long tx_256_to_511; 561 unsigned long tx_512_to_1023; 562 unsigned long tx_1024_to_15xx; 563 unsigned long tx_15xx_to_jumbo; 564 unsigned long tx_gtjumbo; 565 unsigned long tx_collision; 566 unsigned long tx_single_collision; 567 unsigned long tx_multiple_collision; 568 unsigned long tx_excessive_collision; 569 unsigned long tx_deferred; 570 unsigned long tx_late_collision; 571 unsigned long tx_excessive_deferred; 572 unsigned long tx_non_tcpudp; 573 unsigned long tx_mac_src_error; 574 unsigned long tx_ip_src_error; 575 u64 rx_bytes; 576 u64 rx_good_bytes; 577 u64 rx_bad_bytes; 578 unsigned long rx_packets; 579 unsigned long rx_good; 580 unsigned long rx_bad; 581 unsigned long rx_pause; 582 unsigned long rx_control; 583 unsigned long rx_unicast; 584 unsigned long rx_multicast; 585 unsigned long rx_broadcast; 586 unsigned long rx_lt64; 587 unsigned long rx_64; 588 unsigned long rx_65_to_127; 589 unsigned long rx_128_to_255; 590 unsigned long rx_256_to_511; 591 unsigned long rx_512_to_1023; 592 unsigned long rx_1024_to_15xx; 593 unsigned long rx_15xx_to_jumbo; 594 unsigned long rx_gtjumbo; 595 unsigned long rx_bad_lt64; 596 unsigned long rx_bad_64_to_15xx; 597 unsigned long rx_bad_15xx_to_jumbo; 598 unsigned long rx_bad_gtjumbo; 599 unsigned long rx_overflow; 600 unsigned long rx_missed; 601 unsigned long rx_false_carrier; 602 unsigned long rx_symbol_error; 603 unsigned long rx_align_error; 604 unsigned long rx_length_error; 605 unsigned long rx_internal_error; 606 unsigned long rx_good_lt64; 607}; 608 609/* Number of bits used in a multicast filter hash address */ 610#define EFX_MCAST_HASH_BITS 8 611 612/* Number of (single-bit) entries in a multicast filter hash */ 613#define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 614 615/* An Efx multicast filter hash */ 616union efx_multicast_hash { 617 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 618 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 619}; 620 621/** 622 * struct efx_nic - an Efx NIC 623 * @name: Device name (net device name or bus id before net device registered) 624 * @pci_dev: The PCI device 625 * @type: Controller type attributes 626 * @legacy_irq: IRQ number 627 * @workqueue: Workqueue for port reconfigures and the HW monitor. 628 * Work items do not hold and must not acquire RTNL. 629 * @workqueue_name: Name of workqueue 630 * @reset_work: Scheduled reset workitem 631 * @monitor_work: Hardware monitor workitem 632 * @membase_phys: Memory BAR value as physical address 633 * @membase: Memory BAR value 634 * @biu_lock: BIU (bus interface unit) lock 635 * @interrupt_mode: Interrupt mode 636 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 637 * @irq_rx_moderation: IRQ moderation time for RX event queues 638 * @msg_enable: Log message enable flags 639 * @state: Device state flag. Serialised by the rtnl_lock. 640 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE) 641 * @tx_queue: TX DMA queues 642 * @rx_queue: RX DMA queues 643 * @channel: Channels 644 * @next_buffer_table: First available buffer table id 645 * @n_channels: Number of channels in use 646 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 647 * @n_tx_channels: Number of channels used for TX 648 * @rx_buffer_len: RX buffer length 649 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 650 * @rx_indir_table: Indirection table for RSS 651 * @int_error_count: Number of internal errors seen recently 652 * @int_error_expire: Time at which error count will be expired 653 * @irq_status: Interrupt status buffer 654 * @last_irq_cpu: Last CPU to handle interrupt. 655 * This register is written with the SMP processor ID whenever an 656 * interrupt is handled. It is used by efx_nic_test_interrupt() 657 * to verify that an interrupt has occurred. 658 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 659 * @fatal_irq_level: IRQ level (bit number) used for serious errors 660 * @spi_flash: SPI flash device 661 * This field will be %NULL if no flash device is present (or for Siena). 662 * @spi_eeprom: SPI EEPROM device 663 * This field will be %NULL if no EEPROM device is present (or for Siena). 664 * @spi_lock: SPI bus lock 665 * @mtd_list: List of MTDs attached to the NIC 666 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count 667 * @nic_data: Hardware dependant state 668 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 669 * @port_inhibited, efx_monitor() and efx_reconfigure_port() 670 * @port_enabled: Port enabled indicator. 671 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 672 * efx_mac_work() with kernel interfaces. Safe to read under any 673 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 674 * be held to modify it. 675 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock 676 * @port_initialized: Port initialized? 677 * @net_dev: Operating system network device. Consider holding the rtnl lock 678 * @rx_checksum_enabled: RX checksumming enabled 679 * @mac_stats: MAC statistics. These include all statistics the MACs 680 * can provide. Generic code converts these into a standard 681 * &struct net_device_stats. 682 * @stats_buffer: DMA buffer for statistics 683 * @stats_lock: Statistics update lock. Serialises statistics fetches 684 * @mac_op: MAC interface 685 * @mac_address: Permanent MAC address 686 * @phy_type: PHY type 687 * @mdio_lock: MDIO lock 688 * @phy_op: PHY interface 689 * @phy_data: PHY private data (including PHY-specific stats) 690 * @mdio: PHY MDIO interface 691 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 692 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 693 * @xmac_poll_required: XMAC link state needs polling 694 * @link_advertising: Autonegotiation advertising flags 695 * @link_state: Current state of the link 696 * @n_link_state_changes: Number of times the link has changed state 697 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. 698 * @multicast_hash: Multicast hash table 699 * @wanted_fc: Wanted flow control flags 700 * @mac_work: Work item for changing MAC promiscuity and multicast hash 701 * @loopback_mode: Loopback status 702 * @loopback_modes: Supported loopback mode bitmask 703 * @loopback_selftest: Offline self-test private state 704 * 705 * This is stored in the private area of the &struct net_device. 706 */ 707struct efx_nic { 708 char name[IFNAMSIZ]; 709 struct pci_dev *pci_dev; 710 const struct efx_nic_type *type; 711 int legacy_irq; 712 struct workqueue_struct *workqueue; 713 char workqueue_name[16]; 714 struct work_struct reset_work; 715 struct delayed_work monitor_work; 716 resource_size_t membase_phys; 717 void __iomem *membase; 718 spinlock_t biu_lock; 719 enum efx_int_mode interrupt_mode; 720 bool irq_rx_adaptive; 721 unsigned int irq_rx_moderation; 722 u32 msg_enable; 723 724 enum nic_state state; 725 enum reset_type reset_pending; 726 727 struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES]; 728 struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES]; 729 struct efx_channel channel[EFX_MAX_CHANNELS]; 730 731 unsigned next_buffer_table; 732 unsigned n_channels; 733 unsigned n_rx_channels; 734 unsigned n_tx_channels; 735 unsigned int rx_buffer_len; 736 unsigned int rx_buffer_order; 737 u8 rx_hash_key[40]; 738 u32 rx_indir_table[128]; 739 740 unsigned int_error_count; 741 unsigned long int_error_expire; 742 743 struct efx_buffer irq_status; 744 volatile signed int last_irq_cpu; 745 unsigned irq_zero_count; 746 unsigned fatal_irq_level; 747 748 struct efx_spi_device *spi_flash; 749 struct efx_spi_device *spi_eeprom; 750 struct mutex spi_lock; 751#ifdef CONFIG_SFC_MTD 752 struct list_head mtd_list; 753#endif 754 755 unsigned n_rx_nodesc_drop_cnt; 756 757 void *nic_data; 758 759 struct mutex mac_lock; 760 struct work_struct mac_work; 761 bool port_enabled; 762 bool port_inhibited; 763 764 bool port_initialized; 765 struct net_device *net_dev; 766 bool rx_checksum_enabled; 767 768 struct efx_mac_stats mac_stats; 769 struct efx_buffer stats_buffer; 770 spinlock_t stats_lock; 771 772 struct efx_mac_operations *mac_op; 773 unsigned char mac_address[ETH_ALEN]; 774 775 unsigned int phy_type; 776 struct mutex mdio_lock; 777 struct efx_phy_operations *phy_op; 778 void *phy_data; 779 struct mdio_if_info mdio; 780 unsigned int mdio_bus; 781 enum efx_phy_mode phy_mode; 782 783 bool xmac_poll_required; 784 u32 link_advertising; 785 struct efx_link_state link_state; 786 unsigned int n_link_state_changes; 787 788 bool promiscuous; 789 union efx_multicast_hash multicast_hash; 790 enum efx_fc_type wanted_fc; 791 792 atomic_t rx_reset; 793 enum efx_loopback_mode loopback_mode; 794 u64 loopback_modes; 795 796 void *loopback_selftest; 797}; 798 799static inline int efx_dev_registered(struct efx_nic *efx) 800{ 801 return efx->net_dev->reg_state == NETREG_REGISTERED; 802} 803 804/* Net device name, for inclusion in log messages if it has been registered. 805 * Use efx->name not efx->net_dev->name so that races with (un)registration 806 * are harmless. 807 */ 808static inline const char *efx_dev_name(struct efx_nic *efx) 809{ 810 return efx_dev_registered(efx) ? efx->name : ""; 811} 812 813static inline unsigned int efx_port_num(struct efx_nic *efx) 814{ 815 return efx->net_dev->dev_id; 816} 817 818/** 819 * struct efx_nic_type - Efx device type definition 820 * @probe: Probe the controller 821 * @remove: Free resources allocated by probe() 822 * @init: Initialise the controller 823 * @fini: Shut down the controller 824 * @monitor: Periodic function for polling link state and hardware monitor 825 * @reset: Reset the controller hardware and possibly the PHY. This will 826 * be called while the controller is uninitialised. 827 * @probe_port: Probe the MAC and PHY 828 * @remove_port: Free resources allocated by probe_port() 829 * @prepare_flush: Prepare the hardware for flushing the DMA queues 830 * @update_stats: Update statistics not provided by event handling 831 * @start_stats: Start the regular fetching of statistics 832 * @stop_stats: Stop the regular fetching of statistics 833 * @set_id_led: Set state of identifying LED or revert to automatic function 834 * @push_irq_moderation: Apply interrupt moderation value 835 * @push_multicast_hash: Apply multicast hash table 836 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 837 * @get_wol: Get WoL configuration from driver state 838 * @set_wol: Push WoL configuration to the NIC 839 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 840 * @test_registers: Test read/write functionality of control registers 841 * @test_nvram: Test validity of NVRAM contents 842 * @default_mac_ops: efx_mac_operations to set at startup 843 * @revision: Hardware architecture revision 844 * @mem_map_size: Memory BAR mapped size 845 * @txd_ptr_tbl_base: TX descriptor ring base address 846 * @rxd_ptr_tbl_base: RX descriptor ring base address 847 * @buf_tbl_base: Buffer table base address 848 * @evq_ptr_tbl_base: Event queue pointer table base address 849 * @evq_rptr_tbl_base: Event queue read-pointer table base address 850 * @max_dma_mask: Maximum possible DMA mask 851 * @rx_buffer_hash_size: Size of hash at start of RX buffer 852 * @rx_buffer_padding: Size of padding at end of RX buffer 853 * @max_interrupt_mode: Highest capability interrupt mode supported 854 * from &enum efx_init_mode. 855 * @phys_addr_channels: Number of channels with physically addressed 856 * descriptors 857 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches 858 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches 859 * @offload_features: net_device feature flags for protocol offload 860 * features implemented in hardware 861 * @reset_world_flags: Flags for additional components covered by 862 * reset method RESET_TYPE_WORLD 863 */ 864struct efx_nic_type { 865 int (*probe)(struct efx_nic *efx); 866 void (*remove)(struct efx_nic *efx); 867 int (*init)(struct efx_nic *efx); 868 void (*fini)(struct efx_nic *efx); 869 void (*monitor)(struct efx_nic *efx); 870 int (*reset)(struct efx_nic *efx, enum reset_type method); 871 int (*probe_port)(struct efx_nic *efx); 872 void (*remove_port)(struct efx_nic *efx); 873 void (*prepare_flush)(struct efx_nic *efx); 874 void (*update_stats)(struct efx_nic *efx); 875 void (*start_stats)(struct efx_nic *efx); 876 void (*stop_stats)(struct efx_nic *efx); 877 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 878 void (*push_irq_moderation)(struct efx_channel *channel); 879 void (*push_multicast_hash)(struct efx_nic *efx); 880 int (*reconfigure_port)(struct efx_nic *efx); 881 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 882 int (*set_wol)(struct efx_nic *efx, u32 type); 883 void (*resume_wol)(struct efx_nic *efx); 884 int (*test_registers)(struct efx_nic *efx); 885 int (*test_nvram)(struct efx_nic *efx); 886 struct efx_mac_operations *default_mac_ops; 887 888 int revision; 889 unsigned int mem_map_size; 890 unsigned int txd_ptr_tbl_base; 891 unsigned int rxd_ptr_tbl_base; 892 unsigned int buf_tbl_base; 893 unsigned int evq_ptr_tbl_base; 894 unsigned int evq_rptr_tbl_base; 895 u64 max_dma_mask; 896 unsigned int rx_buffer_hash_size; 897 unsigned int rx_buffer_padding; 898 unsigned int max_interrupt_mode; 899 unsigned int phys_addr_channels; 900 unsigned int tx_dc_base; 901 unsigned int rx_dc_base; 902 unsigned long offload_features; 903 u32 reset_world_flags; 904}; 905 906/************************************************************************** 907 * 908 * Prototypes and inline functions 909 * 910 *************************************************************************/ 911 912/* Iterate over all used channels */ 913#define efx_for_each_channel(_channel, _efx) \ 914 for (_channel = &((_efx)->channel[0]); \ 915 _channel < &((_efx)->channel[(efx)->n_channels]); \ 916 _channel++) 917 918/* Iterate over all used TX queues */ 919#define efx_for_each_tx_queue(_tx_queue, _efx) \ 920 for (_tx_queue = &((_efx)->tx_queue[0]); \ 921 _tx_queue < &((_efx)->tx_queue[EFX_TXQ_TYPES * \ 922 (_efx)->n_tx_channels]); \ 923 _tx_queue++) 924 925/* Iterate over all TX queues belonging to a channel */ 926#define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 927 for (_tx_queue = (_channel)->tx_queue; \ 928 _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 929 _tx_queue++) 930 931/* Iterate over all used RX queues */ 932#define efx_for_each_rx_queue(_rx_queue, _efx) \ 933 for (_rx_queue = &((_efx)->rx_queue[0]); \ 934 _rx_queue < &((_efx)->rx_queue[(_efx)->n_rx_channels]); \ 935 _rx_queue++) 936 937/* Iterate over all RX queues belonging to a channel */ 938#define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 939 for (_rx_queue = &((_channel)->efx->rx_queue[(_channel)->channel]); \ 940 _rx_queue; \ 941 _rx_queue = NULL) \ 942 if (_rx_queue->channel != (_channel)) \ 943 continue; \ 944 else 945 946/* Returns a pointer to the specified receive buffer in the RX 947 * descriptor queue. 948 */ 949static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 950 unsigned int index) 951{ 952 return (&rx_queue->buffer[index]); 953} 954 955/* Set bit in a little-endian bitfield */ 956static inline void set_bit_le(unsigned nr, unsigned char *addr) 957{ 958 addr[nr / 8] |= (1 << (nr % 8)); 959} 960 961/* Clear bit in a little-endian bitfield */ 962static inline void clear_bit_le(unsigned nr, unsigned char *addr) 963{ 964 addr[nr / 8] &= ~(1 << (nr % 8)); 965} 966 967 968#define EFX_MAX_FRAME_LEN(mtu) \ 969 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 970 971 972#endif /* EFX_NET_DRIVER_H */ 973