1/* 2 * Driver for the Macintosh 68K onboard MACE controller with PSC 3 * driven DMA. The MACE driver code is derived from mace.c. The 4 * Mac68k theory of operation is courtesy of the MacBSD wizards. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Copyright (C) 1996 Paul Mackerras. 12 * Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk> 13 * 14 * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver 15 * 16 * Copyright (C) 2007 Finn Thain 17 * 18 * Converted to DMA API, converted to unified driver model, 19 * sync'd some routines with mace.c and fixed various bugs. 20 */ 21 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/netdevice.h> 26#include <linux/etherdevice.h> 27#include <linux/delay.h> 28#include <linux/string.h> 29#include <linux/crc32.h> 30#include <linux/bitrev.h> 31#include <linux/dma-mapping.h> 32#include <linux/platform_device.h> 33#include <linux/gfp.h> 34#include <asm/io.h> 35#include <asm/irq.h> 36#include <asm/macintosh.h> 37#include <asm/macints.h> 38#include <asm/mac_psc.h> 39#include <asm/page.h> 40#include "mace.h" 41 42static char mac_mace_string[] = "macmace"; 43 44#define N_TX_BUFF_ORDER 0 45#define N_TX_RING (1 << N_TX_BUFF_ORDER) 46#define N_RX_BUFF_ORDER 3 47#define N_RX_RING (1 << N_RX_BUFF_ORDER) 48 49#define TX_TIMEOUT HZ 50 51#define MACE_BUFF_SIZE 0x800 52 53#define BROKEN_ADDRCHG_REV 0x0941 54 55/* The MACE is simply wired down on a Mac68K box */ 56 57#define MACE_BASE (void *)(0x50F1C000) 58#define MACE_PROM (void *)(0x50F08001) 59 60struct mace_data { 61 volatile struct mace *mace; 62 unsigned char *tx_ring; 63 dma_addr_t tx_ring_phys; 64 unsigned char *rx_ring; 65 dma_addr_t rx_ring_phys; 66 int dma_intr; 67 int rx_slot, rx_tail; 68 int tx_slot, tx_sloti, tx_count; 69 int chipid; 70 struct device *device; 71}; 72 73struct mace_frame { 74 u8 rcvcnt; 75 u8 pad1; 76 u8 rcvsts; 77 u8 pad2; 78 u8 rntpc; 79 u8 pad3; 80 u8 rcvcc; 81 u8 pad4; 82 u32 pad5; 83 u32 pad6; 84 u8 data[1]; 85 /* And frame continues.. */ 86}; 87 88#define PRIV_BYTES sizeof(struct mace_data) 89 90static int mace_open(struct net_device *dev); 91static int mace_close(struct net_device *dev); 92static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); 93static void mace_set_multicast(struct net_device *dev); 94static int mace_set_address(struct net_device *dev, void *addr); 95static void mace_reset(struct net_device *dev); 96static irqreturn_t mace_interrupt(int irq, void *dev_id); 97static irqreturn_t mace_dma_intr(int irq, void *dev_id); 98static void mace_tx_timeout(struct net_device *dev); 99static void __mace_set_address(struct net_device *dev, void *addr); 100 101/* 102 * Load a receive DMA channel with a base address and ring length 103 */ 104 105static void mace_load_rxdma_base(struct net_device *dev, int set) 106{ 107 struct mace_data *mp = netdev_priv(dev); 108 109 psc_write_word(PSC_ENETRD_CMD + set, 0x0100); 110 psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); 111 psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); 112 psc_write_word(PSC_ENETRD_CMD + set, 0x9800); 113 mp->rx_tail = 0; 114} 115 116/* 117 * Reset the receive DMA subsystem 118 */ 119 120static void mace_rxdma_reset(struct net_device *dev) 121{ 122 struct mace_data *mp = netdev_priv(dev); 123 volatile struct mace *mace = mp->mace; 124 u8 maccc = mace->maccc; 125 126 mace->maccc = maccc & ~ENRCV; 127 128 psc_write_word(PSC_ENETRD_CTL, 0x8800); 129 mace_load_rxdma_base(dev, 0x00); 130 psc_write_word(PSC_ENETRD_CTL, 0x0400); 131 132 psc_write_word(PSC_ENETRD_CTL, 0x8800); 133 mace_load_rxdma_base(dev, 0x10); 134 psc_write_word(PSC_ENETRD_CTL, 0x0400); 135 136 mace->maccc = maccc; 137 mp->rx_slot = 0; 138 139 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800); 140 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800); 141} 142 143/* 144 * Reset the transmit DMA subsystem 145 */ 146 147static void mace_txdma_reset(struct net_device *dev) 148{ 149 struct mace_data *mp = netdev_priv(dev); 150 volatile struct mace *mace = mp->mace; 151 u8 maccc; 152 153 psc_write_word(PSC_ENETWR_CTL, 0x8800); 154 155 maccc = mace->maccc; 156 mace->maccc = maccc & ~ENXMT; 157 158 mp->tx_slot = mp->tx_sloti = 0; 159 mp->tx_count = N_TX_RING; 160 161 psc_write_word(PSC_ENETWR_CTL, 0x0400); 162 mace->maccc = maccc; 163} 164 165/* 166 * Disable DMA 167 */ 168 169static void mace_dma_off(struct net_device *dev) 170{ 171 psc_write_word(PSC_ENETRD_CTL, 0x8800); 172 psc_write_word(PSC_ENETRD_CTL, 0x1000); 173 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100); 174 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100); 175 176 psc_write_word(PSC_ENETWR_CTL, 0x8800); 177 psc_write_word(PSC_ENETWR_CTL, 0x1000); 178 psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100); 179 psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100); 180} 181 182static const struct net_device_ops mace_netdev_ops = { 183 .ndo_open = mace_open, 184 .ndo_stop = mace_close, 185 .ndo_start_xmit = mace_xmit_start, 186 .ndo_tx_timeout = mace_tx_timeout, 187 .ndo_set_multicast_list = mace_set_multicast, 188 .ndo_set_mac_address = mace_set_address, 189 .ndo_change_mtu = eth_change_mtu, 190 .ndo_validate_addr = eth_validate_addr, 191}; 192 193/* 194 * Not really much of a probe. The hardware table tells us if this 195 * model of Macintrash has a MACE (AV macintoshes) 196 */ 197 198static int __devinit mace_probe(struct platform_device *pdev) 199{ 200 int j; 201 struct mace_data *mp; 202 unsigned char *addr; 203 struct net_device *dev; 204 unsigned char checksum = 0; 205 static int found = 0; 206 int err; 207 208 if (found || macintosh_config->ether_type != MAC_ETHER_MACE) 209 return -ENODEV; 210 211 found = 1; /* prevent 'finding' one on every device probe */ 212 213 dev = alloc_etherdev(PRIV_BYTES); 214 if (!dev) 215 return -ENOMEM; 216 217 mp = netdev_priv(dev); 218 219 mp->device = &pdev->dev; 220 SET_NETDEV_DEV(dev, &pdev->dev); 221 222 dev->base_addr = (u32)MACE_BASE; 223 mp->mace = (volatile struct mace *) MACE_BASE; 224 225 dev->irq = IRQ_MAC_MACE; 226 mp->dma_intr = IRQ_MAC_MACE_DMA; 227 228 mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo; 229 230 /* 231 * The PROM contains 8 bytes which total 0xFF when XOR'd 232 * together. Due to the usual peculiar apple brain damage 233 * the bytes are spaced out in a strange boundary and the 234 * bits are reversed. 235 */ 236 237 addr = (void *)MACE_PROM; 238 239 for (j = 0; j < 6; ++j) { 240 u8 v = bitrev8(addr[j<<4]); 241 checksum ^= v; 242 dev->dev_addr[j] = v; 243 } 244 for (; j < 8; ++j) { 245 checksum ^= bitrev8(addr[j<<4]); 246 } 247 248 if (checksum != 0xFF) { 249 free_netdev(dev); 250 return -ENODEV; 251 } 252 253 dev->netdev_ops = &mace_netdev_ops; 254 dev->watchdog_timeo = TX_TIMEOUT; 255 256 printk(KERN_INFO "%s: 68K MACE, hardware address %pM\n", 257 dev->name, dev->dev_addr); 258 259 err = register_netdev(dev); 260 if (!err) 261 return 0; 262 263 free_netdev(dev); 264 return err; 265} 266 267/* 268 * Reset the chip. 269 */ 270 271static void mace_reset(struct net_device *dev) 272{ 273 struct mace_data *mp = netdev_priv(dev); 274 volatile struct mace *mb = mp->mace; 275 int i; 276 277 /* soft-reset the chip */ 278 i = 200; 279 while (--i) { 280 mb->biucc = SWRST; 281 if (mb->biucc & SWRST) { 282 udelay(10); 283 continue; 284 } 285 break; 286 } 287 if (!i) { 288 printk(KERN_ERR "macmace: cannot reset chip!\n"); 289 return; 290 } 291 292 mb->maccc = 0; /* turn off tx, rx */ 293 mb->imr = 0xFF; /* disable all intrs for now */ 294 i = mb->ir; 295 296 mb->biucc = XMTSP_64; 297 mb->utr = RTRD; 298 mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU; 299 300 mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */ 301 mb->rcvfc = 0; 302 303 /* load up the hardware address */ 304 __mace_set_address(dev, dev->dev_addr); 305 306 /* clear the multicast filter */ 307 if (mp->chipid == BROKEN_ADDRCHG_REV) 308 mb->iac = LOGADDR; 309 else { 310 mb->iac = ADDRCHG | LOGADDR; 311 while ((mb->iac & ADDRCHG) != 0) 312 ; 313 } 314 for (i = 0; i < 8; ++i) 315 mb->ladrf = 0; 316 317 /* done changing address */ 318 if (mp->chipid != BROKEN_ADDRCHG_REV) 319 mb->iac = 0; 320 321 mb->plscc = PORTSEL_AUI; 322} 323 324/* 325 * Load the address on a mace controller. 326 */ 327 328static void __mace_set_address(struct net_device *dev, void *addr) 329{ 330 struct mace_data *mp = netdev_priv(dev); 331 volatile struct mace *mb = mp->mace; 332 unsigned char *p = addr; 333 int i; 334 335 /* load up the hardware address */ 336 if (mp->chipid == BROKEN_ADDRCHG_REV) 337 mb->iac = PHYADDR; 338 else { 339 mb->iac = ADDRCHG | PHYADDR; 340 while ((mb->iac & ADDRCHG) != 0) 341 ; 342 } 343 for (i = 0; i < 6; ++i) 344 mb->padr = dev->dev_addr[i] = p[i]; 345 if (mp->chipid != BROKEN_ADDRCHG_REV) 346 mb->iac = 0; 347} 348 349static int mace_set_address(struct net_device *dev, void *addr) 350{ 351 struct mace_data *mp = netdev_priv(dev); 352 volatile struct mace *mb = mp->mace; 353 unsigned long flags; 354 u8 maccc; 355 356 local_irq_save(flags); 357 358 maccc = mb->maccc; 359 360 __mace_set_address(dev, addr); 361 362 mb->maccc = maccc; 363 364 local_irq_restore(flags); 365 366 return 0; 367} 368 369/* 370 * Open the Macintosh MACE. Most of this is playing with the DMA 371 * engine. The ethernet chip is quite friendly. 372 */ 373 374static int mace_open(struct net_device *dev) 375{ 376 struct mace_data *mp = netdev_priv(dev); 377 volatile struct mace *mb = mp->mace; 378 379 /* reset the chip */ 380 mace_reset(dev); 381 382 if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) { 383 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq); 384 return -EAGAIN; 385 } 386 if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) { 387 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr); 388 free_irq(dev->irq, dev); 389 return -EAGAIN; 390 } 391 392 /* Allocate the DMA ring buffers */ 393 394 mp->tx_ring = dma_alloc_coherent(mp->device, 395 N_TX_RING * MACE_BUFF_SIZE, 396 &mp->tx_ring_phys, GFP_KERNEL); 397 if (mp->tx_ring == NULL) { 398 printk(KERN_ERR "%s: unable to allocate DMA tx buffers\n", dev->name); 399 goto out1; 400 } 401 402 mp->rx_ring = dma_alloc_coherent(mp->device, 403 N_RX_RING * MACE_BUFF_SIZE, 404 &mp->rx_ring_phys, GFP_KERNEL); 405 if (mp->rx_ring == NULL) { 406 printk(KERN_ERR "%s: unable to allocate DMA rx buffers\n", dev->name); 407 goto out2; 408 } 409 410 mace_dma_off(dev); 411 412 /* Not sure what these do */ 413 414 psc_write_word(PSC_ENETWR_CTL, 0x9000); 415 psc_write_word(PSC_ENETRD_CTL, 0x9000); 416 psc_write_word(PSC_ENETWR_CTL, 0x0400); 417 psc_write_word(PSC_ENETRD_CTL, 0x0400); 418 419 mace_rxdma_reset(dev); 420 mace_txdma_reset(dev); 421 422 /* turn it on! */ 423 mb->maccc = ENXMT | ENRCV; 424 /* enable all interrupts except receive interrupts */ 425 mb->imr = RCVINT; 426 return 0; 427 428out2: 429 dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, 430 mp->tx_ring, mp->tx_ring_phys); 431out1: 432 free_irq(dev->irq, dev); 433 free_irq(mp->dma_intr, dev); 434 return -ENOMEM; 435} 436 437/* 438 * Shut down the mace and its interrupt channel 439 */ 440 441static int mace_close(struct net_device *dev) 442{ 443 struct mace_data *mp = netdev_priv(dev); 444 volatile struct mace *mb = mp->mace; 445 446 mb->maccc = 0; /* disable rx and tx */ 447 mb->imr = 0xFF; /* disable all irqs */ 448 mace_dma_off(dev); /* disable rx and tx dma */ 449 450 return 0; 451} 452 453/* 454 * Transmit a frame 455 */ 456 457static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) 458{ 459 struct mace_data *mp = netdev_priv(dev); 460 unsigned long flags; 461 462 /* Stop the queue since there's only the one buffer */ 463 464 local_irq_save(flags); 465 netif_stop_queue(dev); 466 if (!mp->tx_count) { 467 printk(KERN_ERR "macmace: tx queue running but no free buffers.\n"); 468 local_irq_restore(flags); 469 return NETDEV_TX_BUSY; 470 } 471 mp->tx_count--; 472 local_irq_restore(flags); 473 474 dev->stats.tx_packets++; 475 dev->stats.tx_bytes += skb->len; 476 477 /* We need to copy into our xmit buffer to take care of alignment and caching issues */ 478 skb_copy_from_linear_data(skb, mp->tx_ring, skb->len); 479 480 /* load the Tx DMA and fire it off */ 481 482 psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys); 483 psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len); 484 psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800); 485 486 mp->tx_slot ^= 0x10; 487 488 dev_kfree_skb(skb); 489 490 return NETDEV_TX_OK; 491} 492 493static void mace_set_multicast(struct net_device *dev) 494{ 495 struct mace_data *mp = netdev_priv(dev); 496 volatile struct mace *mb = mp->mace; 497 int i; 498 u32 crc; 499 u8 maccc; 500 unsigned long flags; 501 502 local_irq_save(flags); 503 maccc = mb->maccc; 504 mb->maccc &= ~PROM; 505 506 if (dev->flags & IFF_PROMISC) { 507 mb->maccc |= PROM; 508 } else { 509 unsigned char multicast_filter[8]; 510 struct netdev_hw_addr *ha; 511 512 if (dev->flags & IFF_ALLMULTI) { 513 for (i = 0; i < 8; i++) { 514 multicast_filter[i] = 0xFF; 515 } 516 } else { 517 for (i = 0; i < 8; i++) 518 multicast_filter[i] = 0; 519 netdev_for_each_mc_addr(ha, dev) { 520 crc = ether_crc_le(6, ha->addr); 521 /* bit number in multicast_filter */ 522 i = crc >> 26; 523 multicast_filter[i >> 3] |= 1 << (i & 7); 524 } 525 } 526 527 if (mp->chipid == BROKEN_ADDRCHG_REV) 528 mb->iac = LOGADDR; 529 else { 530 mb->iac = ADDRCHG | LOGADDR; 531 while ((mb->iac & ADDRCHG) != 0) 532 ; 533 } 534 for (i = 0; i < 8; ++i) 535 mb->ladrf = multicast_filter[i]; 536 if (mp->chipid != BROKEN_ADDRCHG_REV) 537 mb->iac = 0; 538 } 539 540 mb->maccc = maccc; 541 local_irq_restore(flags); 542} 543 544static void mace_handle_misc_intrs(struct net_device *dev, int intr) 545{ 546 struct mace_data *mp = netdev_priv(dev); 547 volatile struct mace *mb = mp->mace; 548 static int mace_babbles, mace_jabbers; 549 550 if (intr & MPCO) 551 dev->stats.rx_missed_errors += 256; 552 dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */ 553 if (intr & RNTPCO) 554 dev->stats.rx_length_errors += 256; 555 dev->stats.rx_length_errors += mb->rntpc; /* reading clears it */ 556 if (intr & CERR) 557 ++dev->stats.tx_heartbeat_errors; 558 if (intr & BABBLE) 559 if (mace_babbles++ < 4) 560 printk(KERN_DEBUG "macmace: babbling transmitter\n"); 561 if (intr & JABBER) 562 if (mace_jabbers++ < 4) 563 printk(KERN_DEBUG "macmace: jabbering transceiver\n"); 564} 565 566static irqreturn_t mace_interrupt(int irq, void *dev_id) 567{ 568 struct net_device *dev = (struct net_device *) dev_id; 569 struct mace_data *mp = netdev_priv(dev); 570 volatile struct mace *mb = mp->mace; 571 int intr, fs; 572 unsigned long flags; 573 574 /* don't want the dma interrupt handler to fire */ 575 local_irq_save(flags); 576 577 intr = mb->ir; /* read interrupt register */ 578 mace_handle_misc_intrs(dev, intr); 579 580 if (intr & XMTINT) { 581 fs = mb->xmtfs; 582 if ((fs & XMTSV) == 0) { 583 printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs); 584 mace_reset(dev); 585 } 586 /* dma should have finished */ 587 if (!mp->tx_count) { 588 printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs); 589 } 590 /* Update stats */ 591 if (fs & (UFLO|LCOL|LCAR|RTRY)) { 592 ++dev->stats.tx_errors; 593 if (fs & LCAR) 594 ++dev->stats.tx_carrier_errors; 595 else if (fs & (UFLO|LCOL|RTRY)) { 596 ++dev->stats.tx_aborted_errors; 597 if (mb->xmtfs & UFLO) { 598 printk(KERN_ERR "%s: DMA underrun.\n", dev->name); 599 dev->stats.tx_fifo_errors++; 600 mace_txdma_reset(dev); 601 } 602 } 603 } 604 } 605 606 if (mp->tx_count) 607 netif_wake_queue(dev); 608 609 local_irq_restore(flags); 610 611 return IRQ_HANDLED; 612} 613 614static void mace_tx_timeout(struct net_device *dev) 615{ 616 struct mace_data *mp = netdev_priv(dev); 617 volatile struct mace *mb = mp->mace; 618 unsigned long flags; 619 620 local_irq_save(flags); 621 622 /* turn off both tx and rx and reset the chip */ 623 mb->maccc = 0; 624 printk(KERN_ERR "macmace: transmit timeout - resetting\n"); 625 mace_txdma_reset(dev); 626 mace_reset(dev); 627 628 /* restart rx dma */ 629 mace_rxdma_reset(dev); 630 631 mp->tx_count = N_TX_RING; 632 netif_wake_queue(dev); 633 634 /* turn it on! */ 635 mb->maccc = ENXMT | ENRCV; 636 /* enable all interrupts except receive interrupts */ 637 mb->imr = RCVINT; 638 639 local_irq_restore(flags); 640} 641 642/* 643 * Handle a newly arrived frame 644 */ 645 646static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) 647{ 648 struct sk_buff *skb; 649 unsigned int frame_status = mf->rcvsts; 650 651 if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) { 652 dev->stats.rx_errors++; 653 if (frame_status & RS_OFLO) { 654 printk(KERN_DEBUG "%s: fifo overflow.\n", dev->name); 655 dev->stats.rx_fifo_errors++; 656 } 657 if (frame_status & RS_CLSN) 658 dev->stats.collisions++; 659 if (frame_status & RS_FRAMERR) 660 dev->stats.rx_frame_errors++; 661 if (frame_status & RS_FCSERR) 662 dev->stats.rx_crc_errors++; 663 } else { 664 unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 ); 665 666 skb = dev_alloc_skb(frame_length + 2); 667 if (!skb) { 668 dev->stats.rx_dropped++; 669 return; 670 } 671 skb_reserve(skb, 2); 672 memcpy(skb_put(skb, frame_length), mf->data, frame_length); 673 674 skb->protocol = eth_type_trans(skb, dev); 675 netif_rx(skb); 676 dev->stats.rx_packets++; 677 dev->stats.rx_bytes += frame_length; 678 } 679} 680 681/* 682 * The PSC has passed us a DMA interrupt event. 683 */ 684 685static irqreturn_t mace_dma_intr(int irq, void *dev_id) 686{ 687 struct net_device *dev = (struct net_device *) dev_id; 688 struct mace_data *mp = netdev_priv(dev); 689 int left, head; 690 u16 status; 691 u32 baka; 692 693 /* Not sure what this does */ 694 695 while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY)); 696 if (!(baka & 0x60000000)) return IRQ_NONE; 697 698 /* 699 * Process the read queue 700 */ 701 702 status = psc_read_word(PSC_ENETRD_CTL); 703 704 if (status & 0x2000) { 705 mace_rxdma_reset(dev); 706 } else if (status & 0x0100) { 707 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100); 708 709 left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot); 710 head = N_RX_RING - left; 711 712 /* Loop through the ring buffer and process new packages */ 713 714 while (mp->rx_tail < head) { 715 mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring 716 + (mp->rx_tail * MACE_BUFF_SIZE))); 717 mp->rx_tail++; 718 } 719 720 /* If we're out of buffers in this ring then switch to */ 721 /* the other set, otherwise just reactivate this one. */ 722 723 if (!left) { 724 mace_load_rxdma_base(dev, mp->rx_slot); 725 mp->rx_slot ^= 0x10; 726 } else { 727 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800); 728 } 729 } 730 731 /* 732 * Process the write queue 733 */ 734 735 status = psc_read_word(PSC_ENETWR_CTL); 736 737 if (status & 0x2000) { 738 mace_txdma_reset(dev); 739 } else if (status & 0x0100) { 740 psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100); 741 mp->tx_sloti ^= 0x10; 742 mp->tx_count++; 743 } 744 return IRQ_HANDLED; 745} 746 747MODULE_LICENSE("GPL"); 748MODULE_DESCRIPTION("Macintosh MACE ethernet driver"); 749MODULE_ALIAS("platform:macmace"); 750 751static int __devexit mac_mace_device_remove (struct platform_device *pdev) 752{ 753 struct net_device *dev = platform_get_drvdata(pdev); 754 struct mace_data *mp = netdev_priv(dev); 755 756 unregister_netdev(dev); 757 758 free_irq(dev->irq, dev); 759 free_irq(IRQ_MAC_MACE_DMA, dev); 760 761 dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE, 762 mp->rx_ring, mp->rx_ring_phys); 763 dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, 764 mp->tx_ring, mp->tx_ring_phys); 765 766 free_netdev(dev); 767 768 return 0; 769} 770 771static struct platform_driver mac_mace_driver = { 772 .probe = mace_probe, 773 .remove = __devexit_p(mac_mace_device_remove), 774 .driver = { 775 .name = mac_mace_string, 776 .owner = THIS_MODULE, 777 }, 778}; 779 780static int __init mac_mace_init_module(void) 781{ 782 if (!MACH_IS_MAC) 783 return -ENODEV; 784 785 return platform_driver_register(&mac_mace_driver); 786} 787 788static void __exit mac_mace_cleanup_module(void) 789{ 790 platform_driver_unregister(&mac_mace_driver); 791} 792 793module_init(mac_mace_init_module); 794module_exit(mac_mace_cleanup_module); 795