1/******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2010 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#include <linux/pci.h> 29#include <linux/delay.h> 30#include <linux/sched.h> 31 32#include "ixgbe.h" 33#include "ixgbe_phy.h" 34 35#define IXGBE_82598_MAX_TX_QUEUES 32 36#define IXGBE_82598_MAX_RX_QUEUES 64 37#define IXGBE_82598_RAR_ENTRIES 16 38#define IXGBE_82598_MC_TBL_SIZE 128 39#define IXGBE_82598_VFT_TBL_SIZE 128 40 41static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 42 ixgbe_link_speed *speed, 43 bool *autoneg); 44static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 45 ixgbe_link_speed speed, 46 bool autoneg, 47 bool autoneg_wait_to_complete); 48static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 49 u8 *eeprom_data); 50 51/** 52 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 53 * @hw: pointer to the HW structure 54 * 55 * The defaults for 82598 should be in the range of 50us to 50ms, 56 * however the hardware default for these parts is 500us to 1ms which is less 57 * than the 10ms recommended by the pci-e spec. To address this we need to 58 * increase the value to either 10ms to 250ms for capability version 1 config, 59 * or 16ms to 55ms for version 2. 60 **/ 61static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 62{ 63 struct ixgbe_adapter *adapter = hw->back; 64 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 65 u16 pcie_devctl2; 66 67 /* only take action if timeout value is defaulted to 0 */ 68 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 69 goto out; 70 71 /* 72 * if capababilities version is type 1 we can write the 73 * timeout of 10ms to 250ms through the GCR register 74 */ 75 if (!(gcr & IXGBE_GCR_CAP_VER2)) { 76 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 77 goto out; 78 } 79 80 /* 81 * for version 2 capabilities we need to write the config space 82 * directly in order to set the completion timeout value for 83 * 16ms to 55ms 84 */ 85 pci_read_config_word(adapter->pdev, 86 IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); 87 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 88 pci_write_config_word(adapter->pdev, 89 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 90out: 91 /* disable completion timeout resend */ 92 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 93 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 94} 95 96/** 97 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count 98 * @hw: pointer to hardware structure 99 * 100 * Read PCIe configuration space, and get the MSI-X vector count from 101 * the capabilities table. 102 **/ 103static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) 104{ 105 struct ixgbe_adapter *adapter = hw->back; 106 u16 msix_count; 107 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS, 108 &msix_count); 109 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 110 111 /* MSI-X count is zero-based in HW, so increment to give proper value */ 112 msix_count++; 113 114 return msix_count; 115} 116 117/** 118 */ 119static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 120{ 121 struct ixgbe_mac_info *mac = &hw->mac; 122 123 /* Call PHY identify routine to get the phy type */ 124 ixgbe_identify_phy_generic(hw); 125 126 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 127 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 128 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 129 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 130 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 131 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); 132 133 return 0; 134} 135 136/** 137 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 138 * @hw: pointer to hardware structure 139 * 140 * Initialize any function pointers that were not able to be 141 * set during get_invariants because the PHY/SFP type was 142 * not known. Perform the SFP init if necessary. 143 * 144 **/ 145static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 146{ 147 struct ixgbe_mac_info *mac = &hw->mac; 148 struct ixgbe_phy_info *phy = &hw->phy; 149 s32 ret_val = 0; 150 u16 list_offset, data_offset; 151 152 /* Identify the PHY */ 153 phy->ops.identify(hw); 154 155 /* Overwrite the link function pointers if copper PHY */ 156 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 157 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 158 mac->ops.get_link_capabilities = 159 &ixgbe_get_copper_link_capabilities_82598; 160 } 161 162 switch (hw->phy.type) { 163 case ixgbe_phy_tn: 164 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 165 phy->ops.get_firmware_version = 166 &ixgbe_get_phy_firmware_version_tnx; 167 break; 168 case ixgbe_phy_nl: 169 phy->ops.reset = &ixgbe_reset_phy_nl; 170 171 /* Call SFP+ identify routine to get the SFP+ module type */ 172 ret_val = phy->ops.identify_sfp(hw); 173 if (ret_val != 0) 174 goto out; 175 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 176 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 177 goto out; 178 } 179 180 /* Check to see if SFP+ module is supported */ 181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 182 &list_offset, 183 &data_offset); 184 if (ret_val != 0) { 185 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 186 goto out; 187 } 188 break; 189 default: 190 break; 191 } 192 193out: 194 return ret_val; 195} 196 197/** 198 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 199 * @hw: pointer to hardware structure 200 * 201 * Starts the hardware using the generic start_hw function. 202 * Then set pcie completion timeout 203 **/ 204static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 205{ 206 s32 ret_val = 0; 207 208 ret_val = ixgbe_start_hw_generic(hw); 209 210 /* set the completion timeout for interface */ 211 if (ret_val == 0) 212 ixgbe_set_pcie_completion_timeout(hw); 213 214 return ret_val; 215} 216 217/** 218 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 219 * @hw: pointer to hardware structure 220 * @speed: pointer to link speed 221 * @autoneg: boolean auto-negotiation value 222 * 223 * Determines the link capabilities by reading the AUTOC register. 224 **/ 225static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 226 ixgbe_link_speed *speed, 227 bool *autoneg) 228{ 229 s32 status = 0; 230 u32 autoc = 0; 231 232 /* 233 * Determine link capabilities based on the stored value of AUTOC, 234 * which represents EEPROM defaults. If AUTOC value has not been 235 * stored, use the current register value. 236 */ 237 if (hw->mac.orig_link_settings_stored) 238 autoc = hw->mac.orig_autoc; 239 else 240 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 241 242 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 243 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 244 *speed = IXGBE_LINK_SPEED_1GB_FULL; 245 *autoneg = false; 246 break; 247 248 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 249 *speed = IXGBE_LINK_SPEED_10GB_FULL; 250 *autoneg = false; 251 break; 252 253 case IXGBE_AUTOC_LMS_1G_AN: 254 *speed = IXGBE_LINK_SPEED_1GB_FULL; 255 *autoneg = true; 256 break; 257 258 case IXGBE_AUTOC_LMS_KX4_AN: 259 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 260 *speed = IXGBE_LINK_SPEED_UNKNOWN; 261 if (autoc & IXGBE_AUTOC_KX4_SUPP) 262 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 263 if (autoc & IXGBE_AUTOC_KX_SUPP) 264 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 265 *autoneg = true; 266 break; 267 268 default: 269 status = IXGBE_ERR_LINK_SETUP; 270 break; 271 } 272 273 return status; 274} 275 276/** 277 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities 278 * @hw: pointer to hardware structure 279 * @speed: pointer to link speed 280 * @autoneg: boolean auto-negotiation value 281 * 282 * Determines the link capabilities by reading the AUTOC register. 283 **/ 284static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, 285 ixgbe_link_speed *speed, 286 bool *autoneg) 287{ 288 s32 status = IXGBE_ERR_LINK_SETUP; 289 u16 speed_ability; 290 291 *speed = 0; 292 *autoneg = true; 293 294 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 295 &speed_ability); 296 297 if (status == 0) { 298 if (speed_ability & MDIO_SPEED_10G) 299 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 300 if (speed_ability & MDIO_PMA_SPEED_1000) 301 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 302 } 303 304 return status; 305} 306 307/** 308 * ixgbe_get_media_type_82598 - Determines media type 309 * @hw: pointer to hardware structure 310 * 311 * Returns the media type (fiber, copper, backplane) 312 **/ 313static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 314{ 315 enum ixgbe_media_type media_type; 316 317 /* Media type for I82598 is based on device ID */ 318 switch (hw->device_id) { 319 case IXGBE_DEV_ID_82598: 320 case IXGBE_DEV_ID_82598_BX: 321 media_type = ixgbe_media_type_backplane; 322 break; 323 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 324 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 325 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 326 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 327 case IXGBE_DEV_ID_82598EB_XF_LR: 328 case IXGBE_DEV_ID_82598EB_SFP_LOM: 329 media_type = ixgbe_media_type_fiber; 330 break; 331 case IXGBE_DEV_ID_82598EB_CX4: 332 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 333 media_type = ixgbe_media_type_cx4; 334 break; 335 case IXGBE_DEV_ID_82598AT: 336 case IXGBE_DEV_ID_82598AT2: 337 media_type = ixgbe_media_type_copper; 338 break; 339 default: 340 media_type = ixgbe_media_type_unknown; 341 break; 342 } 343 344 return media_type; 345} 346 347/** 348 * ixgbe_fc_enable_82598 - Enable flow control 349 * @hw: pointer to hardware structure 350 * @packetbuf_num: packet buffer number (0-7) 351 * 352 * Enable flow control according to the current settings. 353 **/ 354static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 355{ 356 s32 ret_val = 0; 357 u32 fctrl_reg; 358 u32 rmcs_reg; 359 u32 reg; 360 u32 link_speed = 0; 361 bool link_up; 362 363#ifdef CONFIG_DCB 364 if (hw->fc.requested_mode == ixgbe_fc_pfc) 365 goto out; 366 367#endif /* CONFIG_DCB */ 368 /* 369 * On 82598 having Rx FC on causes resets while doing 1G 370 * so if it's on turn it off once we know link_speed. For 371 * more details see 82598 Specification update. 372 */ 373 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 374 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 375 switch (hw->fc.requested_mode) { 376 case ixgbe_fc_full: 377 hw->fc.requested_mode = ixgbe_fc_tx_pause; 378 break; 379 case ixgbe_fc_rx_pause: 380 hw->fc.requested_mode = ixgbe_fc_none; 381 break; 382 default: 383 /* no change */ 384 break; 385 } 386 } 387 388 /* Negotiate the fc mode to use */ 389 ret_val = ixgbe_fc_autoneg(hw); 390 if (ret_val) 391 goto out; 392 393 /* Disable any previous flow control settings */ 394 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 395 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 396 397 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 398 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 399 400 /* 401 * The possible values of fc.current_mode are: 402 * 0: Flow control is completely disabled 403 * 1: Rx flow control is enabled (we can receive pause frames, 404 * but not send pause frames). 405 * 2: Tx flow control is enabled (we can send pause frames but 406 * we do not support receiving pause frames). 407 * 3: Both Rx and Tx flow control (symmetric) are enabled. 408 * other: Invalid. 409#ifdef CONFIG_DCB 410 * 4: Priority Flow Control is enabled. 411#endif 412 */ 413 switch (hw->fc.current_mode) { 414 case ixgbe_fc_none: 415 /* 416 * Flow control is disabled by software override or autoneg. 417 * The code below will actually disable it in the HW. 418 */ 419 break; 420 case ixgbe_fc_rx_pause: 421 /* 422 * Rx Flow control is enabled and Tx Flow control is 423 * disabled by software override. Since there really 424 * isn't a way to advertise that we are capable of RX 425 * Pause ONLY, we will advertise that we support both 426 * symmetric and asymmetric Rx PAUSE. Later, we will 427 * disable the adapter's ability to send PAUSE frames. 428 */ 429 fctrl_reg |= IXGBE_FCTRL_RFCE; 430 break; 431 case ixgbe_fc_tx_pause: 432 /* 433 * Tx Flow control is enabled, and Rx Flow control is 434 * disabled by software override. 435 */ 436 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 437 break; 438 case ixgbe_fc_full: 439 /* Flow control (both Rx and Tx) is enabled by SW override. */ 440 fctrl_reg |= IXGBE_FCTRL_RFCE; 441 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 442 break; 443#ifdef CONFIG_DCB 444 case ixgbe_fc_pfc: 445 goto out; 446 break; 447#endif /* CONFIG_DCB */ 448 default: 449 hw_dbg(hw, "Flow control param set incorrectly\n"); 450 ret_val = IXGBE_ERR_CONFIG; 451 goto out; 452 break; 453 } 454 455 /* Set 802.3x based flow control settings. */ 456 fctrl_reg |= IXGBE_FCTRL_DPF; 457 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 458 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 459 460 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 461 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 462 if (hw->fc.send_xon) { 463 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 464 (hw->fc.low_water | IXGBE_FCRTL_XONE)); 465 } else { 466 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), 467 hw->fc.low_water); 468 } 469 470 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), 471 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 472 } 473 474 /* Configure pause time (2 TCs per register) */ 475 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 476 if ((packetbuf_num & 1) == 0) 477 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 478 else 479 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 480 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 481 482 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 483 484out: 485 return ret_val; 486} 487 488/** 489 * ixgbe_start_mac_link_82598 - Configures MAC link settings 490 * @hw: pointer to hardware structure 491 * 492 * Configures link settings based on values in the ixgbe_hw struct. 493 * Restarts the link. Performs autonegotiation if needed. 494 **/ 495static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 496 bool autoneg_wait_to_complete) 497{ 498 u32 autoc_reg; 499 u32 links_reg; 500 u32 i; 501 s32 status = 0; 502 503 /* Restart link */ 504 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 505 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 506 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 507 508 /* Only poll for autoneg to complete if specified to do so */ 509 if (autoneg_wait_to_complete) { 510 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 511 IXGBE_AUTOC_LMS_KX4_AN || 512 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 513 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 514 links_reg = 0; /* Just in case Autoneg time = 0 */ 515 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 516 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 517 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 518 break; 519 msleep(100); 520 } 521 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 522 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 523 hw_dbg(hw, "Autonegotiation did not complete.\n"); 524 } 525 } 526 } 527 528 /* Add delay to filter out noises during initial link setup */ 529 msleep(50); 530 531 return status; 532} 533 534/** 535 * ixgbe_validate_link_ready - Function looks for phy link 536 * @hw: pointer to hardware structure 537 * 538 * Function indicates success when phy link is available. If phy is not ready 539 * within 5 seconds of MAC indicating link, the function returns error. 540 **/ 541static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 542{ 543 u32 timeout; 544 u16 an_reg; 545 546 if (hw->device_id != IXGBE_DEV_ID_82598AT2) 547 return 0; 548 549 for (timeout = 0; 550 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 551 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); 552 553 if ((an_reg & MDIO_AN_STAT1_COMPLETE) && 554 (an_reg & MDIO_STAT1_LSTATUS)) 555 break; 556 557 msleep(100); 558 } 559 560 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 561 hw_dbg(hw, "Link was indicated but link is down\n"); 562 return IXGBE_ERR_LINK_SETUP; 563 } 564 565 return 0; 566} 567 568/** 569 * ixgbe_check_mac_link_82598 - Get link/speed status 570 * @hw: pointer to hardware structure 571 * @speed: pointer to link speed 572 * @link_up: true is link is up, false otherwise 573 * @link_up_wait_to_complete: bool used to wait for link up or not 574 * 575 * Reads the links register to determine if link is up and the current speed 576 **/ 577static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 578 ixgbe_link_speed *speed, bool *link_up, 579 bool link_up_wait_to_complete) 580{ 581 u32 links_reg; 582 u32 i; 583 u16 link_reg, adapt_comp_reg; 584 585 /* 586 * SERDES PHY requires us to read link status from register 0xC79F. 587 * Bit 0 set indicates link is up/ready; clear indicates link down. 588 * 0xC00C is read to check that the XAUI lanes are active. Bit 0 589 * clear indicates active; set indicates inactive. 590 */ 591 if (hw->phy.type == ixgbe_phy_nl) { 592 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 593 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 594 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, 595 &adapt_comp_reg); 596 if (link_up_wait_to_complete) { 597 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 598 if ((link_reg & 1) && 599 ((adapt_comp_reg & 1) == 0)) { 600 *link_up = true; 601 break; 602 } else { 603 *link_up = false; 604 } 605 msleep(100); 606 hw->phy.ops.read_reg(hw, 0xC79F, 607 MDIO_MMD_PMAPMD, 608 &link_reg); 609 hw->phy.ops.read_reg(hw, 0xC00C, 610 MDIO_MMD_PMAPMD, 611 &adapt_comp_reg); 612 } 613 } else { 614 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 615 *link_up = true; 616 else 617 *link_up = false; 618 } 619 620 if (*link_up == false) 621 goto out; 622 } 623 624 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 625 if (link_up_wait_to_complete) { 626 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 627 if (links_reg & IXGBE_LINKS_UP) { 628 *link_up = true; 629 break; 630 } else { 631 *link_up = false; 632 } 633 msleep(100); 634 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 635 } 636 } else { 637 if (links_reg & IXGBE_LINKS_UP) 638 *link_up = true; 639 else 640 *link_up = false; 641 } 642 643 if (links_reg & IXGBE_LINKS_SPEED) 644 *speed = IXGBE_LINK_SPEED_10GB_FULL; 645 else 646 *speed = IXGBE_LINK_SPEED_1GB_FULL; 647 648 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) && 649 (ixgbe_validate_link_ready(hw) != 0)) 650 *link_up = false; 651 652 /* if link is down, zero out the current_mode */ 653 if (*link_up == false) { 654 hw->fc.current_mode = ixgbe_fc_none; 655 hw->fc.fc_was_autonegged = false; 656 } 657out: 658 return 0; 659} 660 661 662/** 663 * ixgbe_setup_mac_link_82598 - Set MAC link speed 664 * @hw: pointer to hardware structure 665 * @speed: new link speed 666 * @autoneg: true if auto-negotiation enabled 667 * @autoneg_wait_to_complete: true if waiting is needed to complete 668 * 669 * Set the link speed in the AUTOC register and restarts link. 670 **/ 671static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 672 ixgbe_link_speed speed, bool autoneg, 673 bool autoneg_wait_to_complete) 674{ 675 s32 status = 0; 676 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 677 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 678 u32 autoc = curr_autoc; 679 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 680 681 /* Check to see if speed passed in is supported. */ 682 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); 683 speed &= link_capabilities; 684 685 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 686 status = IXGBE_ERR_LINK_SETUP; 687 688 /* Set KX4/KX support according to speed requested */ 689 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 690 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 691 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 692 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 693 autoc |= IXGBE_AUTOC_KX4_SUPP; 694 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 695 autoc |= IXGBE_AUTOC_KX_SUPP; 696 if (autoc != curr_autoc) 697 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 698 } 699 700 if (status == 0) { 701 /* 702 * Setup and restart the link based on the new values in 703 * ixgbe_hw This will write the AUTOC register based on the new 704 * stored values 705 */ 706 status = ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 707 } 708 709 return status; 710} 711 712 713/** 714 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 715 * @hw: pointer to hardware structure 716 * @speed: new link speed 717 * @autoneg: true if autonegotiation enabled 718 * @autoneg_wait_to_complete: true if waiting is needed to complete 719 * 720 * Sets the link speed in the AUTOC register in the MAC and restarts link. 721 **/ 722static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 723 ixgbe_link_speed speed, 724 bool autoneg, 725 bool autoneg_wait_to_complete) 726{ 727 s32 status; 728 729 /* Setup the PHY according to input speed */ 730 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 731 autoneg_wait_to_complete); 732 733 /* Set up MAC */ 734 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 735 736 return status; 737} 738 739/** 740 * ixgbe_reset_hw_82598 - Performs hardware reset 741 * @hw: pointer to hardware structure 742 * 743 * Resets the hardware by resetting the transmit and receive units, masks and 744 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 745 * reset. 746 **/ 747static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 748{ 749 s32 status = 0; 750 s32 phy_status = 0; 751 u32 ctrl; 752 u32 gheccr; 753 u32 i; 754 u32 autoc; 755 u8 analog_val; 756 757 /* Call adapter stop to disable tx/rx and clear interrupts */ 758 hw->mac.ops.stop_adapter(hw); 759 760 /* 761 * Power up the Atlas Tx lanes if they are currently powered down. 762 * Atlas Tx lanes are powered down for MAC loopback tests, but 763 * they are not automatically restored on reset. 764 */ 765 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 766 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 767 /* Enable Tx Atlas so packets can be transmitted again */ 768 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 769 &analog_val); 770 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 771 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 772 analog_val); 773 774 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 775 &analog_val); 776 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 777 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 778 analog_val); 779 780 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 781 &analog_val); 782 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 783 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 784 analog_val); 785 786 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 787 &analog_val); 788 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 789 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 790 analog_val); 791 } 792 793 /* Reset PHY */ 794 if (hw->phy.reset_disable == false) { 795 /* PHY ops must be identified and initialized prior to reset */ 796 797 /* Init PHY and function pointers, perform SFP setup */ 798 phy_status = hw->phy.ops.init(hw); 799 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 800 goto reset_hw_out; 801 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 802 goto no_phy_reset; 803 804 805 hw->phy.ops.reset(hw); 806 } 807 808no_phy_reset: 809 /* 810 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 811 * access and verify no pending requests before reset 812 */ 813 status = ixgbe_disable_pcie_master(hw); 814 if (status != 0) { 815 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 816 hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); 817 } 818 819 /* 820 * Issue global reset to the MAC. This needs to be a SW reset. 821 * If link reset is used, it might reset the MAC when mng is using it 822 */ 823 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 824 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); 825 IXGBE_WRITE_FLUSH(hw); 826 827 /* Poll for reset bit to self-clear indicating reset is complete */ 828 for (i = 0; i < 10; i++) { 829 udelay(1); 830 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 831 if (!(ctrl & IXGBE_CTRL_RST)) 832 break; 833 } 834 if (ctrl & IXGBE_CTRL_RST) { 835 status = IXGBE_ERR_RESET_FAILED; 836 hw_dbg(hw, "Reset polling failed to complete.\n"); 837 } 838 839 msleep(50); 840 841 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 842 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 843 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 844 845 /* 846 * Store the original AUTOC value if it has not been 847 * stored off yet. Otherwise restore the stored original 848 * AUTOC value since the reset operation sets back to deaults. 849 */ 850 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 851 if (hw->mac.orig_link_settings_stored == false) { 852 hw->mac.orig_autoc = autoc; 853 hw->mac.orig_link_settings_stored = true; 854 } else if (autoc != hw->mac.orig_autoc) { 855 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 856 } 857 858 /* 859 * Store MAC address from RAR0, clear receive address registers, and 860 * clear the multicast table 861 */ 862 hw->mac.ops.init_rx_addrs(hw); 863 864 /* Store the permanent mac address */ 865 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 866 867reset_hw_out: 868 if (phy_status) 869 status = phy_status; 870 871 return status; 872} 873 874/** 875 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 876 * @hw: pointer to hardware struct 877 * @rar: receive address register index to associate with a VMDq index 878 * @vmdq: VMDq set index 879 **/ 880static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 881{ 882 u32 rar_high; 883 884 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 885 rar_high &= ~IXGBE_RAH_VIND_MASK; 886 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 887 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 888 return 0; 889} 890 891/** 892 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 893 * @hw: pointer to hardware struct 894 * @rar: receive address register index to associate with a VMDq index 895 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 896 **/ 897static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 898{ 899 u32 rar_high; 900 u32 rar_entries = hw->mac.num_rar_entries; 901 902 if (rar < rar_entries) { 903 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 904 if (rar_high & IXGBE_RAH_VIND_MASK) { 905 rar_high &= ~IXGBE_RAH_VIND_MASK; 906 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 907 } 908 } else { 909 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 910 } 911 912 return 0; 913} 914 915/** 916 * ixgbe_set_vfta_82598 - Set VLAN filter table 917 * @hw: pointer to hardware structure 918 * @vlan: VLAN id to write to VLAN filter 919 * @vind: VMDq output index that maps queue to VLAN id in VFTA 920 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 921 * 922 * Turn on/off specified VLAN in the VLAN filter table. 923 **/ 924static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 925 bool vlan_on) 926{ 927 u32 regindex; 928 u32 bitindex; 929 u32 bits; 930 u32 vftabyte; 931 932 if (vlan > 4095) 933 return IXGBE_ERR_PARAM; 934 935 /* Determine 32-bit word position in array */ 936 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 937 938 /* Determine the location of the (VMD) queue index */ 939 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 940 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 941 942 /* Set the nibble for VMD queue index */ 943 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 944 bits &= (~(0x0F << bitindex)); 945 bits |= (vind << bitindex); 946 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 947 948 /* Determine the location of the bit for this VLAN id */ 949 bitindex = vlan & 0x1F; /* lower five bits */ 950 951 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 952 if (vlan_on) 953 /* Turn on this VLAN id */ 954 bits |= (1 << bitindex); 955 else 956 /* Turn off this VLAN id */ 957 bits &= ~(1 << bitindex); 958 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 959 960 return 0; 961} 962 963/** 964 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 965 * @hw: pointer to hardware structure 966 * 967 * Clears the VLAN filer table, and the VMDq index associated with the filter 968 **/ 969static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 970{ 971 u32 offset; 972 u32 vlanbyte; 973 974 for (offset = 0; offset < hw->mac.vft_size; offset++) 975 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 976 977 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 978 for (offset = 0; offset < hw->mac.vft_size; offset++) 979 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 980 0); 981 982 return 0; 983} 984 985/** 986 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 987 * @hw: pointer to hardware structure 988 * @reg: analog register to read 989 * @val: read value 990 * 991 * Performs read operation to Atlas analog register specified. 992 **/ 993static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 994{ 995 u32 atlas_ctl; 996 997 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 998 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 999 IXGBE_WRITE_FLUSH(hw); 1000 udelay(10); 1001 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1002 *val = (u8)atlas_ctl; 1003 1004 return 0; 1005} 1006 1007/** 1008 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1009 * @hw: pointer to hardware structure 1010 * @reg: atlas register to write 1011 * @val: value to write 1012 * 1013 * Performs write operation to Atlas analog register specified. 1014 **/ 1015static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 1016{ 1017 u32 atlas_ctl; 1018 1019 atlas_ctl = (reg << 8) | val; 1020 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1021 IXGBE_WRITE_FLUSH(hw); 1022 udelay(10); 1023 1024 return 0; 1025} 1026 1027/** 1028 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module 1029 * over I2C interface through an intermediate phy. 1030 * @hw: pointer to hardware structure 1031 * @byte_offset: EEPROM byte offset to read 1032 * @eeprom_data: value read 1033 * 1034 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1035 **/ 1036static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1037 u8 *eeprom_data) 1038{ 1039 s32 status = 0; 1040 u16 sfp_addr = 0; 1041 u16 sfp_data = 0; 1042 u16 sfp_stat = 0; 1043 u32 i; 1044 1045 if (hw->phy.type == ixgbe_phy_nl) { 1046 /* 1047 * phy SDA/SCL registers are at addresses 0xC30A to 1048 * 0xC30D. These registers are used to talk to the SFP+ 1049 * module's EEPROM through the SDA/SCL (I2C) interface. 1050 */ 1051 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 1052 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1053 hw->phy.ops.write_reg(hw, 1054 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1055 MDIO_MMD_PMAPMD, 1056 sfp_addr); 1057 1058 /* Poll status */ 1059 for (i = 0; i < 100; i++) { 1060 hw->phy.ops.read_reg(hw, 1061 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1062 MDIO_MMD_PMAPMD, 1063 &sfp_stat); 1064 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1065 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1066 break; 1067 msleep(10); 1068 } 1069 1070 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1071 hw_dbg(hw, "EEPROM read did not pass.\n"); 1072 status = IXGBE_ERR_SFP_NOT_PRESENT; 1073 goto out; 1074 } 1075 1076 /* Read data */ 1077 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1078 MDIO_MMD_PMAPMD, &sfp_data); 1079 1080 *eeprom_data = (u8)(sfp_data >> 8); 1081 } else { 1082 status = IXGBE_ERR_PHY; 1083 goto out; 1084 } 1085 1086out: 1087 return status; 1088} 1089 1090/** 1091 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1092 * @hw: pointer to hardware structure 1093 * 1094 * Determines physical layer capabilities of the current configuration. 1095 **/ 1096static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1097{ 1098 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1099 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1100 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1101 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1102 u16 ext_ability = 0; 1103 1104 hw->phy.ops.identify(hw); 1105 1106 /* Copper PHY must be checked before AUTOC LMS to determine correct 1107 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1108 if (hw->phy.type == ixgbe_phy_tn || 1109 hw->phy.type == ixgbe_phy_cu_unknown) { 1110 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, 1111 &ext_ability); 1112 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 1113 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1114 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 1115 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1116 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 1117 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1118 goto out; 1119 } 1120 1121 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1122 case IXGBE_AUTOC_LMS_1G_AN: 1123 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1124 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1125 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1126 else 1127 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1128 break; 1129 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1130 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1131 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1132 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1133 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1134 else /* XAUI */ 1135 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1136 break; 1137 case IXGBE_AUTOC_LMS_KX4_AN: 1138 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1139 if (autoc & IXGBE_AUTOC_KX_SUPP) 1140 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1141 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1142 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1143 break; 1144 default: 1145 break; 1146 } 1147 1148 if (hw->phy.type == ixgbe_phy_nl) { 1149 hw->phy.ops.identify_sfp(hw); 1150 1151 switch (hw->phy.sfp_type) { 1152 case ixgbe_sfp_type_da_cu: 1153 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1154 break; 1155 case ixgbe_sfp_type_sr: 1156 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1157 break; 1158 case ixgbe_sfp_type_lr: 1159 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1160 break; 1161 default: 1162 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1163 break; 1164 } 1165 } 1166 1167 switch (hw->device_id) { 1168 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1169 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1170 break; 1171 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1172 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1173 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1174 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1175 break; 1176 case IXGBE_DEV_ID_82598EB_XF_LR: 1177 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1178 break; 1179 default: 1180 break; 1181 } 1182 1183out: 1184 return physical_layer; 1185} 1186 1187static struct ixgbe_mac_operations mac_ops_82598 = { 1188 .init_hw = &ixgbe_init_hw_generic, 1189 .reset_hw = &ixgbe_reset_hw_82598, 1190 .start_hw = &ixgbe_start_hw_82598, 1191 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 1192 .get_media_type = &ixgbe_get_media_type_82598, 1193 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, 1194 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 1195 .get_mac_addr = &ixgbe_get_mac_addr_generic, 1196 .stop_adapter = &ixgbe_stop_adapter_generic, 1197 .get_bus_info = &ixgbe_get_bus_info_generic, 1198 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 1199 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, 1200 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, 1201 .setup_link = &ixgbe_setup_mac_link_82598, 1202 .check_link = &ixgbe_check_mac_link_82598, 1203 .get_link_capabilities = &ixgbe_get_link_capabilities_82598, 1204 .led_on = &ixgbe_led_on_generic, 1205 .led_off = &ixgbe_led_off_generic, 1206 .blink_led_start = &ixgbe_blink_led_start_generic, 1207 .blink_led_stop = &ixgbe_blink_led_stop_generic, 1208 .set_rar = &ixgbe_set_rar_generic, 1209 .clear_rar = &ixgbe_clear_rar_generic, 1210 .set_vmdq = &ixgbe_set_vmdq_82598, 1211 .clear_vmdq = &ixgbe_clear_vmdq_82598, 1212 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 1213 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, 1214 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 1215 .enable_mc = &ixgbe_enable_mc_generic, 1216 .disable_mc = &ixgbe_disable_mc_generic, 1217 .clear_vfta = &ixgbe_clear_vfta_82598, 1218 .set_vfta = &ixgbe_set_vfta_82598, 1219 .fc_enable = &ixgbe_fc_enable_82598, 1220}; 1221 1222static struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1223 .init_params = &ixgbe_init_eeprom_params_generic, 1224 .read = &ixgbe_read_eerd_generic, 1225 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 1226 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 1227}; 1228 1229static struct ixgbe_phy_operations phy_ops_82598 = { 1230 .identify = &ixgbe_identify_phy_generic, 1231 .identify_sfp = &ixgbe_identify_sfp_module_generic, 1232 .init = &ixgbe_init_phy_ops_82598, 1233 .reset = &ixgbe_reset_phy_generic, 1234 .read_reg = &ixgbe_read_phy_reg_generic, 1235 .write_reg = &ixgbe_write_phy_reg_generic, 1236 .setup_link = &ixgbe_setup_phy_link_generic, 1237 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 1238 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, 1239 .check_overtemp = &ixgbe_tn_check_overtemp, 1240}; 1241 1242struct ixgbe_info ixgbe_82598_info = { 1243 .mac = ixgbe_mac_82598EB, 1244 .get_invariants = &ixgbe_get_invariants_82598, 1245 .mac_ops = &mac_ops_82598, 1246 .eeprom_ops = &eeprom_ops_82598, 1247 .phy_ops = &phy_ops_82598, 1248}; 1249