1/****************************************************************************/ 2 3/* 4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 5 * processors. 6 * 7 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 8 * (C) Copyright 2000-2001, Lineo (www.lineo.com) 9 */ 10 11/****************************************************************************/ 12#ifndef FEC_H 13#define FEC_H 14/****************************************************************************/ 15 16#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 17 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) 18/* 19 * Just figures, Motorola would have to change the offsets for 20 * registers in the same peripheral device on different models 21 * of the ColdFire! 22 */ 23#define FEC_IEVENT 0x004 /* Interrupt event reg */ 24#define FEC_IMASK 0x008 /* Interrupt mask reg */ 25#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ 26#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ 27#define FEC_ECNTRL 0x024 /* Ethernet control reg */ 28#define FEC_MII_DATA 0x040 /* MII manage frame reg */ 29#define FEC_MII_SPEED 0x044 /* MII speed control reg */ 30#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 31#define FEC_R_CNTRL 0x084 /* Receive control reg */ 32#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 33#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 34#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 35#define FEC_OPD 0x0ec /* Opcode + Pause duration */ 36#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 37#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 38#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 39#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 40#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 41#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 42#define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 43#define FEC_R_DES_START 0x180 /* Receive descriptor ring */ 44#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */ 45#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ 46#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 47#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 48 49#else 50 51#define FEC_ECNTRL 0x000 /* Ethernet control reg */ 52#define FEC_IEVENT 0x004 /* Interrupt even reg */ 53#define FEC_IMASK 0x008 /* Interrupt mask reg */ 54#define FEC_IVEC 0x00c /* Interrupt vec status reg */ 55#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ 56#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ 57#define FEC_MII_DATA 0x040 /* MII manage frame reg */ 58#define FEC_MII_SPEED 0x044 /* MII speed control reg */ 59#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 60#define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 61#define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 62#define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 63#define FEC_R_CNTRL 0x104 /* Receive control reg */ 64#define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 65#define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 66#define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 67#define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 68#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 69#define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 70#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */ 71#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */ 72#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */ 73#define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 74 75#endif /* CONFIG_M5272 */ 76 77 78/* 79 * Define the buffer descriptor structure. 80 */ 81#ifdef CONFIG_ARCH_MXC 82struct bufdesc { 83 unsigned short cbd_datlen; /* Data length */ 84 unsigned short cbd_sc; /* Control and status info */ 85 unsigned long cbd_bufaddr; /* Buffer address */ 86}; 87#else 88struct bufdesc { 89 unsigned short cbd_sc; /* Control and status info */ 90 unsigned short cbd_datlen; /* Data length */ 91 unsigned long cbd_bufaddr; /* Buffer address */ 92}; 93#endif 94 95/* 96 * The following definitions courtesy of commproc.h, which where 97 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 98 */ 99#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ 100#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 101#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 102#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 103#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 104#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 105#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 106#define BD_SC_BR ((ushort)0x0020) /* Break received */ 107#define BD_SC_FR ((ushort)0x0010) /* Framing error */ 108#define BD_SC_PR ((ushort)0x0008) /* Parity error */ 109#define BD_SC_OV ((ushort)0x0002) /* Overrun */ 110#define BD_SC_CD ((ushort)0x0001) /* ?? */ 111 112/* Buffer descriptor control/status used by Ethernet receive. 113*/ 114#define BD_ENET_RX_EMPTY ((ushort)0x8000) 115#define BD_ENET_RX_WRAP ((ushort)0x2000) 116#define BD_ENET_RX_INTR ((ushort)0x1000) 117#define BD_ENET_RX_LAST ((ushort)0x0800) 118#define BD_ENET_RX_FIRST ((ushort)0x0400) 119#define BD_ENET_RX_MISS ((ushort)0x0100) 120#define BD_ENET_RX_LG ((ushort)0x0020) 121#define BD_ENET_RX_NO ((ushort)0x0010) 122#define BD_ENET_RX_SH ((ushort)0x0008) 123#define BD_ENET_RX_CR ((ushort)0x0004) 124#define BD_ENET_RX_OV ((ushort)0x0002) 125#define BD_ENET_RX_CL ((ushort)0x0001) 126#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 127 128/* Buffer descriptor control/status used by Ethernet transmit. 129*/ 130#define BD_ENET_TX_READY ((ushort)0x8000) 131#define BD_ENET_TX_PAD ((ushort)0x4000) 132#define BD_ENET_TX_WRAP ((ushort)0x2000) 133#define BD_ENET_TX_INTR ((ushort)0x1000) 134#define BD_ENET_TX_LAST ((ushort)0x0800) 135#define BD_ENET_TX_TC ((ushort)0x0400) 136#define BD_ENET_TX_DEF ((ushort)0x0200) 137#define BD_ENET_TX_HB ((ushort)0x0100) 138#define BD_ENET_TX_LC ((ushort)0x0080) 139#define BD_ENET_TX_RL ((ushort)0x0040) 140#define BD_ENET_TX_RCMASK ((ushort)0x003c) 141#define BD_ENET_TX_UN ((ushort)0x0002) 142#define BD_ENET_TX_CSL ((ushort)0x0001) 143#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 144 145 146/****************************************************************************/ 147#endif /* FEC_H */ 148