1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 */ 28 29/* e1000_hw.c 30 * Shared functions for accessing and configuring the MAC 31 */ 32 33#include "e1000.h" 34 35static s32 e1000_check_downshift(struct e1000_hw *hw); 36static s32 e1000_check_polarity(struct e1000_hw *hw, 37 e1000_rev_polarity *polarity); 38static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 39static void e1000_clear_vfta(struct e1000_hw *hw); 40static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, 41 bool link_up); 42static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); 43static s32 e1000_detect_gig_phy(struct e1000_hw *hw); 44static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); 45static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 46 u16 *max_length); 47static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 48static s32 e1000_id_led_init(struct e1000_hw *hw); 49static void e1000_init_rx_addrs(struct e1000_hw *hw); 50static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 51 struct e1000_phy_info *phy_info); 52static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 53 struct e1000_phy_info *phy_info); 54static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 55static s32 e1000_wait_autoneg(struct e1000_hw *hw); 56static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); 57static s32 e1000_set_phy_type(struct e1000_hw *hw); 58static void e1000_phy_init_script(struct e1000_hw *hw); 59static s32 e1000_setup_copper_link(struct e1000_hw *hw); 60static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 61static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); 62static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 63static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); 64static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 65static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 66static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); 67static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); 68static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 69static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, 70 u16 words, u16 *data); 71static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 72 u16 words, u16 *data); 73static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); 74static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); 75static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); 76static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); 77static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 78 u16 phy_data); 79static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 80 u16 *phy_data); 81static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); 82static s32 e1000_acquire_eeprom(struct e1000_hw *hw); 83static void e1000_release_eeprom(struct e1000_hw *hw); 84static void e1000_standby_eeprom(struct e1000_hw *hw); 85static s32 e1000_set_vco_speed(struct e1000_hw *hw); 86static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); 87static s32 e1000_set_phy_mode(struct e1000_hw *hw); 88static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 89 u16 *data); 90static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 91 u16 *data); 92 93/* IGP cable length table */ 94static const 95u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { 96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 102 100, 103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 104 110, 110, 105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 106 120, 120 107}; 108 109static DEFINE_SPINLOCK(e1000_eeprom_lock); 110 111/** 112 * e1000_set_phy_type - Set the phy type member in the hw struct. 113 * @hw: Struct containing variables accessed by shared code 114 */ 115static s32 e1000_set_phy_type(struct e1000_hw *hw) 116{ 117 e_dbg("e1000_set_phy_type"); 118 119 if (hw->mac_type == e1000_undefined) 120 return -E1000_ERR_PHY_TYPE; 121 122 switch (hw->phy_id) { 123 case M88E1000_E_PHY_ID: 124 case M88E1000_I_PHY_ID: 125 case M88E1011_I_PHY_ID: 126 case M88E1111_I_PHY_ID: 127 hw->phy_type = e1000_phy_m88; 128 break; 129 case IGP01E1000_I_PHY_ID: 130 if (hw->mac_type == e1000_82541 || 131 hw->mac_type == e1000_82541_rev_2 || 132 hw->mac_type == e1000_82547 || 133 hw->mac_type == e1000_82547_rev_2) { 134 hw->phy_type = e1000_phy_igp; 135 break; 136 } 137 default: 138 /* Should never have loaded on this device */ 139 hw->phy_type = e1000_phy_undefined; 140 return -E1000_ERR_PHY_TYPE; 141 } 142 143 return E1000_SUCCESS; 144} 145 146/** 147 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY 148 * @hw: Struct containing variables accessed by shared code 149 */ 150static void e1000_phy_init_script(struct e1000_hw *hw) 151{ 152 u32 ret_val; 153 u16 phy_saved_data; 154 155 e_dbg("e1000_phy_init_script"); 156 157 if (hw->phy_init_script) { 158 msleep(20); 159 160 /* Save off the current value of register 0x2F5B to be restored at 161 * the end of this routine. */ 162 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 163 164 /* Disabled the PHY transmitter */ 165 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 166 msleep(20); 167 168 e1000_write_phy_reg(hw, 0x0000, 0x0140); 169 msleep(5); 170 171 switch (hw->mac_type) { 172 case e1000_82541: 173 case e1000_82547: 174 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 175 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 176 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 177 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 178 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 179 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 180 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 181 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 182 e1000_write_phy_reg(hw, 0x2010, 0x0008); 183 break; 184 185 case e1000_82541_rev_2: 186 case e1000_82547_rev_2: 187 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 188 break; 189 default: 190 break; 191 } 192 193 e1000_write_phy_reg(hw, 0x0000, 0x3300); 194 msleep(20); 195 196 /* Now enable the transmitter */ 197 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 198 199 if (hw->mac_type == e1000_82547) { 200 u16 fused, fine, coarse; 201 202 /* Move to analog registers page */ 203 e1000_read_phy_reg(hw, 204 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 205 &fused); 206 207 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 208 e1000_read_phy_reg(hw, 209 IGP01E1000_ANALOG_FUSE_STATUS, 210 &fused); 211 212 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 213 coarse = 214 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 215 216 if (coarse > 217 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 218 coarse -= 219 IGP01E1000_ANALOG_FUSE_COARSE_10; 220 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 221 } else if (coarse == 222 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 223 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 224 225 fused = 226 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 227 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 228 (coarse & 229 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 230 231 e1000_write_phy_reg(hw, 232 IGP01E1000_ANALOG_FUSE_CONTROL, 233 fused); 234 e1000_write_phy_reg(hw, 235 IGP01E1000_ANALOG_FUSE_BYPASS, 236 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 237 } 238 } 239 } 240} 241 242/** 243 * e1000_set_mac_type - Set the mac type member in the hw struct. 244 * @hw: Struct containing variables accessed by shared code 245 */ 246s32 e1000_set_mac_type(struct e1000_hw *hw) 247{ 248 e_dbg("e1000_set_mac_type"); 249 250 switch (hw->device_id) { 251 case E1000_DEV_ID_82542: 252 switch (hw->revision_id) { 253 case E1000_82542_2_0_REV_ID: 254 hw->mac_type = e1000_82542_rev2_0; 255 break; 256 case E1000_82542_2_1_REV_ID: 257 hw->mac_type = e1000_82542_rev2_1; 258 break; 259 default: 260 /* Invalid 82542 revision ID */ 261 return -E1000_ERR_MAC_TYPE; 262 } 263 break; 264 case E1000_DEV_ID_82543GC_FIBER: 265 case E1000_DEV_ID_82543GC_COPPER: 266 hw->mac_type = e1000_82543; 267 break; 268 case E1000_DEV_ID_82544EI_COPPER: 269 case E1000_DEV_ID_82544EI_FIBER: 270 case E1000_DEV_ID_82544GC_COPPER: 271 case E1000_DEV_ID_82544GC_LOM: 272 hw->mac_type = e1000_82544; 273 break; 274 case E1000_DEV_ID_82540EM: 275 case E1000_DEV_ID_82540EM_LOM: 276 case E1000_DEV_ID_82540EP: 277 case E1000_DEV_ID_82540EP_LOM: 278 case E1000_DEV_ID_82540EP_LP: 279 hw->mac_type = e1000_82540; 280 break; 281 case E1000_DEV_ID_82545EM_COPPER: 282 case E1000_DEV_ID_82545EM_FIBER: 283 hw->mac_type = e1000_82545; 284 break; 285 case E1000_DEV_ID_82545GM_COPPER: 286 case E1000_DEV_ID_82545GM_FIBER: 287 case E1000_DEV_ID_82545GM_SERDES: 288 hw->mac_type = e1000_82545_rev_3; 289 break; 290 case E1000_DEV_ID_82546EB_COPPER: 291 case E1000_DEV_ID_82546EB_FIBER: 292 case E1000_DEV_ID_82546EB_QUAD_COPPER: 293 hw->mac_type = e1000_82546; 294 break; 295 case E1000_DEV_ID_82546GB_COPPER: 296 case E1000_DEV_ID_82546GB_FIBER: 297 case E1000_DEV_ID_82546GB_SERDES: 298 case E1000_DEV_ID_82546GB_PCIE: 299 case E1000_DEV_ID_82546GB_QUAD_COPPER: 300 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 301 hw->mac_type = e1000_82546_rev_3; 302 break; 303 case E1000_DEV_ID_82541EI: 304 case E1000_DEV_ID_82541EI_MOBILE: 305 case E1000_DEV_ID_82541ER_LOM: 306 hw->mac_type = e1000_82541; 307 break; 308 case E1000_DEV_ID_82541ER: 309 case E1000_DEV_ID_82541GI: 310 case E1000_DEV_ID_82541GI_LF: 311 case E1000_DEV_ID_82541GI_MOBILE: 312 hw->mac_type = e1000_82541_rev_2; 313 break; 314 case E1000_DEV_ID_82547EI: 315 case E1000_DEV_ID_82547EI_MOBILE: 316 hw->mac_type = e1000_82547; 317 break; 318 case E1000_DEV_ID_82547GI: 319 hw->mac_type = e1000_82547_rev_2; 320 break; 321 default: 322 /* Should never have loaded on this device */ 323 return -E1000_ERR_MAC_TYPE; 324 } 325 326 switch (hw->mac_type) { 327 case e1000_82541: 328 case e1000_82547: 329 case e1000_82541_rev_2: 330 case e1000_82547_rev_2: 331 hw->asf_firmware_present = true; 332 break; 333 default: 334 break; 335 } 336 337 /* The 82543 chip does not count tx_carrier_errors properly in 338 * FD mode 339 */ 340 if (hw->mac_type == e1000_82543) 341 hw->bad_tx_carr_stats_fd = true; 342 343 if (hw->mac_type > e1000_82544) 344 hw->has_smbus = true; 345 346 return E1000_SUCCESS; 347} 348 349/** 350 * e1000_set_media_type - Set media type and TBI compatibility. 351 * @hw: Struct containing variables accessed by shared code 352 */ 353void e1000_set_media_type(struct e1000_hw *hw) 354{ 355 u32 status; 356 357 e_dbg("e1000_set_media_type"); 358 359 if (hw->mac_type != e1000_82543) { 360 /* tbi_compatibility is only valid on 82543 */ 361 hw->tbi_compatibility_en = false; 362 } 363 364 switch (hw->device_id) { 365 case E1000_DEV_ID_82545GM_SERDES: 366 case E1000_DEV_ID_82546GB_SERDES: 367 hw->media_type = e1000_media_type_internal_serdes; 368 break; 369 default: 370 switch (hw->mac_type) { 371 case e1000_82542_rev2_0: 372 case e1000_82542_rev2_1: 373 hw->media_type = e1000_media_type_fiber; 374 break; 375 default: 376 status = er32(STATUS); 377 if (status & E1000_STATUS_TBIMODE) { 378 hw->media_type = e1000_media_type_fiber; 379 /* tbi_compatibility not valid on fiber */ 380 hw->tbi_compatibility_en = false; 381 } else { 382 hw->media_type = e1000_media_type_copper; 383 } 384 break; 385 } 386 } 387} 388 389/** 390 * e1000_reset_hw: reset the hardware completely 391 * @hw: Struct containing variables accessed by shared code 392 * 393 * Reset the transmit and receive units; mask and clear all interrupts. 394 */ 395s32 e1000_reset_hw(struct e1000_hw *hw) 396{ 397 u32 ctrl; 398 u32 ctrl_ext; 399 u32 icr; 400 u32 manc; 401 u32 led_ctrl; 402 s32 ret_val; 403 404 e_dbg("e1000_reset_hw"); 405 406 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 407 if (hw->mac_type == e1000_82542_rev2_0) { 408 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 409 e1000_pci_clear_mwi(hw); 410 } 411 412 /* Clear interrupt mask to stop board from generating interrupts */ 413 e_dbg("Masking off all interrupts\n"); 414 ew32(IMC, 0xffffffff); 415 416 /* Disable the Transmit and Receive units. Then delay to allow 417 * any pending transactions to complete before we hit the MAC with 418 * the global reset. 419 */ 420 ew32(RCTL, 0); 421 ew32(TCTL, E1000_TCTL_PSP); 422 E1000_WRITE_FLUSH(); 423 424 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 425 hw->tbi_compatibility_on = false; 426 427 /* Delay to allow any outstanding PCI transactions to complete before 428 * resetting the device 429 */ 430 msleep(10); 431 432 ctrl = er32(CTRL); 433 434 /* Must reset the PHY before resetting the MAC */ 435 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 436 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); 437 msleep(5); 438 } 439 440 /* Issue a global reset to the MAC. This will reset the chip's 441 * transmit, receive, DMA, and link units. It will not effect 442 * the current PCI configuration. The global reset bit is self- 443 * clearing, and should clear within a microsecond. 444 */ 445 e_dbg("Issuing a global reset to MAC\n"); 446 447 switch (hw->mac_type) { 448 case e1000_82544: 449 case e1000_82540: 450 case e1000_82545: 451 case e1000_82546: 452 case e1000_82541: 453 case e1000_82541_rev_2: 454 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 455 break; 456 case e1000_82545_rev_3: 457 case e1000_82546_rev_3: 458 /* Reset is performed on a shadow of the control register */ 459 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); 460 break; 461 default: 462 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 463 break; 464 } 465 466 /* After MAC reset, force reload of EEPROM to restore power-on settings to 467 * device. Later controllers reload the EEPROM automatically, so just wait 468 * for reload to complete. 469 */ 470 switch (hw->mac_type) { 471 case e1000_82542_rev2_0: 472 case e1000_82542_rev2_1: 473 case e1000_82543: 474 case e1000_82544: 475 /* Wait for reset to complete */ 476 udelay(10); 477 ctrl_ext = er32(CTRL_EXT); 478 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 479 ew32(CTRL_EXT, ctrl_ext); 480 E1000_WRITE_FLUSH(); 481 /* Wait for EEPROM reload */ 482 msleep(2); 483 break; 484 case e1000_82541: 485 case e1000_82541_rev_2: 486 case e1000_82547: 487 case e1000_82547_rev_2: 488 /* Wait for EEPROM reload */ 489 msleep(20); 490 break; 491 default: 492 /* Auto read done will delay 5ms or poll based on mac type */ 493 ret_val = e1000_get_auto_rd_done(hw); 494 if (ret_val) 495 return ret_val; 496 break; 497 } 498 499 /* Disable HW ARPs on ASF enabled adapters */ 500 if (hw->mac_type >= e1000_82540) { 501 manc = er32(MANC); 502 manc &= ~(E1000_MANC_ARP_EN); 503 ew32(MANC, manc); 504 } 505 506 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 507 e1000_phy_init_script(hw); 508 509 /* Configure activity LED after PHY reset */ 510 led_ctrl = er32(LEDCTL); 511 led_ctrl &= IGP_ACTIVITY_LED_MASK; 512 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 513 ew32(LEDCTL, led_ctrl); 514 } 515 516 /* Clear interrupt mask to stop board from generating interrupts */ 517 e_dbg("Masking off all interrupts\n"); 518 ew32(IMC, 0xffffffff); 519 520 /* Clear any pending interrupt events. */ 521 icr = er32(ICR); 522 523 /* If MWI was previously enabled, reenable it. */ 524 if (hw->mac_type == e1000_82542_rev2_0) { 525 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 526 e1000_pci_set_mwi(hw); 527 } 528 529 return E1000_SUCCESS; 530} 531 532/** 533 * e1000_init_hw: Performs basic configuration of the adapter. 534 * @hw: Struct containing variables accessed by shared code 535 * 536 * Assumes that the controller has previously been reset and is in a 537 * post-reset uninitialized state. Initializes the receive address registers, 538 * multicast table, and VLAN filter table. Calls routines to setup link 539 * configuration and flow control settings. Clears all on-chip counters. Leaves 540 * the transmit and receive units disabled and uninitialized. 541 */ 542s32 e1000_init_hw(struct e1000_hw *hw) 543{ 544 u32 ctrl; 545 u32 i; 546 s32 ret_val; 547 u32 mta_size; 548 u32 ctrl_ext; 549 550 e_dbg("e1000_init_hw"); 551 552 /* Initialize Identification LED */ 553 ret_val = e1000_id_led_init(hw); 554 if (ret_val) { 555 e_dbg("Error Initializing Identification LED\n"); 556 return ret_val; 557 } 558 559 /* Set the media type and TBI compatibility */ 560 e1000_set_media_type(hw); 561 562 /* Disabling VLAN filtering. */ 563 e_dbg("Initializing the IEEE VLAN\n"); 564 if (hw->mac_type < e1000_82545_rev_3) 565 ew32(VET, 0); 566 e1000_clear_vfta(hw); 567 568 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 569 if (hw->mac_type == e1000_82542_rev2_0) { 570 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 571 e1000_pci_clear_mwi(hw); 572 ew32(RCTL, E1000_RCTL_RST); 573 E1000_WRITE_FLUSH(); 574 msleep(5); 575 } 576 577 /* Setup the receive address. This involves initializing all of the Receive 578 * Address Registers (RARs 0 - 15). 579 */ 580 e1000_init_rx_addrs(hw); 581 582 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 583 if (hw->mac_type == e1000_82542_rev2_0) { 584 ew32(RCTL, 0); 585 E1000_WRITE_FLUSH(); 586 msleep(1); 587 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 588 e1000_pci_set_mwi(hw); 589 } 590 591 /* Zero out the Multicast HASH table */ 592 e_dbg("Zeroing the MTA\n"); 593 mta_size = E1000_MC_TBL_SIZE; 594 for (i = 0; i < mta_size; i++) { 595 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 596 /* use write flush to prevent Memory Write Block (MWB) from 597 * occurring when accessing our register space */ 598 E1000_WRITE_FLUSH(); 599 } 600 601 /* Set the PCI priority bit correctly in the CTRL register. This 602 * determines if the adapter gives priority to receives, or if it 603 * gives equal priority to transmits and receives. Valid only on 604 * 82542 and 82543 silicon. 605 */ 606 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 607 ctrl = er32(CTRL); 608 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); 609 } 610 611 switch (hw->mac_type) { 612 case e1000_82545_rev_3: 613 case e1000_82546_rev_3: 614 break; 615 default: 616 if (hw->bus_type == e1000_bus_type_pcix 617 && e1000_pcix_get_mmrbc(hw) > 2048) 618 e1000_pcix_set_mmrbc(hw, 2048); 619 break; 620 } 621 622 /* Call a subroutine to configure the link and setup flow control. */ 623 ret_val = e1000_setup_link(hw); 624 625 /* Set the transmit descriptor write-back policy */ 626 if (hw->mac_type > e1000_82544) { 627 ctrl = er32(TXDCTL); 628 ctrl = 629 (ctrl & ~E1000_TXDCTL_WTHRESH) | 630 E1000_TXDCTL_FULL_TX_DESC_WB; 631 ew32(TXDCTL, ctrl); 632 } 633 634 /* Clear all of the statistics registers (clear on read). It is 635 * important that we do this after we have tried to establish link 636 * because the symbol error count will increment wildly if there 637 * is no link. 638 */ 639 e1000_clear_hw_cntrs(hw); 640 641 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 642 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 643 ctrl_ext = er32(CTRL_EXT); 644 /* Relaxed ordering must be disabled to avoid a parity 645 * error crash in a PCI slot. */ 646 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 647 ew32(CTRL_EXT, ctrl_ext); 648 } 649 650 return ret_val; 651} 652 653/** 654 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. 655 * @hw: Struct containing variables accessed by shared code. 656 */ 657static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 658{ 659 u16 eeprom_data; 660 s32 ret_val; 661 662 e_dbg("e1000_adjust_serdes_amplitude"); 663 664 if (hw->media_type != e1000_media_type_internal_serdes) 665 return E1000_SUCCESS; 666 667 switch (hw->mac_type) { 668 case e1000_82545_rev_3: 669 case e1000_82546_rev_3: 670 break; 671 default: 672 return E1000_SUCCESS; 673 } 674 675 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, 676 &eeprom_data); 677 if (ret_val) { 678 return ret_val; 679 } 680 681 if (eeprom_data != EEPROM_RESERVED_WORD) { 682 /* Adjust SERDES output amplitude only. */ 683 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 684 ret_val = 685 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 686 if (ret_val) 687 return ret_val; 688 } 689 690 return E1000_SUCCESS; 691} 692 693/** 694 * e1000_setup_link - Configures flow control and link settings. 695 * @hw: Struct containing variables accessed by shared code 696 * 697 * Determines which flow control settings to use. Calls the appropriate media- 698 * specific link configuration function. Configures the flow control settings. 699 * Assuming the adapter has a valid link partner, a valid link should be 700 * established. Assumes the hardware has previously been reset and the 701 * transmitter and receiver are not enabled. 702 */ 703s32 e1000_setup_link(struct e1000_hw *hw) 704{ 705 u32 ctrl_ext; 706 s32 ret_val; 707 u16 eeprom_data; 708 709 e_dbg("e1000_setup_link"); 710 711 /* Read and store word 0x0F of the EEPROM. This word contains bits 712 * that determine the hardware's default PAUSE (flow control) mode, 713 * a bit that determines whether the HW defaults to enabling or 714 * disabling auto-negotiation, and the direction of the 715 * SW defined pins. If there is no SW over-ride of the flow 716 * control setting, then the variable hw->fc will 717 * be initialized based on a value in the EEPROM. 718 */ 719 if (hw->fc == E1000_FC_DEFAULT) { 720 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 721 1, &eeprom_data); 722 if (ret_val) { 723 e_dbg("EEPROM Read Error\n"); 724 return -E1000_ERR_EEPROM; 725 } 726 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 727 hw->fc = E1000_FC_NONE; 728 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 729 EEPROM_WORD0F_ASM_DIR) 730 hw->fc = E1000_FC_TX_PAUSE; 731 else 732 hw->fc = E1000_FC_FULL; 733 } 734 735 /* We want to save off the original Flow Control configuration just 736 * in case we get disconnected and then reconnected into a different 737 * hub or switch with different Flow Control capabilities. 738 */ 739 if (hw->mac_type == e1000_82542_rev2_0) 740 hw->fc &= (~E1000_FC_TX_PAUSE); 741 742 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 743 hw->fc &= (~E1000_FC_RX_PAUSE); 744 745 hw->original_fc = hw->fc; 746 747 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); 748 749 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 750 * polarity value for the SW controlled pins, and setup the 751 * Extended Device Control reg with that info. 752 * This is needed because one of the SW controlled pins is used for 753 * signal detection. So this should be done before e1000_setup_pcs_link() 754 * or e1000_phy_setup() is called. 755 */ 756 if (hw->mac_type == e1000_82543) { 757 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 758 1, &eeprom_data); 759 if (ret_val) { 760 e_dbg("EEPROM Read Error\n"); 761 return -E1000_ERR_EEPROM; 762 } 763 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 764 SWDPIO__EXT_SHIFT); 765 ew32(CTRL_EXT, ctrl_ext); 766 } 767 768 /* Call the necessary subroutine to configure the link. */ 769 ret_val = (hw->media_type == e1000_media_type_copper) ? 770 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); 771 772 /* Initialize the flow control address, type, and PAUSE timer 773 * registers to their default values. This is done even if flow 774 * control is disabled, because it does not hurt anything to 775 * initialize these registers. 776 */ 777 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 778 779 ew32(FCT, FLOW_CONTROL_TYPE); 780 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 781 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 782 783 ew32(FCTTV, hw->fc_pause_time); 784 785 /* Set the flow control receive threshold registers. Normally, 786 * these registers will be set to a default threshold that may be 787 * adjusted later by the driver's runtime code. However, if the 788 * ability to transmit pause frames in not enabled, then these 789 * registers will be set to 0. 790 */ 791 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 792 ew32(FCRTL, 0); 793 ew32(FCRTH, 0); 794 } else { 795 /* We need to set up the Receive Threshold high and low water marks 796 * as well as (optionally) enabling the transmission of XON frames. 797 */ 798 if (hw->fc_send_xon) { 799 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 800 ew32(FCRTH, hw->fc_high_water); 801 } else { 802 ew32(FCRTL, hw->fc_low_water); 803 ew32(FCRTH, hw->fc_high_water); 804 } 805 } 806 return ret_val; 807} 808 809/** 810 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link 811 * @hw: Struct containing variables accessed by shared code 812 * 813 * Manipulates Physical Coding Sublayer functions in order to configure 814 * link. Assumes the hardware has been previously reset and the transmitter 815 * and receiver are not enabled. 816 */ 817static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 818{ 819 u32 ctrl; 820 u32 status; 821 u32 txcw = 0; 822 u32 i; 823 u32 signal = 0; 824 s32 ret_val; 825 826 e_dbg("e1000_setup_fiber_serdes_link"); 827 828 /* On adapters with a MAC newer than 82544, SWDP 1 will be 829 * set when the optics detect a signal. On older adapters, it will be 830 * cleared when there is a signal. This applies to fiber media only. 831 * If we're on serdes media, adjust the output amplitude to value 832 * set in the EEPROM. 833 */ 834 ctrl = er32(CTRL); 835 if (hw->media_type == e1000_media_type_fiber) 836 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 837 838 ret_val = e1000_adjust_serdes_amplitude(hw); 839 if (ret_val) 840 return ret_val; 841 842 /* Take the link out of reset */ 843 ctrl &= ~(E1000_CTRL_LRST); 844 845 /* Adjust VCO speed to improve BER performance */ 846 ret_val = e1000_set_vco_speed(hw); 847 if (ret_val) 848 return ret_val; 849 850 e1000_config_collision_dist(hw); 851 852 /* Check for a software override of the flow control settings, and setup 853 * the device accordingly. If auto-negotiation is enabled, then software 854 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 855 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 856 * auto-negotiation is disabled, then software will have to manually 857 * configure the two flow control enable bits in the CTRL register. 858 * 859 * The possible values of the "fc" parameter are: 860 * 0: Flow control is completely disabled 861 * 1: Rx flow control is enabled (we can receive pause frames, but 862 * not send pause frames). 863 * 2: Tx flow control is enabled (we can send pause frames but we do 864 * not support receiving pause frames). 865 * 3: Both Rx and TX flow control (symmetric) are enabled. 866 */ 867 switch (hw->fc) { 868 case E1000_FC_NONE: 869 /* Flow control is completely disabled by a software over-ride. */ 870 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 871 break; 872 case E1000_FC_RX_PAUSE: 873 /* RX Flow control is enabled and TX Flow control is disabled by a 874 * software over-ride. Since there really isn't a way to advertise 875 * that we are capable of RX Pause ONLY, we will advertise that we 876 * support both symmetric and asymmetric RX PAUSE. Later, we will 877 * disable the adapter's ability to send PAUSE frames. 878 */ 879 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 880 break; 881 case E1000_FC_TX_PAUSE: 882 /* TX Flow control is enabled, and RX Flow control is disabled, by a 883 * software over-ride. 884 */ 885 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 886 break; 887 case E1000_FC_FULL: 888 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 889 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 890 break; 891 default: 892 e_dbg("Flow control param set incorrectly\n"); 893 return -E1000_ERR_CONFIG; 894 break; 895 } 896 897 /* Since auto-negotiation is enabled, take the link out of reset (the link 898 * will be in reset, because we previously reset the chip). This will 899 * restart auto-negotiation. If auto-negotiation is successful then the 900 * link-up status bit will be set and the flow control enable bits (RFCE 901 * and TFCE) will be set according to their negotiated value. 902 */ 903 e_dbg("Auto-negotiation enabled\n"); 904 905 ew32(TXCW, txcw); 906 ew32(CTRL, ctrl); 907 E1000_WRITE_FLUSH(); 908 909 hw->txcw = txcw; 910 msleep(1); 911 912 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 913 * indication in the Device Status Register. Time-out if a link isn't 914 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 915 * less than 500 milliseconds even if the other end is doing it in SW). 916 * For internal serdes, we just assume a signal is present, then poll. 917 */ 918 if (hw->media_type == e1000_media_type_internal_serdes || 919 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { 920 e_dbg("Looking for Link\n"); 921 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 922 msleep(10); 923 status = er32(STATUS); 924 if (status & E1000_STATUS_LU) 925 break; 926 } 927 if (i == (LINK_UP_TIMEOUT / 10)) { 928 e_dbg("Never got a valid link from auto-neg!!!\n"); 929 hw->autoneg_failed = 1; 930 /* AutoNeg failed to achieve a link, so we'll call 931 * e1000_check_for_link. This routine will force the link up if 932 * we detect a signal. This will allow us to communicate with 933 * non-autonegotiating link partners. 934 */ 935 ret_val = e1000_check_for_link(hw); 936 if (ret_val) { 937 e_dbg("Error while checking for link\n"); 938 return ret_val; 939 } 940 hw->autoneg_failed = 0; 941 } else { 942 hw->autoneg_failed = 0; 943 e_dbg("Valid Link Found\n"); 944 } 945 } else { 946 e_dbg("No Signal Detected\n"); 947 } 948 return E1000_SUCCESS; 949} 950 951/** 952 * e1000_copper_link_preconfig - early configuration for copper 953 * @hw: Struct containing variables accessed by shared code 954 * 955 * Make sure we have a valid PHY and change PHY mode before link setup. 956 */ 957static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) 958{ 959 u32 ctrl; 960 s32 ret_val; 961 u16 phy_data; 962 963 e_dbg("e1000_copper_link_preconfig"); 964 965 ctrl = er32(CTRL); 966 /* With 82543, we need to force speed and duplex on the MAC equal to what 967 * the PHY speed and duplex configuration is. In addition, we need to 968 * perform a hardware reset on the PHY to take it out of reset. 969 */ 970 if (hw->mac_type > e1000_82543) { 971 ctrl |= E1000_CTRL_SLU; 972 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 973 ew32(CTRL, ctrl); 974 } else { 975 ctrl |= 976 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 977 ew32(CTRL, ctrl); 978 ret_val = e1000_phy_hw_reset(hw); 979 if (ret_val) 980 return ret_val; 981 } 982 983 /* Make sure we have a valid PHY */ 984 ret_val = e1000_detect_gig_phy(hw); 985 if (ret_val) { 986 e_dbg("Error, did not detect valid phy.\n"); 987 return ret_val; 988 } 989 e_dbg("Phy ID = %x\n", hw->phy_id); 990 991 /* Set PHY to class A mode (if necessary) */ 992 ret_val = e1000_set_phy_mode(hw); 993 if (ret_val) 994 return ret_val; 995 996 if ((hw->mac_type == e1000_82545_rev_3) || 997 (hw->mac_type == e1000_82546_rev_3)) { 998 ret_val = 999 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1000 phy_data |= 0x00000008; 1001 ret_val = 1002 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1003 } 1004 1005 if (hw->mac_type <= e1000_82543 || 1006 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1007 hw->mac_type == e1000_82541_rev_2 1008 || hw->mac_type == e1000_82547_rev_2) 1009 hw->phy_reset_disable = false; 1010 1011 return E1000_SUCCESS; 1012} 1013 1014/** 1015 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. 1016 * @hw: Struct containing variables accessed by shared code 1017 */ 1018static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) 1019{ 1020 u32 led_ctrl; 1021 s32 ret_val; 1022 u16 phy_data; 1023 1024 e_dbg("e1000_copper_link_igp_setup"); 1025 1026 if (hw->phy_reset_disable) 1027 return E1000_SUCCESS; 1028 1029 ret_val = e1000_phy_reset(hw); 1030 if (ret_val) { 1031 e_dbg("Error Resetting the PHY\n"); 1032 return ret_val; 1033 } 1034 1035 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1036 msleep(15); 1037 /* Configure activity LED after PHY reset */ 1038 led_ctrl = er32(LEDCTL); 1039 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1040 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1041 ew32(LEDCTL, led_ctrl); 1042 1043 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1044 if (hw->phy_type == e1000_phy_igp) { 1045 /* disable lplu d3 during driver init */ 1046 ret_val = e1000_set_d3_lplu_state(hw, false); 1047 if (ret_val) { 1048 e_dbg("Error Disabling LPLU D3\n"); 1049 return ret_val; 1050 } 1051 } 1052 1053 /* Configure mdi-mdix settings */ 1054 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1055 if (ret_val) 1056 return ret_val; 1057 1058 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1059 hw->dsp_config_state = e1000_dsp_config_disabled; 1060 /* Force MDI for earlier revs of the IGP PHY */ 1061 phy_data &= 1062 ~(IGP01E1000_PSCR_AUTO_MDIX | 1063 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1064 hw->mdix = 1; 1065 1066 } else { 1067 hw->dsp_config_state = e1000_dsp_config_enabled; 1068 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1069 1070 switch (hw->mdix) { 1071 case 1: 1072 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1073 break; 1074 case 2: 1075 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1076 break; 1077 case 0: 1078 default: 1079 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1080 break; 1081 } 1082 } 1083 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1084 if (ret_val) 1085 return ret_val; 1086 1087 /* set auto-master slave resolution settings */ 1088 if (hw->autoneg) { 1089 e1000_ms_type phy_ms_setting = hw->master_slave; 1090 1091 if (hw->ffe_config_state == e1000_ffe_config_active) 1092 hw->ffe_config_state = e1000_ffe_config_enabled; 1093 1094 if (hw->dsp_config_state == e1000_dsp_config_activated) 1095 hw->dsp_config_state = e1000_dsp_config_enabled; 1096 1097 /* when autonegotiation advertisement is only 1000Mbps then we 1098 * should disable SmartSpeed and enable Auto MasterSlave 1099 * resolution as hardware default. */ 1100 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1101 /* Disable SmartSpeed */ 1102 ret_val = 1103 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1104 &phy_data); 1105 if (ret_val) 1106 return ret_val; 1107 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1108 ret_val = 1109 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1110 phy_data); 1111 if (ret_val) 1112 return ret_val; 1113 /* Set auto Master/Slave resolution process */ 1114 ret_val = 1115 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1116 if (ret_val) 1117 return ret_val; 1118 phy_data &= ~CR_1000T_MS_ENABLE; 1119 ret_val = 1120 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1121 if (ret_val) 1122 return ret_val; 1123 } 1124 1125 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1126 if (ret_val) 1127 return ret_val; 1128 1129 /* load defaults for future use */ 1130 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1131 ((phy_data & CR_1000T_MS_VALUE) ? 1132 e1000_ms_force_master : 1133 e1000_ms_force_slave) : e1000_ms_auto; 1134 1135 switch (phy_ms_setting) { 1136 case e1000_ms_force_master: 1137 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1138 break; 1139 case e1000_ms_force_slave: 1140 phy_data |= CR_1000T_MS_ENABLE; 1141 phy_data &= ~(CR_1000T_MS_VALUE); 1142 break; 1143 case e1000_ms_auto: 1144 phy_data &= ~CR_1000T_MS_ENABLE; 1145 default: 1146 break; 1147 } 1148 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1149 if (ret_val) 1150 return ret_val; 1151 } 1152 1153 return E1000_SUCCESS; 1154} 1155 1156/** 1157 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. 1158 * @hw: Struct containing variables accessed by shared code 1159 */ 1160static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1161{ 1162 s32 ret_val; 1163 u16 phy_data; 1164 1165 e_dbg("e1000_copper_link_mgp_setup"); 1166 1167 if (hw->phy_reset_disable) 1168 return E1000_SUCCESS; 1169 1170 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1171 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1172 if (ret_val) 1173 return ret_val; 1174 1175 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1176 1177 /* Options: 1178 * MDI/MDI-X = 0 (default) 1179 * 0 - Auto for all speeds 1180 * 1 - MDI mode 1181 * 2 - MDI-X mode 1182 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1183 */ 1184 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1185 1186 switch (hw->mdix) { 1187 case 1: 1188 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1189 break; 1190 case 2: 1191 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1192 break; 1193 case 3: 1194 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1195 break; 1196 case 0: 1197 default: 1198 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1199 break; 1200 } 1201 1202 /* Options: 1203 * disable_polarity_correction = 0 (default) 1204 * Automatic Correction for Reversed Cable Polarity 1205 * 0 - Disabled 1206 * 1 - Enabled 1207 */ 1208 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1209 if (hw->disable_polarity_correction == 1) 1210 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1211 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1212 if (ret_val) 1213 return ret_val; 1214 1215 if (hw->phy_revision < M88E1011_I_REV_4) { 1216 /* Force TX_CLK in the Extended PHY Specific Control Register 1217 * to 25MHz clock. 1218 */ 1219 ret_val = 1220 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1221 &phy_data); 1222 if (ret_val) 1223 return ret_val; 1224 1225 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1226 1227 if ((hw->phy_revision == E1000_REVISION_2) && 1228 (hw->phy_id == M88E1111_I_PHY_ID)) { 1229 /* Vidalia Phy, set the downshift counter to 5x */ 1230 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1231 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1232 ret_val = e1000_write_phy_reg(hw, 1233 M88E1000_EXT_PHY_SPEC_CTRL, 1234 phy_data); 1235 if (ret_val) 1236 return ret_val; 1237 } else { 1238 /* Configure Master and Slave downshift values */ 1239 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1240 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1241 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1242 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1243 ret_val = e1000_write_phy_reg(hw, 1244 M88E1000_EXT_PHY_SPEC_CTRL, 1245 phy_data); 1246 if (ret_val) 1247 return ret_val; 1248 } 1249 } 1250 1251 /* SW Reset the PHY so all changes take effect */ 1252 ret_val = e1000_phy_reset(hw); 1253 if (ret_val) { 1254 e_dbg("Error Resetting the PHY\n"); 1255 return ret_val; 1256 } 1257 1258 return E1000_SUCCESS; 1259} 1260 1261/** 1262 * e1000_copper_link_autoneg - setup auto-neg 1263 * @hw: Struct containing variables accessed by shared code 1264 * 1265 * Setup auto-negotiation and flow control advertisements, 1266 * and then perform auto-negotiation. 1267 */ 1268static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1269{ 1270 s32 ret_val; 1271 u16 phy_data; 1272 1273 e_dbg("e1000_copper_link_autoneg"); 1274 1275 /* Perform some bounds checking on the hw->autoneg_advertised 1276 * parameter. If this variable is zero, then set it to the default. 1277 */ 1278 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1279 1280 /* If autoneg_advertised is zero, we assume it was not defaulted 1281 * by the calling code so we set to advertise full capability. 1282 */ 1283 if (hw->autoneg_advertised == 0) 1284 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1285 1286 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1287 ret_val = e1000_phy_setup_autoneg(hw); 1288 if (ret_val) { 1289 e_dbg("Error Setting up Auto-Negotiation\n"); 1290 return ret_val; 1291 } 1292 e_dbg("Restarting Auto-Neg\n"); 1293 1294 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1295 * the Auto Neg Restart bit in the PHY control register. 1296 */ 1297 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1298 if (ret_val) 1299 return ret_val; 1300 1301 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1302 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1303 if (ret_val) 1304 return ret_val; 1305 1306 /* Does the user want to wait for Auto-Neg to complete here, or 1307 * check at a later time (for example, callback routine). 1308 */ 1309 if (hw->wait_autoneg_complete) { 1310 ret_val = e1000_wait_autoneg(hw); 1311 if (ret_val) { 1312 e_dbg 1313 ("Error while waiting for autoneg to complete\n"); 1314 return ret_val; 1315 } 1316 } 1317 1318 hw->get_link_status = true; 1319 1320 return E1000_SUCCESS; 1321} 1322 1323/** 1324 * e1000_copper_link_postconfig - post link setup 1325 * @hw: Struct containing variables accessed by shared code 1326 * 1327 * Config the MAC and the PHY after link is up. 1328 * 1) Set up the MAC to the current PHY speed/duplex 1329 * if we are on 82543. If we 1330 * are on newer silicon, we only need to configure 1331 * collision distance in the Transmit Control Register. 1332 * 2) Set up flow control on the MAC to that established with 1333 * the link partner. 1334 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1335 */ 1336static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) 1337{ 1338 s32 ret_val; 1339 e_dbg("e1000_copper_link_postconfig"); 1340 1341 if (hw->mac_type >= e1000_82544) { 1342 e1000_config_collision_dist(hw); 1343 } else { 1344 ret_val = e1000_config_mac_to_phy(hw); 1345 if (ret_val) { 1346 e_dbg("Error configuring MAC to PHY settings\n"); 1347 return ret_val; 1348 } 1349 } 1350 ret_val = e1000_config_fc_after_link_up(hw); 1351 if (ret_val) { 1352 e_dbg("Error Configuring Flow Control\n"); 1353 return ret_val; 1354 } 1355 1356 /* Config DSP to improve Giga link quality */ 1357 if (hw->phy_type == e1000_phy_igp) { 1358 ret_val = e1000_config_dsp_after_link_change(hw, true); 1359 if (ret_val) { 1360 e_dbg("Error Configuring DSP after link up\n"); 1361 return ret_val; 1362 } 1363 } 1364 1365 return E1000_SUCCESS; 1366} 1367 1368/** 1369 * e1000_setup_copper_link - phy/speed/duplex setting 1370 * @hw: Struct containing variables accessed by shared code 1371 * 1372 * Detects which PHY is present and sets up the speed and duplex 1373 */ 1374static s32 e1000_setup_copper_link(struct e1000_hw *hw) 1375{ 1376 s32 ret_val; 1377 u16 i; 1378 u16 phy_data; 1379 1380 e_dbg("e1000_setup_copper_link"); 1381 1382 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1383 ret_val = e1000_copper_link_preconfig(hw); 1384 if (ret_val) 1385 return ret_val; 1386 1387 if (hw->phy_type == e1000_phy_igp) { 1388 ret_val = e1000_copper_link_igp_setup(hw); 1389 if (ret_val) 1390 return ret_val; 1391 } else if (hw->phy_type == e1000_phy_m88) { 1392 ret_val = e1000_copper_link_mgp_setup(hw); 1393 if (ret_val) 1394 return ret_val; 1395 } 1396 1397 if (hw->autoneg) { 1398 /* Setup autoneg and flow control advertisement 1399 * and perform autonegotiation */ 1400 ret_val = e1000_copper_link_autoneg(hw); 1401 if (ret_val) 1402 return ret_val; 1403 } else { 1404 /* PHY will be set to 10H, 10F, 100H,or 100F 1405 * depending on value from forced_speed_duplex. */ 1406 e_dbg("Forcing speed and duplex\n"); 1407 ret_val = e1000_phy_force_speed_duplex(hw); 1408 if (ret_val) { 1409 e_dbg("Error Forcing Speed and Duplex\n"); 1410 return ret_val; 1411 } 1412 } 1413 1414 /* Check link status. Wait up to 100 microseconds for link to become 1415 * valid. 1416 */ 1417 for (i = 0; i < 10; i++) { 1418 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1419 if (ret_val) 1420 return ret_val; 1421 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1422 if (ret_val) 1423 return ret_val; 1424 1425 if (phy_data & MII_SR_LINK_STATUS) { 1426 /* Config the MAC and PHY after link is up */ 1427 ret_val = e1000_copper_link_postconfig(hw); 1428 if (ret_val) 1429 return ret_val; 1430 1431 e_dbg("Valid link established!!!\n"); 1432 return E1000_SUCCESS; 1433 } 1434 udelay(10); 1435 } 1436 1437 e_dbg("Unable to establish link!!!\n"); 1438 return E1000_SUCCESS; 1439} 1440 1441/** 1442 * e1000_phy_setup_autoneg - phy settings 1443 * @hw: Struct containing variables accessed by shared code 1444 * 1445 * Configures PHY autoneg and flow control advertisement settings 1446 */ 1447s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1448{ 1449 s32 ret_val; 1450 u16 mii_autoneg_adv_reg; 1451 u16 mii_1000t_ctrl_reg; 1452 1453 e_dbg("e1000_phy_setup_autoneg"); 1454 1455 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1456 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1457 if (ret_val) 1458 return ret_val; 1459 1460 /* Read the MII 1000Base-T Control Register (Address 9). */ 1461 ret_val = 1462 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1463 if (ret_val) 1464 return ret_val; 1465 1466 /* Need to parse both autoneg_advertised and fc and set up 1467 * the appropriate PHY registers. First we will parse for 1468 * autoneg_advertised software override. Since we can advertise 1469 * a plethora of combinations, we need to check each bit 1470 * individually. 1471 */ 1472 1473 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1474 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1475 * the 1000Base-T Control Register (Address 9). 1476 */ 1477 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1478 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1479 1480 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); 1481 1482 /* Do we want to advertise 10 Mb Half Duplex? */ 1483 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1484 e_dbg("Advertise 10mb Half duplex\n"); 1485 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1486 } 1487 1488 /* Do we want to advertise 10 Mb Full Duplex? */ 1489 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1490 e_dbg("Advertise 10mb Full duplex\n"); 1491 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1492 } 1493 1494 /* Do we want to advertise 100 Mb Half Duplex? */ 1495 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1496 e_dbg("Advertise 100mb Half duplex\n"); 1497 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1498 } 1499 1500 /* Do we want to advertise 100 Mb Full Duplex? */ 1501 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1502 e_dbg("Advertise 100mb Full duplex\n"); 1503 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1504 } 1505 1506 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1507 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1508 e_dbg 1509 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1510 } 1511 1512 /* Do we want to advertise 1000 Mb Full Duplex? */ 1513 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1514 e_dbg("Advertise 1000mb Full duplex\n"); 1515 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1516 } 1517 1518 /* Check for a software override of the flow control settings, and 1519 * setup the PHY advertisement registers accordingly. If 1520 * auto-negotiation is enabled, then software will have to set the 1521 * "PAUSE" bits to the correct value in the Auto-Negotiation 1522 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1523 * 1524 * The possible values of the "fc" parameter are: 1525 * 0: Flow control is completely disabled 1526 * 1: Rx flow control is enabled (we can receive pause frames 1527 * but not send pause frames). 1528 * 2: Tx flow control is enabled (we can send pause frames 1529 * but we do not support receiving pause frames). 1530 * 3: Both Rx and TX flow control (symmetric) are enabled. 1531 * other: No software override. The flow control configuration 1532 * in the EEPROM is used. 1533 */ 1534 switch (hw->fc) { 1535 case E1000_FC_NONE: /* 0 */ 1536 /* Flow control (RX & TX) is completely disabled by a 1537 * software over-ride. 1538 */ 1539 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1540 break; 1541 case E1000_FC_RX_PAUSE: /* 1 */ 1542 /* RX Flow control is enabled, and TX Flow control is 1543 * disabled, by a software over-ride. 1544 */ 1545 /* Since there really isn't a way to advertise that we are 1546 * capable of RX Pause ONLY, we will advertise that we 1547 * support both symmetric and asymmetric RX PAUSE. Later 1548 * (in e1000_config_fc_after_link_up) we will disable the 1549 *hw's ability to send PAUSE frames. 1550 */ 1551 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1552 break; 1553 case E1000_FC_TX_PAUSE: /* 2 */ 1554 /* TX Flow control is enabled, and RX Flow control is 1555 * disabled, by a software over-ride. 1556 */ 1557 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1558 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1559 break; 1560 case E1000_FC_FULL: /* 3 */ 1561 /* Flow control (both RX and TX) is enabled by a software 1562 * over-ride. 1563 */ 1564 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1565 break; 1566 default: 1567 e_dbg("Flow control param set incorrectly\n"); 1568 return -E1000_ERR_CONFIG; 1569 } 1570 1571 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1572 if (ret_val) 1573 return ret_val; 1574 1575 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1576 1577 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1578 if (ret_val) 1579 return ret_val; 1580 1581 return E1000_SUCCESS; 1582} 1583 1584/** 1585 * e1000_phy_force_speed_duplex - force link settings 1586 * @hw: Struct containing variables accessed by shared code 1587 * 1588 * Force PHY speed and duplex settings to hw->forced_speed_duplex 1589 */ 1590static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1591{ 1592 u32 ctrl; 1593 s32 ret_val; 1594 u16 mii_ctrl_reg; 1595 u16 mii_status_reg; 1596 u16 phy_data; 1597 u16 i; 1598 1599 e_dbg("e1000_phy_force_speed_duplex"); 1600 1601 /* Turn off Flow control if we are forcing speed and duplex. */ 1602 hw->fc = E1000_FC_NONE; 1603 1604 e_dbg("hw->fc = %d\n", hw->fc); 1605 1606 /* Read the Device Control Register. */ 1607 ctrl = er32(CTRL); 1608 1609 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 1610 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1611 ctrl &= ~(DEVICE_SPEED_MASK); 1612 1613 /* Clear the Auto Speed Detect Enable bit. */ 1614 ctrl &= ~E1000_CTRL_ASDE; 1615 1616 /* Read the MII Control Register. */ 1617 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 1618 if (ret_val) 1619 return ret_val; 1620 1621 /* We need to disable autoneg in order to force link and duplex. */ 1622 1623 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 1624 1625 /* Are we forcing Full or Half Duplex? */ 1626 if (hw->forced_speed_duplex == e1000_100_full || 1627 hw->forced_speed_duplex == e1000_10_full) { 1628 /* We want to force full duplex so we SET the full duplex bits in the 1629 * Device and MII Control Registers. 1630 */ 1631 ctrl |= E1000_CTRL_FD; 1632 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1633 e_dbg("Full Duplex\n"); 1634 } else { 1635 /* We want to force half duplex so we CLEAR the full duplex bits in 1636 * the Device and MII Control Registers. 1637 */ 1638 ctrl &= ~E1000_CTRL_FD; 1639 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1640 e_dbg("Half Duplex\n"); 1641 } 1642 1643 /* Are we forcing 100Mbps??? */ 1644 if (hw->forced_speed_duplex == e1000_100_full || 1645 hw->forced_speed_duplex == e1000_100_half) { 1646 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 1647 ctrl |= E1000_CTRL_SPD_100; 1648 mii_ctrl_reg |= MII_CR_SPEED_100; 1649 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1650 e_dbg("Forcing 100mb "); 1651 } else { 1652 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1653 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1654 mii_ctrl_reg |= MII_CR_SPEED_10; 1655 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1656 e_dbg("Forcing 10mb "); 1657 } 1658 1659 e1000_config_collision_dist(hw); 1660 1661 /* Write the configured values back to the Device Control Reg. */ 1662 ew32(CTRL, ctrl); 1663 1664 if (hw->phy_type == e1000_phy_m88) { 1665 ret_val = 1666 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1667 if (ret_val) 1668 return ret_val; 1669 1670 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1671 * forced whenever speed are duplex are forced. 1672 */ 1673 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1674 ret_val = 1675 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1676 if (ret_val) 1677 return ret_val; 1678 1679 e_dbg("M88E1000 PSCR: %x\n", phy_data); 1680 1681 /* Need to reset the PHY or these changes will be ignored */ 1682 mii_ctrl_reg |= MII_CR_RESET; 1683 1684 /* Disable MDI-X support for 10/100 */ 1685 } else { 1686 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1687 * forced whenever speed or duplex are forced. 1688 */ 1689 ret_val = 1690 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1691 if (ret_val) 1692 return ret_val; 1693 1694 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1695 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1696 1697 ret_val = 1698 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1699 if (ret_val) 1700 return ret_val; 1701 } 1702 1703 /* Write back the modified PHY MII control register. */ 1704 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 1705 if (ret_val) 1706 return ret_val; 1707 1708 udelay(1); 1709 1710 /* The wait_autoneg_complete flag may be a little misleading here. 1711 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 1712 * But we do want to delay for a period while forcing only so we 1713 * don't generate false No Link messages. So we will wait here 1714 * only if the user has set wait_autoneg_complete to 1, which is 1715 * the default. 1716 */ 1717 if (hw->wait_autoneg_complete) { 1718 /* We will wait for autoneg to complete. */ 1719 e_dbg("Waiting for forced speed/duplex link.\n"); 1720 mii_status_reg = 0; 1721 1722 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 1723 for (i = PHY_FORCE_TIME; i > 0; i--) { 1724 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1725 * to be set. 1726 */ 1727 ret_val = 1728 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1729 if (ret_val) 1730 return ret_val; 1731 1732 ret_val = 1733 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1734 if (ret_val) 1735 return ret_val; 1736 1737 if (mii_status_reg & MII_SR_LINK_STATUS) 1738 break; 1739 msleep(100); 1740 } 1741 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { 1742 /* We didn't get link. Reset the DSP and wait again for link. */ 1743 ret_val = e1000_phy_reset_dsp(hw); 1744 if (ret_val) { 1745 e_dbg("Error Resetting PHY DSP\n"); 1746 return ret_val; 1747 } 1748 } 1749 /* This loop will early-out if the link condition has been met. */ 1750 for (i = PHY_FORCE_TIME; i > 0; i--) { 1751 if (mii_status_reg & MII_SR_LINK_STATUS) 1752 break; 1753 msleep(100); 1754 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1755 * to be set. 1756 */ 1757 ret_val = 1758 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1759 if (ret_val) 1760 return ret_val; 1761 1762 ret_val = 1763 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1764 if (ret_val) 1765 return ret_val; 1766 } 1767 } 1768 1769 if (hw->phy_type == e1000_phy_m88) { 1770 /* Because we reset the PHY above, we need to re-force TX_CLK in the 1771 * Extended PHY Specific Control Register to 25MHz clock. This value 1772 * defaults back to a 2.5MHz clock when the PHY is reset. 1773 */ 1774 ret_val = 1775 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1776 &phy_data); 1777 if (ret_val) 1778 return ret_val; 1779 1780 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1781 ret_val = 1782 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1783 phy_data); 1784 if (ret_val) 1785 return ret_val; 1786 1787 /* In addition, because of the s/w reset above, we need to enable CRS on 1788 * TX. This must be set for both full and half duplex operation. 1789 */ 1790 ret_val = 1791 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1792 if (ret_val) 1793 return ret_val; 1794 1795 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1796 ret_val = 1797 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1798 if (ret_val) 1799 return ret_val; 1800 1801 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) 1802 && (!hw->autoneg) 1803 && (hw->forced_speed_duplex == e1000_10_full 1804 || hw->forced_speed_duplex == e1000_10_half)) { 1805 ret_val = e1000_polarity_reversal_workaround(hw); 1806 if (ret_val) 1807 return ret_val; 1808 } 1809 } 1810 return E1000_SUCCESS; 1811} 1812 1813/** 1814 * e1000_config_collision_dist - set collision distance register 1815 * @hw: Struct containing variables accessed by shared code 1816 * 1817 * Sets the collision distance in the Transmit Control register. 1818 * Link should have been established previously. Reads the speed and duplex 1819 * information from the Device Status register. 1820 */ 1821void e1000_config_collision_dist(struct e1000_hw *hw) 1822{ 1823 u32 tctl, coll_dist; 1824 1825 e_dbg("e1000_config_collision_dist"); 1826 1827 if (hw->mac_type < e1000_82543) 1828 coll_dist = E1000_COLLISION_DISTANCE_82542; 1829 else 1830 coll_dist = E1000_COLLISION_DISTANCE; 1831 1832 tctl = er32(TCTL); 1833 1834 tctl &= ~E1000_TCTL_COLD; 1835 tctl |= coll_dist << E1000_COLD_SHIFT; 1836 1837 ew32(TCTL, tctl); 1838 E1000_WRITE_FLUSH(); 1839} 1840 1841/** 1842 * e1000_config_mac_to_phy - sync phy and mac settings 1843 * @hw: Struct containing variables accessed by shared code 1844 * @mii_reg: data to write to the MII control register 1845 * 1846 * Sets MAC speed and duplex settings to reflect the those in the PHY 1847 * The contents of the PHY register containing the needed information need to 1848 * be passed in. 1849 */ 1850static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) 1851{ 1852 u32 ctrl; 1853 s32 ret_val; 1854 u16 phy_data; 1855 1856 e_dbg("e1000_config_mac_to_phy"); 1857 1858 /* 82544 or newer MAC, Auto Speed Detection takes care of 1859 * MAC speed/duplex configuration.*/ 1860 if (hw->mac_type >= e1000_82544) 1861 return E1000_SUCCESS; 1862 1863 /* Read the Device Control Register and set the bits to Force Speed 1864 * and Duplex. 1865 */ 1866 ctrl = er32(CTRL); 1867 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1868 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1869 1870 /* Set up duplex in the Device Control and Transmit Control 1871 * registers depending on negotiated values. 1872 */ 1873 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1874 if (ret_val) 1875 return ret_val; 1876 1877 if (phy_data & M88E1000_PSSR_DPLX) 1878 ctrl |= E1000_CTRL_FD; 1879 else 1880 ctrl &= ~E1000_CTRL_FD; 1881 1882 e1000_config_collision_dist(hw); 1883 1884 /* Set up speed in the Device Control register depending on 1885 * negotiated values. 1886 */ 1887 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1888 ctrl |= E1000_CTRL_SPD_1000; 1889 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1890 ctrl |= E1000_CTRL_SPD_100; 1891 1892 /* Write the configured values back to the Device Control Reg. */ 1893 ew32(CTRL, ctrl); 1894 return E1000_SUCCESS; 1895} 1896 1897/** 1898 * e1000_force_mac_fc - force flow control settings 1899 * @hw: Struct containing variables accessed by shared code 1900 * 1901 * Forces the MAC's flow control settings. 1902 * Sets the TFCE and RFCE bits in the device control register to reflect 1903 * the adapter settings. TFCE and RFCE need to be explicitly set by 1904 * software when a Copper PHY is used because autonegotiation is managed 1905 * by the PHY rather than the MAC. Software must also configure these 1906 * bits when link is forced on a fiber connection. 1907 */ 1908s32 e1000_force_mac_fc(struct e1000_hw *hw) 1909{ 1910 u32 ctrl; 1911 1912 e_dbg("e1000_force_mac_fc"); 1913 1914 /* Get the current configuration of the Device Control Register */ 1915 ctrl = er32(CTRL); 1916 1917 /* Because we didn't get link via the internal auto-negotiation 1918 * mechanism (we either forced link or we got link via PHY 1919 * auto-neg), we have to manually enable/disable transmit an 1920 * receive flow control. 1921 * 1922 * The "Case" statement below enables/disable flow control 1923 * according to the "hw->fc" parameter. 1924 * 1925 * The possible values of the "fc" parameter are: 1926 * 0: Flow control is completely disabled 1927 * 1: Rx flow control is enabled (we can receive pause 1928 * frames but not send pause frames). 1929 * 2: Tx flow control is enabled (we can send pause frames 1930 * frames but we do not receive pause frames). 1931 * 3: Both Rx and TX flow control (symmetric) is enabled. 1932 * other: No other values should be possible at this point. 1933 */ 1934 1935 switch (hw->fc) { 1936 case E1000_FC_NONE: 1937 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1938 break; 1939 case E1000_FC_RX_PAUSE: 1940 ctrl &= (~E1000_CTRL_TFCE); 1941 ctrl |= E1000_CTRL_RFCE; 1942 break; 1943 case E1000_FC_TX_PAUSE: 1944 ctrl &= (~E1000_CTRL_RFCE); 1945 ctrl |= E1000_CTRL_TFCE; 1946 break; 1947 case E1000_FC_FULL: 1948 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1949 break; 1950 default: 1951 e_dbg("Flow control param set incorrectly\n"); 1952 return -E1000_ERR_CONFIG; 1953 } 1954 1955 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1956 if (hw->mac_type == e1000_82542_rev2_0) 1957 ctrl &= (~E1000_CTRL_TFCE); 1958 1959 ew32(CTRL, ctrl); 1960 return E1000_SUCCESS; 1961} 1962 1963/** 1964 * e1000_config_fc_after_link_up - configure flow control after autoneg 1965 * @hw: Struct containing variables accessed by shared code 1966 * 1967 * Configures flow control settings after link is established 1968 * Should be called immediately after a valid link has been established. 1969 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1970 * and autonegotiation is enabled, the MAC flow control settings will be set 1971 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1972 * and RFCE bits will be automatically set to the negotiated flow control mode. 1973 */ 1974static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) 1975{ 1976 s32 ret_val; 1977 u16 mii_status_reg; 1978 u16 mii_nway_adv_reg; 1979 u16 mii_nway_lp_ability_reg; 1980 u16 speed; 1981 u16 duplex; 1982 1983 e_dbg("e1000_config_fc_after_link_up"); 1984 1985 /* Check for the case where we have fiber media and auto-neg failed 1986 * so we had to force link. In this case, we need to force the 1987 * configuration of the MAC to match the "fc" parameter. 1988 */ 1989 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 1990 || ((hw->media_type == e1000_media_type_internal_serdes) 1991 && (hw->autoneg_failed)) 1992 || ((hw->media_type == e1000_media_type_copper) 1993 && (!hw->autoneg))) { 1994 ret_val = e1000_force_mac_fc(hw); 1995 if (ret_val) { 1996 e_dbg("Error forcing flow control settings\n"); 1997 return ret_val; 1998 } 1999 } 2000 2001 /* Check for the case where we have copper media and auto-neg is 2002 * enabled. In this case, we need to check and see if Auto-Neg 2003 * has completed, and if so, how the PHY and link partner has 2004 * flow control configured. 2005 */ 2006 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2007 /* Read the MII Status Register and check to see if AutoNeg 2008 * has completed. We read this twice because this reg has 2009 * some "sticky" (latched) bits. 2010 */ 2011 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2012 if (ret_val) 2013 return ret_val; 2014 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2015 if (ret_val) 2016 return ret_val; 2017 2018 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2019 /* The AutoNeg process has completed, so we now need to 2020 * read both the Auto Negotiation Advertisement Register 2021 * (Address 4) and the Auto_Negotiation Base Page Ability 2022 * Register (Address 5) to determine how flow control was 2023 * negotiated. 2024 */ 2025 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2026 &mii_nway_adv_reg); 2027 if (ret_val) 2028 return ret_val; 2029 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2030 &mii_nway_lp_ability_reg); 2031 if (ret_val) 2032 return ret_val; 2033 2034 /* Two bits in the Auto Negotiation Advertisement Register 2035 * (Address 4) and two bits in the Auto Negotiation Base 2036 * Page Ability Register (Address 5) determine flow control 2037 * for both the PHY and the link partner. The following 2038 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 2039 * 1999, describes these PAUSE resolution bits and how flow 2040 * control is determined based upon these settings. 2041 * NOTE: DC = Don't Care 2042 * 2043 * LOCAL DEVICE | LINK PARTNER 2044 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2045 *-------|---------|-------|---------|-------------------- 2046 * 0 | 0 | DC | DC | E1000_FC_NONE 2047 * 0 | 1 | 0 | DC | E1000_FC_NONE 2048 * 0 | 1 | 1 | 0 | E1000_FC_NONE 2049 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2050 * 1 | 0 | 0 | DC | E1000_FC_NONE 2051 * 1 | DC | 1 | DC | E1000_FC_FULL 2052 * 1 | 1 | 0 | 0 | E1000_FC_NONE 2053 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2054 * 2055 */ 2056 /* Are both PAUSE bits set to 1? If so, this implies 2057 * Symmetric Flow Control is enabled at both ends. The 2058 * ASM_DIR bits are irrelevant per the spec. 2059 * 2060 * For Symmetric Flow Control: 2061 * 2062 * LOCAL DEVICE | LINK PARTNER 2063 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2064 *-------|---------|-------|---------|-------------------- 2065 * 1 | DC | 1 | DC | E1000_FC_FULL 2066 * 2067 */ 2068 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2069 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2070 /* Now we need to check if the user selected RX ONLY 2071 * of pause frames. In this case, we had to advertise 2072 * FULL flow control because we could not advertise RX 2073 * ONLY. Hence, we must now check to see if we need to 2074 * turn OFF the TRANSMISSION of PAUSE frames. 2075 */ 2076 if (hw->original_fc == E1000_FC_FULL) { 2077 hw->fc = E1000_FC_FULL; 2078 e_dbg("Flow Control = FULL.\n"); 2079 } else { 2080 hw->fc = E1000_FC_RX_PAUSE; 2081 e_dbg 2082 ("Flow Control = RX PAUSE frames only.\n"); 2083 } 2084 } 2085 /* For receiving PAUSE frames ONLY. 2086 * 2087 * LOCAL DEVICE | LINK PARTNER 2088 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2089 *-------|---------|-------|---------|-------------------- 2090 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2091 * 2092 */ 2093 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2094 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2095 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2096 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2097 { 2098 hw->fc = E1000_FC_TX_PAUSE; 2099 e_dbg 2100 ("Flow Control = TX PAUSE frames only.\n"); 2101 } 2102 /* For transmitting PAUSE frames ONLY. 2103 * 2104 * LOCAL DEVICE | LINK PARTNER 2105 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2106 *-------|---------|-------|---------|-------------------- 2107 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2108 * 2109 */ 2110 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2111 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2112 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2113 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2114 { 2115 hw->fc = E1000_FC_RX_PAUSE; 2116 e_dbg 2117 ("Flow Control = RX PAUSE frames only.\n"); 2118 } 2119 /* Per the IEEE spec, at this point flow control should be 2120 * disabled. However, we want to consider that we could 2121 * be connected to a legacy switch that doesn't advertise 2122 * desired flow control, but can be forced on the link 2123 * partner. So if we advertised no flow control, that is 2124 * what we will resolve to. If we advertised some kind of 2125 * receive capability (Rx Pause Only or Full Flow Control) 2126 * and the link partner advertised none, we will configure 2127 * ourselves to enable Rx Flow Control only. We can do 2128 * this safely for two reasons: If the link partner really 2129 * didn't want flow control enabled, and we enable Rx, no 2130 * harm done since we won't be receiving any PAUSE frames 2131 * anyway. If the intent on the link partner was to have 2132 * flow control enabled, then by us enabling RX only, we 2133 * can at least receive pause frames and process them. 2134 * This is a good idea because in most cases, since we are 2135 * predominantly a server NIC, more times than not we will 2136 * be asked to delay transmission of packets than asking 2137 * our link partner to pause transmission of frames. 2138 */ 2139 else if ((hw->original_fc == E1000_FC_NONE || 2140 hw->original_fc == E1000_FC_TX_PAUSE) || 2141 hw->fc_strict_ieee) { 2142 hw->fc = E1000_FC_NONE; 2143 e_dbg("Flow Control = NONE.\n"); 2144 } else { 2145 hw->fc = E1000_FC_RX_PAUSE; 2146 e_dbg 2147 ("Flow Control = RX PAUSE frames only.\n"); 2148 } 2149 2150 /* Now we need to do one last check... If we auto- 2151 * negotiated to HALF DUPLEX, flow control should not be 2152 * enabled per IEEE 802.3 spec. 2153 */ 2154 ret_val = 2155 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2156 if (ret_val) { 2157 e_dbg 2158 ("Error getting link speed and duplex\n"); 2159 return ret_val; 2160 } 2161 2162 if (duplex == HALF_DUPLEX) 2163 hw->fc = E1000_FC_NONE; 2164 2165 /* Now we call a subroutine to actually force the MAC 2166 * controller to use the correct flow control settings. 2167 */ 2168 ret_val = e1000_force_mac_fc(hw); 2169 if (ret_val) { 2170 e_dbg 2171 ("Error forcing flow control settings\n"); 2172 return ret_val; 2173 } 2174 } else { 2175 e_dbg 2176 ("Copper PHY and Auto Neg has not completed.\n"); 2177 } 2178 } 2179 return E1000_SUCCESS; 2180} 2181 2182/** 2183 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 2184 * @hw: pointer to the HW structure 2185 * 2186 * Checks for link up on the hardware. If link is not up and we have 2187 * a signal, then we need to force link up. 2188 */ 2189static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 2190{ 2191 u32 rxcw; 2192 u32 ctrl; 2193 u32 status; 2194 s32 ret_val = E1000_SUCCESS; 2195 2196 e_dbg("e1000_check_for_serdes_link_generic"); 2197 2198 ctrl = er32(CTRL); 2199 status = er32(STATUS); 2200 rxcw = er32(RXCW); 2201 2202 /* 2203 * If we don't have link (auto-negotiation failed or link partner 2204 * cannot auto-negotiate), and our link partner is not trying to 2205 * auto-negotiate with us (we are receiving idles or data), 2206 * we need to force link up. We also need to give auto-negotiation 2207 * time to complete. 2208 */ 2209 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 2210 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 2211 if (hw->autoneg_failed == 0) { 2212 hw->autoneg_failed = 1; 2213 goto out; 2214 } 2215 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 2216 2217 /* Disable auto-negotiation in the TXCW register */ 2218 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2219 2220 /* Force link-up and also force full-duplex. */ 2221 ctrl = er32(CTRL); 2222 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2223 ew32(CTRL, ctrl); 2224 2225 /* Configure Flow Control after forcing link up. */ 2226 ret_val = e1000_config_fc_after_link_up(hw); 2227 if (ret_val) { 2228 e_dbg("Error configuring flow control\n"); 2229 goto out; 2230 } 2231 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2232 /* 2233 * If we are forcing link and we are receiving /C/ ordered 2234 * sets, re-enable auto-negotiation in the TXCW register 2235 * and disable forced link in the Device Control register 2236 * in an attempt to auto-negotiate with our link partner. 2237 */ 2238 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2239 ew32(TXCW, hw->txcw); 2240 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 2241 2242 hw->serdes_has_link = true; 2243 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 2244 /* 2245 * If we force link for non-auto-negotiation switch, check 2246 * link status based on MAC synchronization for internal 2247 * serdes media type. 2248 */ 2249 /* SYNCH bit and IV bit are sticky. */ 2250 udelay(10); 2251 rxcw = er32(RXCW); 2252 if (rxcw & E1000_RXCW_SYNCH) { 2253 if (!(rxcw & E1000_RXCW_IV)) { 2254 hw->serdes_has_link = true; 2255 e_dbg("SERDES: Link up - forced.\n"); 2256 } 2257 } else { 2258 hw->serdes_has_link = false; 2259 e_dbg("SERDES: Link down - force failed.\n"); 2260 } 2261 } 2262 2263 if (E1000_TXCW_ANE & er32(TXCW)) { 2264 status = er32(STATUS); 2265 if (status & E1000_STATUS_LU) { 2266 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 2267 udelay(10); 2268 rxcw = er32(RXCW); 2269 if (rxcw & E1000_RXCW_SYNCH) { 2270 if (!(rxcw & E1000_RXCW_IV)) { 2271 hw->serdes_has_link = true; 2272 e_dbg("SERDES: Link up - autoneg " 2273 "completed successfully.\n"); 2274 } else { 2275 hw->serdes_has_link = false; 2276 e_dbg("SERDES: Link down - invalid" 2277 "codewords detected in autoneg.\n"); 2278 } 2279 } else { 2280 hw->serdes_has_link = false; 2281 e_dbg("SERDES: Link down - no sync.\n"); 2282 } 2283 } else { 2284 hw->serdes_has_link = false; 2285 e_dbg("SERDES: Link down - autoneg failed\n"); 2286 } 2287 } 2288 2289 out: 2290 return ret_val; 2291} 2292 2293/** 2294 * e1000_check_for_link 2295 * @hw: Struct containing variables accessed by shared code 2296 * 2297 * Checks to see if the link status of the hardware has changed. 2298 * Called by any function that needs to check the link status of the adapter. 2299 */ 2300s32 e1000_check_for_link(struct e1000_hw *hw) 2301{ 2302 u32 rxcw = 0; 2303 u32 ctrl; 2304 u32 status; 2305 u32 rctl; 2306 u32 icr; 2307 u32 signal = 0; 2308 s32 ret_val; 2309 u16 phy_data; 2310 2311 e_dbg("e1000_check_for_link"); 2312 2313 ctrl = er32(CTRL); 2314 status = er32(STATUS); 2315 2316 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be 2317 * set when the optics detect a signal. On older adapters, it will be 2318 * cleared when there is a signal. This applies to fiber media only. 2319 */ 2320 if ((hw->media_type == e1000_media_type_fiber) || 2321 (hw->media_type == e1000_media_type_internal_serdes)) { 2322 rxcw = er32(RXCW); 2323 2324 if (hw->media_type == e1000_media_type_fiber) { 2325 signal = 2326 (hw->mac_type > 2327 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2328 if (status & E1000_STATUS_LU) 2329 hw->get_link_status = false; 2330 } 2331 } 2332 2333 /* If we have a copper PHY then we only want to go out to the PHY 2334 * registers to see if Auto-Neg has completed and/or if our link 2335 * status has changed. The get_link_status flag will be set if we 2336 * receive a Link Status Change interrupt or we have Rx Sequence 2337 * Errors. 2338 */ 2339 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2340 /* First we want to see if the MII Status Register reports 2341 * link. If so, then we want to get the current speed/duplex 2342 * of the PHY. 2343 * Read the register twice since the link bit is sticky. 2344 */ 2345 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2346 if (ret_val) 2347 return ret_val; 2348 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2349 if (ret_val) 2350 return ret_val; 2351 2352 if (phy_data & MII_SR_LINK_STATUS) { 2353 hw->get_link_status = false; 2354 /* Check if there was DownShift, must be checked immediately after 2355 * link-up */ 2356 e1000_check_downshift(hw); 2357 2358 2359 if ((hw->mac_type == e1000_82544 2360 || hw->mac_type == e1000_82543) && (!hw->autoneg) 2361 && (hw->forced_speed_duplex == e1000_10_full 2362 || hw->forced_speed_duplex == e1000_10_half)) { 2363 ew32(IMC, 0xffffffff); 2364 ret_val = 2365 e1000_polarity_reversal_workaround(hw); 2366 icr = er32(ICR); 2367 ew32(ICS, (icr & ~E1000_ICS_LSC)); 2368 ew32(IMS, IMS_ENABLE_MASK); 2369 } 2370 2371 } else { 2372 /* No link detected */ 2373 e1000_config_dsp_after_link_change(hw, false); 2374 return 0; 2375 } 2376 2377 /* If we are forcing speed/duplex, then we simply return since 2378 * we have already determined whether we have link or not. 2379 */ 2380 if (!hw->autoneg) 2381 return -E1000_ERR_CONFIG; 2382 2383 /* optimize the dsp settings for the igp phy */ 2384 e1000_config_dsp_after_link_change(hw, true); 2385 2386 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2387 * have Si on board that is 82544 or newer, Auto 2388 * Speed Detection takes care of MAC speed/duplex 2389 * configuration. So we only need to configure Collision 2390 * Distance in the MAC. Otherwise, we need to force 2391 * speed/duplex on the MAC to the current PHY speed/duplex 2392 * settings. 2393 */ 2394 if (hw->mac_type >= e1000_82544) 2395 e1000_config_collision_dist(hw); 2396 else { 2397 ret_val = e1000_config_mac_to_phy(hw); 2398 if (ret_val) { 2399 e_dbg 2400 ("Error configuring MAC to PHY settings\n"); 2401 return ret_val; 2402 } 2403 } 2404 2405 /* Configure Flow Control now that Auto-Neg has completed. First, we 2406 * need to restore the desired flow control settings because we may 2407 * have had to re-autoneg with a different link partner. 2408 */ 2409 ret_val = e1000_config_fc_after_link_up(hw); 2410 if (ret_val) { 2411 e_dbg("Error configuring flow control\n"); 2412 return ret_val; 2413 } 2414 2415 /* At this point we know that we are on copper and we have 2416 * auto-negotiated link. These are conditions for checking the link 2417 * partner capability register. We use the link speed to determine if 2418 * TBI compatibility needs to be turned on or off. If the link is not 2419 * at gigabit speed, then TBI compatibility is not needed. If we are 2420 * at gigabit speed, we turn on TBI compatibility. 2421 */ 2422 if (hw->tbi_compatibility_en) { 2423 u16 speed, duplex; 2424 ret_val = 2425 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2426 if (ret_val) { 2427 e_dbg 2428 ("Error getting link speed and duplex\n"); 2429 return ret_val; 2430 } 2431 if (speed != SPEED_1000) { 2432 /* If link speed is not set to gigabit speed, we do not need 2433 * to enable TBI compatibility. 2434 */ 2435 if (hw->tbi_compatibility_on) { 2436 /* If we previously were in the mode, turn it off. */ 2437 rctl = er32(RCTL); 2438 rctl &= ~E1000_RCTL_SBP; 2439 ew32(RCTL, rctl); 2440 hw->tbi_compatibility_on = false; 2441 } 2442 } else { 2443 /* If TBI compatibility is was previously off, turn it on. For 2444 * compatibility with a TBI link partner, we will store bad 2445 * packets. Some frames have an additional byte on the end and 2446 * will look like CRC errors to to the hardware. 2447 */ 2448 if (!hw->tbi_compatibility_on) { 2449 hw->tbi_compatibility_on = true; 2450 rctl = er32(RCTL); 2451 rctl |= E1000_RCTL_SBP; 2452 ew32(RCTL, rctl); 2453 } 2454 } 2455 } 2456 } 2457 2458 if ((hw->media_type == e1000_media_type_fiber) || 2459 (hw->media_type == e1000_media_type_internal_serdes)) 2460 e1000_check_for_serdes_link_generic(hw); 2461 2462 return E1000_SUCCESS; 2463} 2464 2465/** 2466 * e1000_get_speed_and_duplex 2467 * @hw: Struct containing variables accessed by shared code 2468 * @speed: Speed of the connection 2469 * @duplex: Duplex setting of the connection 2470 2471 * Detects the current speed and duplex settings of the hardware. 2472 */ 2473s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) 2474{ 2475 u32 status; 2476 s32 ret_val; 2477 u16 phy_data; 2478 2479 e_dbg("e1000_get_speed_and_duplex"); 2480 2481 if (hw->mac_type >= e1000_82543) { 2482 status = er32(STATUS); 2483 if (status & E1000_STATUS_SPEED_1000) { 2484 *speed = SPEED_1000; 2485 e_dbg("1000 Mbs, "); 2486 } else if (status & E1000_STATUS_SPEED_100) { 2487 *speed = SPEED_100; 2488 e_dbg("100 Mbs, "); 2489 } else { 2490 *speed = SPEED_10; 2491 e_dbg("10 Mbs, "); 2492 } 2493 2494 if (status & E1000_STATUS_FD) { 2495 *duplex = FULL_DUPLEX; 2496 e_dbg("Full Duplex\n"); 2497 } else { 2498 *duplex = HALF_DUPLEX; 2499 e_dbg(" Half Duplex\n"); 2500 } 2501 } else { 2502 e_dbg("1000 Mbs, Full Duplex\n"); 2503 *speed = SPEED_1000; 2504 *duplex = FULL_DUPLEX; 2505 } 2506 2507 /* IGP01 PHY may advertise full duplex operation after speed downgrade even 2508 * if it is operating at half duplex. Here we set the duplex settings to 2509 * match the duplex in the link partner's capabilities. 2510 */ 2511 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 2512 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 2513 if (ret_val) 2514 return ret_val; 2515 2516 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 2517 *duplex = HALF_DUPLEX; 2518 else { 2519 ret_val = 2520 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 2521 if (ret_val) 2522 return ret_val; 2523 if ((*speed == SPEED_100 2524 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 2525 || (*speed == SPEED_10 2526 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 2527 *duplex = HALF_DUPLEX; 2528 } 2529 } 2530 2531 return E1000_SUCCESS; 2532} 2533 2534/** 2535 * e1000_wait_autoneg 2536 * @hw: Struct containing variables accessed by shared code 2537 * 2538 * Blocks until autoneg completes or times out (~4.5 seconds) 2539 */ 2540static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2541{ 2542 s32 ret_val; 2543 u16 i; 2544 u16 phy_data; 2545 2546 e_dbg("e1000_wait_autoneg"); 2547 e_dbg("Waiting for Auto-Neg to complete.\n"); 2548 2549 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2550 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2551 /* Read the MII Status Register and wait for Auto-Neg 2552 * Complete bit to be set. 2553 */ 2554 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2555 if (ret_val) 2556 return ret_val; 2557 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2558 if (ret_val) 2559 return ret_val; 2560 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2561 return E1000_SUCCESS; 2562 } 2563 msleep(100); 2564 } 2565 return E1000_SUCCESS; 2566} 2567 2568/** 2569 * e1000_raise_mdi_clk - Raises the Management Data Clock 2570 * @hw: Struct containing variables accessed by shared code 2571 * @ctrl: Device control register's current value 2572 */ 2573static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2574{ 2575 /* Raise the clock input to the Management Data Clock (by setting the MDC 2576 * bit), and then delay 10 microseconds. 2577 */ 2578 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); 2579 E1000_WRITE_FLUSH(); 2580 udelay(10); 2581} 2582 2583/** 2584 * e1000_lower_mdi_clk - Lowers the Management Data Clock 2585 * @hw: Struct containing variables accessed by shared code 2586 * @ctrl: Device control register's current value 2587 */ 2588static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2589{ 2590 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2591 * bit), and then delay 10 microseconds. 2592 */ 2593 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2594 E1000_WRITE_FLUSH(); 2595 udelay(10); 2596} 2597 2598/** 2599 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY 2600 * @hw: Struct containing variables accessed by shared code 2601 * @data: Data to send out to the PHY 2602 * @count: Number of bits to shift out 2603 * 2604 * Bits are shifted out in MSB to LSB order. 2605 */ 2606static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) 2607{ 2608 u32 ctrl; 2609 u32 mask; 2610 2611 /* We need to shift "count" number of bits out to the PHY. So, the value 2612 * in the "data" parameter will be shifted out to the PHY one bit at a 2613 * time. In order to do this, "data" must be broken down into bits. 2614 */ 2615 mask = 0x01; 2616 mask <<= (count - 1); 2617 2618 ctrl = er32(CTRL); 2619 2620 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2621 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2622 2623 while (mask) { 2624 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2625 * then raising and lowering the Management Data Clock. A "0" is 2626 * shifted out to the PHY by setting the MDIO bit to "0" and then 2627 * raising and lowering the clock. 2628 */ 2629 if (data & mask) 2630 ctrl |= E1000_CTRL_MDIO; 2631 else 2632 ctrl &= ~E1000_CTRL_MDIO; 2633 2634 ew32(CTRL, ctrl); 2635 E1000_WRITE_FLUSH(); 2636 2637 udelay(10); 2638 2639 e1000_raise_mdi_clk(hw, &ctrl); 2640 e1000_lower_mdi_clk(hw, &ctrl); 2641 2642 mask = mask >> 1; 2643 } 2644} 2645 2646/** 2647 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY 2648 * @hw: Struct containing variables accessed by shared code 2649 * 2650 * Bits are shifted in in MSB to LSB order. 2651 */ 2652static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2653{ 2654 u32 ctrl; 2655 u16 data = 0; 2656 u8 i; 2657 2658 /* In order to read a register from the PHY, we need to shift in a total 2659 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2660 * to avoid contention on the MDIO pin when a read operation is performed. 2661 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2662 * by raising the input to the Management Data Clock (setting the MDC bit), 2663 * and then reading the value of the MDIO bit. 2664 */ 2665 ctrl = er32(CTRL); 2666 2667 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2668 ctrl &= ~E1000_CTRL_MDIO_DIR; 2669 ctrl &= ~E1000_CTRL_MDIO; 2670 2671 ew32(CTRL, ctrl); 2672 E1000_WRITE_FLUSH(); 2673 2674 /* Raise and Lower the clock before reading in the data. This accounts for 2675 * the turnaround bits. The first clock occurred when we clocked out the 2676 * last bit of the Register Address. 2677 */ 2678 e1000_raise_mdi_clk(hw, &ctrl); 2679 e1000_lower_mdi_clk(hw, &ctrl); 2680 2681 for (data = 0, i = 0; i < 16; i++) { 2682 data = data << 1; 2683 e1000_raise_mdi_clk(hw, &ctrl); 2684 ctrl = er32(CTRL); 2685 /* Check to see if we shifted in a "1". */ 2686 if (ctrl & E1000_CTRL_MDIO) 2687 data |= 1; 2688 e1000_lower_mdi_clk(hw, &ctrl); 2689 } 2690 2691 e1000_raise_mdi_clk(hw, &ctrl); 2692 e1000_lower_mdi_clk(hw, &ctrl); 2693 2694 return data; 2695} 2696 2697 2698/** 2699 * e1000_read_phy_reg - read a phy register 2700 * @hw: Struct containing variables accessed by shared code 2701 * @reg_addr: address of the PHY register to read 2702 * 2703 * Reads the value from a PHY register, if the value is on a specific non zero 2704 * page, sets the page first. 2705 */ 2706s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) 2707{ 2708 u32 ret_val; 2709 2710 e_dbg("e1000_read_phy_reg"); 2711 2712 if ((hw->phy_type == e1000_phy_igp) && 2713 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2714 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2715 (u16) reg_addr); 2716 if (ret_val) 2717 return ret_val; 2718 } 2719 2720 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2721 phy_data); 2722 2723 return ret_val; 2724} 2725 2726static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2727 u16 *phy_data) 2728{ 2729 u32 i; 2730 u32 mdic = 0; 2731 const u32 phy_addr = 1; 2732 2733 e_dbg("e1000_read_phy_reg_ex"); 2734 2735 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2736 e_dbg("PHY Address %d is out of range\n", reg_addr); 2737 return -E1000_ERR_PARAM; 2738 } 2739 2740 if (hw->mac_type > e1000_82543) { 2741 /* Set up Op-code, Phy Address, and register address in the MDI 2742 * Control register. The MAC will take care of interfacing with the 2743 * PHY to retrieve the desired data. 2744 */ 2745 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2746 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2747 (E1000_MDIC_OP_READ)); 2748 2749 ew32(MDIC, mdic); 2750 2751 /* Poll the ready bit to see if the MDI read completed */ 2752 for (i = 0; i < 64; i++) { 2753 udelay(50); 2754 mdic = er32(MDIC); 2755 if (mdic & E1000_MDIC_READY) 2756 break; 2757 } 2758 if (!(mdic & E1000_MDIC_READY)) { 2759 e_dbg("MDI Read did not complete\n"); 2760 return -E1000_ERR_PHY; 2761 } 2762 if (mdic & E1000_MDIC_ERROR) { 2763 e_dbg("MDI Error\n"); 2764 return -E1000_ERR_PHY; 2765 } 2766 *phy_data = (u16) mdic; 2767 } else { 2768 /* We must first send a preamble through the MDIO pin to signal the 2769 * beginning of an MII instruction. This is done by sending 32 2770 * consecutive "1" bits. 2771 */ 2772 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2773 2774 /* Now combine the next few fields that are required for a read 2775 * operation. We use this method instead of calling the 2776 * e1000_shift_out_mdi_bits routine five different times. The format of 2777 * a MII read instruction consists of a shift out of 14 bits and is 2778 * defined as follows: 2779 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2780 * followed by a shift in of 18 bits. This first two bits shifted in 2781 * are TurnAround bits used to avoid contention on the MDIO pin when a 2782 * READ operation is performed. These two bits are thrown away 2783 * followed by a shift in of 16 bits which contains the desired data. 2784 */ 2785 mdic = ((reg_addr) | (phy_addr << 5) | 2786 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2787 2788 e1000_shift_out_mdi_bits(hw, mdic, 14); 2789 2790 /* Now that we've shifted out the read command to the MII, we need to 2791 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2792 * register address. 2793 */ 2794 *phy_data = e1000_shift_in_mdi_bits(hw); 2795 } 2796 return E1000_SUCCESS; 2797} 2798 2799/** 2800 * e1000_write_phy_reg - write a phy register 2801 * 2802 * @hw: Struct containing variables accessed by shared code 2803 * @reg_addr: address of the PHY register to write 2804 * @data: data to write to the PHY 2805 2806 * Writes a value to a PHY register 2807 */ 2808s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) 2809{ 2810 u32 ret_val; 2811 2812 e_dbg("e1000_write_phy_reg"); 2813 2814 if ((hw->phy_type == e1000_phy_igp) && 2815 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2816 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2817 (u16) reg_addr); 2818 if (ret_val) 2819 return ret_val; 2820 } 2821 2822 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2823 phy_data); 2824 2825 return ret_val; 2826} 2827 2828static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2829 u16 phy_data) 2830{ 2831 u32 i; 2832 u32 mdic = 0; 2833 const u32 phy_addr = 1; 2834 2835 e_dbg("e1000_write_phy_reg_ex"); 2836 2837 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2838 e_dbg("PHY Address %d is out of range\n", reg_addr); 2839 return -E1000_ERR_PARAM; 2840 } 2841 2842 if (hw->mac_type > e1000_82543) { 2843 /* Set up Op-code, Phy Address, register address, and data intended 2844 * for the PHY register in the MDI Control register. The MAC will take 2845 * care of interfacing with the PHY to send the desired data. 2846 */ 2847 mdic = (((u32) phy_data) | 2848 (reg_addr << E1000_MDIC_REG_SHIFT) | 2849 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2850 (E1000_MDIC_OP_WRITE)); 2851 2852 ew32(MDIC, mdic); 2853 2854 /* Poll the ready bit to see if the MDI read completed */ 2855 for (i = 0; i < 641; i++) { 2856 udelay(5); 2857 mdic = er32(MDIC); 2858 if (mdic & E1000_MDIC_READY) 2859 break; 2860 } 2861 if (!(mdic & E1000_MDIC_READY)) { 2862 e_dbg("MDI Write did not complete\n"); 2863 return -E1000_ERR_PHY; 2864 } 2865 } else { 2866 /* We'll need to use the SW defined pins to shift the write command 2867 * out to the PHY. We first send a preamble to the PHY to signal the 2868 * beginning of the MII instruction. This is done by sending 32 2869 * consecutive "1" bits. 2870 */ 2871 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2872 2873 /* Now combine the remaining required fields that will indicate a 2874 * write operation. We use this method instead of calling the 2875 * e1000_shift_out_mdi_bits routine for each field in the command. The 2876 * format of a MII write instruction is as follows: 2877 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2878 */ 2879 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2880 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2881 mdic <<= 16; 2882 mdic |= (u32) phy_data; 2883 2884 e1000_shift_out_mdi_bits(hw, mdic, 32); 2885 } 2886 2887 return E1000_SUCCESS; 2888} 2889 2890/** 2891 * e1000_phy_hw_reset - reset the phy, hardware style 2892 * @hw: Struct containing variables accessed by shared code 2893 * 2894 * Returns the PHY to the power-on reset state 2895 */ 2896s32 e1000_phy_hw_reset(struct e1000_hw *hw) 2897{ 2898 u32 ctrl, ctrl_ext; 2899 u32 led_ctrl; 2900 s32 ret_val; 2901 2902 e_dbg("e1000_phy_hw_reset"); 2903 2904 e_dbg("Resetting Phy...\n"); 2905 2906 if (hw->mac_type > e1000_82543) { 2907 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2908 * bit. Then, take it out of reset. 2909 * For e1000 hardware, we delay for 10ms between the assert 2910 * and deassert. 2911 */ 2912 ctrl = er32(CTRL); 2913 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2914 E1000_WRITE_FLUSH(); 2915 2916 msleep(10); 2917 2918 ew32(CTRL, ctrl); 2919 E1000_WRITE_FLUSH(); 2920 2921 } else { 2922 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2923 * bit to put the PHY into reset. Then, take it out of reset. 2924 */ 2925 ctrl_ext = er32(CTRL_EXT); 2926 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 2927 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 2928 ew32(CTRL_EXT, ctrl_ext); 2929 E1000_WRITE_FLUSH(); 2930 msleep(10); 2931 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 2932 ew32(CTRL_EXT, ctrl_ext); 2933 E1000_WRITE_FLUSH(); 2934 } 2935 udelay(150); 2936 2937 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2938 /* Configure activity LED after PHY reset */ 2939 led_ctrl = er32(LEDCTL); 2940 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2941 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2942 ew32(LEDCTL, led_ctrl); 2943 } 2944 2945 /* Wait for FW to finish PHY configuration. */ 2946 ret_val = e1000_get_phy_cfg_done(hw); 2947 if (ret_val != E1000_SUCCESS) 2948 return ret_val; 2949 2950 return ret_val; 2951} 2952 2953/** 2954 * e1000_phy_reset - reset the phy to commit settings 2955 * @hw: Struct containing variables accessed by shared code 2956 * 2957 * Resets the PHY 2958 * Sets bit 15 of the MII Control register 2959 */ 2960s32 e1000_phy_reset(struct e1000_hw *hw) 2961{ 2962 s32 ret_val; 2963 u16 phy_data; 2964 2965 e_dbg("e1000_phy_reset"); 2966 2967 switch (hw->phy_type) { 2968 case e1000_phy_igp: 2969 ret_val = e1000_phy_hw_reset(hw); 2970 if (ret_val) 2971 return ret_val; 2972 break; 2973 default: 2974 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2975 if (ret_val) 2976 return ret_val; 2977 2978 phy_data |= MII_CR_RESET; 2979 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2980 if (ret_val) 2981 return ret_val; 2982 2983 udelay(1); 2984 break; 2985 } 2986 2987 if (hw->phy_type == e1000_phy_igp) 2988 e1000_phy_init_script(hw); 2989 2990 return E1000_SUCCESS; 2991} 2992 2993/** 2994 * e1000_detect_gig_phy - check the phy type 2995 * @hw: Struct containing variables accessed by shared code 2996 * 2997 * Probes the expected PHY address for known PHY IDs 2998 */ 2999static s32 e1000_detect_gig_phy(struct e1000_hw *hw) 3000{ 3001 s32 phy_init_status, ret_val; 3002 u16 phy_id_high, phy_id_low; 3003 bool match = false; 3004 3005 e_dbg("e1000_detect_gig_phy"); 3006 3007 if (hw->phy_id != 0) 3008 return E1000_SUCCESS; 3009 3010 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3011 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3012 if (ret_val) 3013 return ret_val; 3014 3015 hw->phy_id = (u32) (phy_id_high << 16); 3016 udelay(20); 3017 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3018 if (ret_val) 3019 return ret_val; 3020 3021 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); 3022 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; 3023 3024 switch (hw->mac_type) { 3025 case e1000_82543: 3026 if (hw->phy_id == M88E1000_E_PHY_ID) 3027 match = true; 3028 break; 3029 case e1000_82544: 3030 if (hw->phy_id == M88E1000_I_PHY_ID) 3031 match = true; 3032 break; 3033 case e1000_82540: 3034 case e1000_82545: 3035 case e1000_82545_rev_3: 3036 case e1000_82546: 3037 case e1000_82546_rev_3: 3038 if (hw->phy_id == M88E1011_I_PHY_ID) 3039 match = true; 3040 break; 3041 case e1000_82541: 3042 case e1000_82541_rev_2: 3043 case e1000_82547: 3044 case e1000_82547_rev_2: 3045 if (hw->phy_id == IGP01E1000_I_PHY_ID) 3046 match = true; 3047 break; 3048 default: 3049 e_dbg("Invalid MAC type %d\n", hw->mac_type); 3050 return -E1000_ERR_CONFIG; 3051 } 3052 phy_init_status = e1000_set_phy_type(hw); 3053 3054 if ((match) && (phy_init_status == E1000_SUCCESS)) { 3055 e_dbg("PHY ID 0x%X detected\n", hw->phy_id); 3056 return E1000_SUCCESS; 3057 } 3058 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); 3059 return -E1000_ERR_PHY; 3060} 3061 3062/** 3063 * e1000_phy_reset_dsp - reset DSP 3064 * @hw: Struct containing variables accessed by shared code 3065 * 3066 * Resets the PHY's DSP 3067 */ 3068static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) 3069{ 3070 s32 ret_val; 3071 e_dbg("e1000_phy_reset_dsp"); 3072 3073 do { 3074 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3075 if (ret_val) 3076 break; 3077 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 3078 if (ret_val) 3079 break; 3080 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 3081 if (ret_val) 3082 break; 3083 ret_val = E1000_SUCCESS; 3084 } while (0); 3085 3086 return ret_val; 3087} 3088 3089/** 3090 * e1000_phy_igp_get_info - get igp specific registers 3091 * @hw: Struct containing variables accessed by shared code 3092 * @phy_info: PHY information structure 3093 * 3094 * Get PHY information from various PHY registers for igp PHY only. 3095 */ 3096static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 3097 struct e1000_phy_info *phy_info) 3098{ 3099 s32 ret_val; 3100 u16 phy_data, min_length, max_length, average; 3101 e1000_rev_polarity polarity; 3102 3103 e_dbg("e1000_phy_igp_get_info"); 3104 3105 /* The downshift status is checked only once, after link is established, 3106 * and it stored in the hw->speed_downgraded parameter. */ 3107 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3108 3109 /* IGP01E1000 does not need to support it. */ 3110 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3111 3112 /* IGP01E1000 always correct polarity reversal */ 3113 phy_info->polarity_correction = e1000_polarity_reversal_enabled; 3114 3115 /* Check polarity status */ 3116 ret_val = e1000_check_polarity(hw, &polarity); 3117 if (ret_val) 3118 return ret_val; 3119 3120 phy_info->cable_polarity = polarity; 3121 3122 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 3123 if (ret_val) 3124 return ret_val; 3125 3126 phy_info->mdix_mode = 3127 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> 3128 IGP01E1000_PSSR_MDIX_SHIFT); 3129 3130 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 3131 IGP01E1000_PSSR_SPEED_1000MBPS) { 3132 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 3133 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3134 if (ret_val) 3135 return ret_val; 3136 3137 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3138 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3139 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3140 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3141 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3142 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3143 3144 /* Get cable length */ 3145 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 3146 if (ret_val) 3147 return ret_val; 3148 3149 /* Translate to old method */ 3150 average = (max_length + min_length) / 2; 3151 3152 if (average <= e1000_igp_cable_length_50) 3153 phy_info->cable_length = e1000_cable_length_50; 3154 else if (average <= e1000_igp_cable_length_80) 3155 phy_info->cable_length = e1000_cable_length_50_80; 3156 else if (average <= e1000_igp_cable_length_110) 3157 phy_info->cable_length = e1000_cable_length_80_110; 3158 else if (average <= e1000_igp_cable_length_140) 3159 phy_info->cable_length = e1000_cable_length_110_140; 3160 else 3161 phy_info->cable_length = e1000_cable_length_140; 3162 } 3163 3164 return E1000_SUCCESS; 3165} 3166 3167/** 3168 * e1000_phy_m88_get_info - get m88 specific registers 3169 * @hw: Struct containing variables accessed by shared code 3170 * @phy_info: PHY information structure 3171 * 3172 * Get PHY information from various PHY registers for m88 PHY only. 3173 */ 3174static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 3175 struct e1000_phy_info *phy_info) 3176{ 3177 s32 ret_val; 3178 u16 phy_data; 3179 e1000_rev_polarity polarity; 3180 3181 e_dbg("e1000_phy_m88_get_info"); 3182 3183 /* The downshift status is checked only once, after link is established, 3184 * and it stored in the hw->speed_downgraded parameter. */ 3185 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3186 3187 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3188 if (ret_val) 3189 return ret_val; 3190 3191 phy_info->extended_10bt_distance = 3192 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 3193 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 3194 e1000_10bt_ext_dist_enable_lower : 3195 e1000_10bt_ext_dist_enable_normal; 3196 3197 phy_info->polarity_correction = 3198 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 3199 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 3200 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 3201 3202 /* Check polarity status */ 3203 ret_val = e1000_check_polarity(hw, &polarity); 3204 if (ret_val) 3205 return ret_val; 3206 phy_info->cable_polarity = polarity; 3207 3208 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3209 if (ret_val) 3210 return ret_val; 3211 3212 phy_info->mdix_mode = 3213 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> 3214 M88E1000_PSSR_MDIX_SHIFT); 3215 3216 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 3217 /* Cable Length Estimation and Local/Remote Receiver Information 3218 * are only valid at 1000 Mbps. 3219 */ 3220 phy_info->cable_length = 3221 (e1000_cable_length) ((phy_data & 3222 M88E1000_PSSR_CABLE_LENGTH) >> 3223 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 3224 3225 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3226 if (ret_val) 3227 return ret_val; 3228 3229 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3230 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3231 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3232 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3233 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3234 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3235 3236 } 3237 3238 return E1000_SUCCESS; 3239} 3240 3241/** 3242 * e1000_phy_get_info - request phy info 3243 * @hw: Struct containing variables accessed by shared code 3244 * @phy_info: PHY information structure 3245 * 3246 * Get PHY information from various PHY registers 3247 */ 3248s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) 3249{ 3250 s32 ret_val; 3251 u16 phy_data; 3252 3253 e_dbg("e1000_phy_get_info"); 3254 3255 phy_info->cable_length = e1000_cable_length_undefined; 3256 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 3257 phy_info->cable_polarity = e1000_rev_polarity_undefined; 3258 phy_info->downshift = e1000_downshift_undefined; 3259 phy_info->polarity_correction = e1000_polarity_reversal_undefined; 3260 phy_info->mdix_mode = e1000_auto_x_mode_undefined; 3261 phy_info->local_rx = e1000_1000t_rx_status_undefined; 3262 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 3263 3264 if (hw->media_type != e1000_media_type_copper) { 3265 e_dbg("PHY info is only valid for copper media\n"); 3266 return -E1000_ERR_CONFIG; 3267 } 3268 3269 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3270 if (ret_val) 3271 return ret_val; 3272 3273 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3274 if (ret_val) 3275 return ret_val; 3276 3277 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 3278 e_dbg("PHY info is only valid if link is up\n"); 3279 return -E1000_ERR_CONFIG; 3280 } 3281 3282 if (hw->phy_type == e1000_phy_igp) 3283 return e1000_phy_igp_get_info(hw, phy_info); 3284 else 3285 return e1000_phy_m88_get_info(hw, phy_info); 3286} 3287 3288s32 e1000_validate_mdi_setting(struct e1000_hw *hw) 3289{ 3290 e_dbg("e1000_validate_mdi_settings"); 3291 3292 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 3293 e_dbg("Invalid MDI setting detected\n"); 3294 hw->mdix = 1; 3295 return -E1000_ERR_CONFIG; 3296 } 3297 return E1000_SUCCESS; 3298} 3299 3300/** 3301 * e1000_init_eeprom_params - initialize sw eeprom vars 3302 * @hw: Struct containing variables accessed by shared code 3303 * 3304 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3305 * is configured. 3306 */ 3307s32 e1000_init_eeprom_params(struct e1000_hw *hw) 3308{ 3309 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3310 u32 eecd = er32(EECD); 3311 s32 ret_val = E1000_SUCCESS; 3312 u16 eeprom_size; 3313 3314 e_dbg("e1000_init_eeprom_params"); 3315 3316 switch (hw->mac_type) { 3317 case e1000_82542_rev2_0: 3318 case e1000_82542_rev2_1: 3319 case e1000_82543: 3320 case e1000_82544: 3321 eeprom->type = e1000_eeprom_microwire; 3322 eeprom->word_size = 64; 3323 eeprom->opcode_bits = 3; 3324 eeprom->address_bits = 6; 3325 eeprom->delay_usec = 50; 3326 break; 3327 case e1000_82540: 3328 case e1000_82545: 3329 case e1000_82545_rev_3: 3330 case e1000_82546: 3331 case e1000_82546_rev_3: 3332 eeprom->type = e1000_eeprom_microwire; 3333 eeprom->opcode_bits = 3; 3334 eeprom->delay_usec = 50; 3335 if (eecd & E1000_EECD_SIZE) { 3336 eeprom->word_size = 256; 3337 eeprom->address_bits = 8; 3338 } else { 3339 eeprom->word_size = 64; 3340 eeprom->address_bits = 6; 3341 } 3342 break; 3343 case e1000_82541: 3344 case e1000_82541_rev_2: 3345 case e1000_82547: 3346 case e1000_82547_rev_2: 3347 if (eecd & E1000_EECD_TYPE) { 3348 eeprom->type = e1000_eeprom_spi; 3349 eeprom->opcode_bits = 8; 3350 eeprom->delay_usec = 1; 3351 if (eecd & E1000_EECD_ADDR_BITS) { 3352 eeprom->page_size = 32; 3353 eeprom->address_bits = 16; 3354 } else { 3355 eeprom->page_size = 8; 3356 eeprom->address_bits = 8; 3357 } 3358 } else { 3359 eeprom->type = e1000_eeprom_microwire; 3360 eeprom->opcode_bits = 3; 3361 eeprom->delay_usec = 50; 3362 if (eecd & E1000_EECD_ADDR_BITS) { 3363 eeprom->word_size = 256; 3364 eeprom->address_bits = 8; 3365 } else { 3366 eeprom->word_size = 64; 3367 eeprom->address_bits = 6; 3368 } 3369 } 3370 break; 3371 default: 3372 break; 3373 } 3374 3375 if (eeprom->type == e1000_eeprom_spi) { 3376 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 3377 * 32KB (incremented by powers of 2). 3378 */ 3379 /* Set to default value for initial eeprom read. */ 3380 eeprom->word_size = 64; 3381 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 3382 if (ret_val) 3383 return ret_val; 3384 eeprom_size = 3385 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 3386 /* 256B eeprom size was not supported in earlier hardware, so we 3387 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 3388 * is never the result used in the shifting logic below. */ 3389 if (eeprom_size) 3390 eeprom_size++; 3391 3392 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 3393 } 3394 return ret_val; 3395} 3396 3397/** 3398 * e1000_raise_ee_clk - Raises the EEPROM's clock input. 3399 * @hw: Struct containing variables accessed by shared code 3400 * @eecd: EECD's current value 3401 */ 3402static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) 3403{ 3404 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 3405 * wait <delay> microseconds. 3406 */ 3407 *eecd = *eecd | E1000_EECD_SK; 3408 ew32(EECD, *eecd); 3409 E1000_WRITE_FLUSH(); 3410 udelay(hw->eeprom.delay_usec); 3411} 3412 3413/** 3414 * e1000_lower_ee_clk - Lowers the EEPROM's clock input. 3415 * @hw: Struct containing variables accessed by shared code 3416 * @eecd: EECD's current value 3417 */ 3418static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) 3419{ 3420 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 3421 * wait 50 microseconds. 3422 */ 3423 *eecd = *eecd & ~E1000_EECD_SK; 3424 ew32(EECD, *eecd); 3425 E1000_WRITE_FLUSH(); 3426 udelay(hw->eeprom.delay_usec); 3427} 3428 3429/** 3430 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. 3431 * @hw: Struct containing variables accessed by shared code 3432 * @data: data to send to the EEPROM 3433 * @count: number of bits to shift out 3434 */ 3435static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) 3436{ 3437 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3438 u32 eecd; 3439 u32 mask; 3440 3441 /* We need to shift "count" bits out to the EEPROM. So, value in the 3442 * "data" parameter will be shifted out to the EEPROM one bit at a time. 3443 * In order to do this, "data" must be broken down into bits. 3444 */ 3445 mask = 0x01 << (count - 1); 3446 eecd = er32(EECD); 3447 if (eeprom->type == e1000_eeprom_microwire) { 3448 eecd &= ~E1000_EECD_DO; 3449 } else if (eeprom->type == e1000_eeprom_spi) { 3450 eecd |= E1000_EECD_DO; 3451 } 3452 do { 3453 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 3454 * and then raising and then lowering the clock (the SK bit controls 3455 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 3456 * by setting "DI" to "0" and then raising and then lowering the clock. 3457 */ 3458 eecd &= ~E1000_EECD_DI; 3459 3460 if (data & mask) 3461 eecd |= E1000_EECD_DI; 3462 3463 ew32(EECD, eecd); 3464 E1000_WRITE_FLUSH(); 3465 3466 udelay(eeprom->delay_usec); 3467 3468 e1000_raise_ee_clk(hw, &eecd); 3469 e1000_lower_ee_clk(hw, &eecd); 3470 3471 mask = mask >> 1; 3472 3473 } while (mask); 3474 3475 /* We leave the "DI" bit set to "0" when we leave this routine. */ 3476 eecd &= ~E1000_EECD_DI; 3477 ew32(EECD, eecd); 3478} 3479 3480/** 3481 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM 3482 * @hw: Struct containing variables accessed by shared code 3483 * @count: number of bits to shift in 3484 */ 3485static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) 3486{ 3487 u32 eecd; 3488 u32 i; 3489 u16 data; 3490 3491 /* In order to read a register from the EEPROM, we need to shift 'count' 3492 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 3493 * input to the EEPROM (setting the SK bit), and then reading the value of 3494 * the "DO" bit. During this "shifting in" process the "DI" bit should 3495 * always be clear. 3496 */ 3497 3498 eecd = er32(EECD); 3499 3500 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 3501 data = 0; 3502 3503 for (i = 0; i < count; i++) { 3504 data = data << 1; 3505 e1000_raise_ee_clk(hw, &eecd); 3506 3507 eecd = er32(EECD); 3508 3509 eecd &= ~(E1000_EECD_DI); 3510 if (eecd & E1000_EECD_DO) 3511 data |= 1; 3512 3513 e1000_lower_ee_clk(hw, &eecd); 3514 } 3515 3516 return data; 3517} 3518 3519/** 3520 * e1000_acquire_eeprom - Prepares EEPROM for access 3521 * @hw: Struct containing variables accessed by shared code 3522 * 3523 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 3524 * function should be called before issuing a command to the EEPROM. 3525 */ 3526static s32 e1000_acquire_eeprom(struct e1000_hw *hw) 3527{ 3528 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3529 u32 eecd, i = 0; 3530 3531 e_dbg("e1000_acquire_eeprom"); 3532 3533 eecd = er32(EECD); 3534 3535 /* Request EEPROM Access */ 3536 if (hw->mac_type > e1000_82544) { 3537 eecd |= E1000_EECD_REQ; 3538 ew32(EECD, eecd); 3539 eecd = er32(EECD); 3540 while ((!(eecd & E1000_EECD_GNT)) && 3541 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3542 i++; 3543 udelay(5); 3544 eecd = er32(EECD); 3545 } 3546 if (!(eecd & E1000_EECD_GNT)) { 3547 eecd &= ~E1000_EECD_REQ; 3548 ew32(EECD, eecd); 3549 e_dbg("Could not acquire EEPROM grant\n"); 3550 return -E1000_ERR_EEPROM; 3551 } 3552 } 3553 3554 /* Setup EEPROM for Read/Write */ 3555 3556 if (eeprom->type == e1000_eeprom_microwire) { 3557 /* Clear SK and DI */ 3558 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 3559 ew32(EECD, eecd); 3560 3561 /* Set CS */ 3562 eecd |= E1000_EECD_CS; 3563 ew32(EECD, eecd); 3564 } else if (eeprom->type == e1000_eeprom_spi) { 3565 /* Clear SK and CS */ 3566 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3567 ew32(EECD, eecd); 3568 udelay(1); 3569 } 3570 3571 return E1000_SUCCESS; 3572} 3573 3574/** 3575 * e1000_standby_eeprom - Returns EEPROM to a "standby" state 3576 * @hw: Struct containing variables accessed by shared code 3577 */ 3578static void e1000_standby_eeprom(struct e1000_hw *hw) 3579{ 3580 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3581 u32 eecd; 3582 3583 eecd = er32(EECD); 3584 3585 if (eeprom->type == e1000_eeprom_microwire) { 3586 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3587 ew32(EECD, eecd); 3588 E1000_WRITE_FLUSH(); 3589 udelay(eeprom->delay_usec); 3590 3591 /* Clock high */ 3592 eecd |= E1000_EECD_SK; 3593 ew32(EECD, eecd); 3594 E1000_WRITE_FLUSH(); 3595 udelay(eeprom->delay_usec); 3596 3597 /* Select EEPROM */ 3598 eecd |= E1000_EECD_CS; 3599 ew32(EECD, eecd); 3600 E1000_WRITE_FLUSH(); 3601 udelay(eeprom->delay_usec); 3602 3603 /* Clock low */ 3604 eecd &= ~E1000_EECD_SK; 3605 ew32(EECD, eecd); 3606 E1000_WRITE_FLUSH(); 3607 udelay(eeprom->delay_usec); 3608 } else if (eeprom->type == e1000_eeprom_spi) { 3609 /* Toggle CS to flush commands */ 3610 eecd |= E1000_EECD_CS; 3611 ew32(EECD, eecd); 3612 E1000_WRITE_FLUSH(); 3613 udelay(eeprom->delay_usec); 3614 eecd &= ~E1000_EECD_CS; 3615 ew32(EECD, eecd); 3616 E1000_WRITE_FLUSH(); 3617 udelay(eeprom->delay_usec); 3618 } 3619} 3620 3621/** 3622 * e1000_release_eeprom - drop chip select 3623 * @hw: Struct containing variables accessed by shared code 3624 * 3625 * Terminates a command by inverting the EEPROM's chip select pin 3626 */ 3627static void e1000_release_eeprom(struct e1000_hw *hw) 3628{ 3629 u32 eecd; 3630 3631 e_dbg("e1000_release_eeprom"); 3632 3633 eecd = er32(EECD); 3634 3635 if (hw->eeprom.type == e1000_eeprom_spi) { 3636 eecd |= E1000_EECD_CS; /* Pull CS high */ 3637 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 3638 3639 ew32(EECD, eecd); 3640 3641 udelay(hw->eeprom.delay_usec); 3642 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 3643 /* cleanup eeprom */ 3644 3645 /* CS on Microwire is active-high */ 3646 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 3647 3648 ew32(EECD, eecd); 3649 3650 /* Rising edge of clock */ 3651 eecd |= E1000_EECD_SK; 3652 ew32(EECD, eecd); 3653 E1000_WRITE_FLUSH(); 3654 udelay(hw->eeprom.delay_usec); 3655 3656 /* Falling edge of clock */ 3657 eecd &= ~E1000_EECD_SK; 3658 ew32(EECD, eecd); 3659 E1000_WRITE_FLUSH(); 3660 udelay(hw->eeprom.delay_usec); 3661 } 3662 3663 /* Stop requesting EEPROM access */ 3664 if (hw->mac_type > e1000_82544) { 3665 eecd &= ~E1000_EECD_REQ; 3666 ew32(EECD, eecd); 3667 } 3668} 3669 3670/** 3671 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. 3672 * @hw: Struct containing variables accessed by shared code 3673 */ 3674static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) 3675{ 3676 u16 retry_count = 0; 3677 u8 spi_stat_reg; 3678 3679 e_dbg("e1000_spi_eeprom_ready"); 3680 3681 /* Read "Status Register" repeatedly until the LSB is cleared. The 3682 * EEPROM will signal that the command has been completed by clearing 3683 * bit 0 of the internal status register. If it's not cleared within 3684 * 5 milliseconds, then error out. 3685 */ 3686 retry_count = 0; 3687 do { 3688 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 3689 hw->eeprom.opcode_bits); 3690 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); 3691 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 3692 break; 3693 3694 udelay(5); 3695 retry_count += 5; 3696 3697 e1000_standby_eeprom(hw); 3698 } while (retry_count < EEPROM_MAX_RETRY_SPI); 3699 3700 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 3701 * only 0-5mSec on 5V devices) 3702 */ 3703 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 3704 e_dbg("SPI EEPROM Status error\n"); 3705 return -E1000_ERR_EEPROM; 3706 } 3707 3708 return E1000_SUCCESS; 3709} 3710 3711/** 3712 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. 3713 * @hw: Struct containing variables accessed by shared code 3714 * @offset: offset of word in the EEPROM to read 3715 * @data: word read from the EEPROM 3716 * @words: number of words to read 3717 */ 3718s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3719{ 3720 s32 ret; 3721 spin_lock(&e1000_eeprom_lock); 3722 ret = e1000_do_read_eeprom(hw, offset, words, data); 3723 spin_unlock(&e1000_eeprom_lock); 3724 return ret; 3725} 3726 3727static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 3728 u16 *data) 3729{ 3730 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3731 u32 i = 0; 3732 3733 e_dbg("e1000_read_eeprom"); 3734 3735 /* If eeprom is not yet detected, do so now */ 3736 if (eeprom->word_size == 0) 3737 e1000_init_eeprom_params(hw); 3738 3739 /* A check for invalid values: offset too large, too many words, and not 3740 * enough words. 3741 */ 3742 if ((offset >= eeprom->word_size) 3743 || (words > eeprom->word_size - offset) || (words == 0)) { 3744 e_dbg("\"words\" parameter out of bounds. Words = %d," 3745 "size = %d\n", offset, eeprom->word_size); 3746 return -E1000_ERR_EEPROM; 3747 } 3748 3749 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 3750 * directly. In this case, we need to acquire the EEPROM so that 3751 * FW or other port software does not interrupt. 3752 */ 3753 /* Prepare the EEPROM for bit-bang reading */ 3754 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3755 return -E1000_ERR_EEPROM; 3756 3757 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 3758 * acquired the EEPROM at this point, so any returns should release it */ 3759 if (eeprom->type == e1000_eeprom_spi) { 3760 u16 word_in; 3761 u8 read_opcode = EEPROM_READ_OPCODE_SPI; 3762 3763 if (e1000_spi_eeprom_ready(hw)) { 3764 e1000_release_eeprom(hw); 3765 return -E1000_ERR_EEPROM; 3766 } 3767 3768 e1000_standby_eeprom(hw); 3769 3770 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 3771 if ((eeprom->address_bits == 8) && (offset >= 128)) 3772 read_opcode |= EEPROM_A8_OPCODE_SPI; 3773 3774 /* Send the READ command (opcode + addr) */ 3775 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 3776 e1000_shift_out_ee_bits(hw, (u16) (offset * 2), 3777 eeprom->address_bits); 3778 3779 /* Read the data. The address of the eeprom internally increments with 3780 * each byte (spi) being read, saving on the overhead of eeprom setup 3781 * and tear-down. The address counter will roll over if reading beyond 3782 * the size of the eeprom, thus allowing the entire memory to be read 3783 * starting from any offset. */ 3784 for (i = 0; i < words; i++) { 3785 word_in = e1000_shift_in_ee_bits(hw, 16); 3786 data[i] = (word_in >> 8) | (word_in << 8); 3787 } 3788 } else if (eeprom->type == e1000_eeprom_microwire) { 3789 for (i = 0; i < words; i++) { 3790 /* Send the READ command (opcode + addr) */ 3791 e1000_shift_out_ee_bits(hw, 3792 EEPROM_READ_OPCODE_MICROWIRE, 3793 eeprom->opcode_bits); 3794 e1000_shift_out_ee_bits(hw, (u16) (offset + i), 3795 eeprom->address_bits); 3796 3797 /* Read the data. For microwire, each word requires the overhead 3798 * of eeprom setup and tear-down. */ 3799 data[i] = e1000_shift_in_ee_bits(hw, 16); 3800 e1000_standby_eeprom(hw); 3801 } 3802 } 3803 3804 /* End this read operation */ 3805 e1000_release_eeprom(hw); 3806 3807 return E1000_SUCCESS; 3808} 3809 3810/** 3811 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum 3812 * @hw: Struct containing variables accessed by shared code 3813 * 3814 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 3815 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 3816 * valid. 3817 */ 3818s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) 3819{ 3820 u16 checksum = 0; 3821 u16 i, eeprom_data; 3822 3823 e_dbg("e1000_validate_eeprom_checksum"); 3824 3825 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3826 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3827 e_dbg("EEPROM Read Error\n"); 3828 return -E1000_ERR_EEPROM; 3829 } 3830 checksum += eeprom_data; 3831 } 3832 3833 if (checksum == (u16) EEPROM_SUM) 3834 return E1000_SUCCESS; 3835 else { 3836 e_dbg("EEPROM Checksum Invalid\n"); 3837 return -E1000_ERR_EEPROM; 3838 } 3839} 3840 3841/** 3842 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum 3843 * @hw: Struct containing variables accessed by shared code 3844 * 3845 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 3846 * Writes the difference to word offset 63 of the EEPROM. 3847 */ 3848s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) 3849{ 3850 u16 checksum = 0; 3851 u16 i, eeprom_data; 3852 3853 e_dbg("e1000_update_eeprom_checksum"); 3854 3855 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 3856 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3857 e_dbg("EEPROM Read Error\n"); 3858 return -E1000_ERR_EEPROM; 3859 } 3860 checksum += eeprom_data; 3861 } 3862 checksum = (u16) EEPROM_SUM - checksum; 3863 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 3864 e_dbg("EEPROM Write Error\n"); 3865 return -E1000_ERR_EEPROM; 3866 } 3867 return E1000_SUCCESS; 3868} 3869 3870/** 3871 * e1000_write_eeprom - write words to the different EEPROM types. 3872 * @hw: Struct containing variables accessed by shared code 3873 * @offset: offset within the EEPROM to be written to 3874 * @words: number of words to write 3875 * @data: 16 bit word to be written to the EEPROM 3876 * 3877 * If e1000_update_eeprom_checksum is not called after this function, the 3878 * EEPROM will most likely contain an invalid checksum. 3879 */ 3880s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3881{ 3882 s32 ret; 3883 spin_lock(&e1000_eeprom_lock); 3884 ret = e1000_do_write_eeprom(hw, offset, words, data); 3885 spin_unlock(&e1000_eeprom_lock); 3886 return ret; 3887} 3888 3889static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 3890 u16 *data) 3891{ 3892 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3893 s32 status = 0; 3894 3895 e_dbg("e1000_write_eeprom"); 3896 3897 /* If eeprom is not yet detected, do so now */ 3898 if (eeprom->word_size == 0) 3899 e1000_init_eeprom_params(hw); 3900 3901 /* A check for invalid values: offset too large, too many words, and not 3902 * enough words. 3903 */ 3904 if ((offset >= eeprom->word_size) 3905 || (words > eeprom->word_size - offset) || (words == 0)) { 3906 e_dbg("\"words\" parameter out of bounds\n"); 3907 return -E1000_ERR_EEPROM; 3908 } 3909 3910 /* Prepare the EEPROM for writing */ 3911 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3912 return -E1000_ERR_EEPROM; 3913 3914 if (eeprom->type == e1000_eeprom_microwire) { 3915 status = e1000_write_eeprom_microwire(hw, offset, words, data); 3916 } else { 3917 status = e1000_write_eeprom_spi(hw, offset, words, data); 3918 msleep(10); 3919 } 3920 3921 /* Done with writing */ 3922 e1000_release_eeprom(hw); 3923 3924 return status; 3925} 3926 3927/** 3928 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. 3929 * @hw: Struct containing variables accessed by shared code 3930 * @offset: offset within the EEPROM to be written to 3931 * @words: number of words to write 3932 * @data: pointer to array of 8 bit words to be written to the EEPROM 3933 */ 3934static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, 3935 u16 *data) 3936{ 3937 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3938 u16 widx = 0; 3939 3940 e_dbg("e1000_write_eeprom_spi"); 3941 3942 while (widx < words) { 3943 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; 3944 3945 if (e1000_spi_eeprom_ready(hw)) 3946 return -E1000_ERR_EEPROM; 3947 3948 e1000_standby_eeprom(hw); 3949 3950 /* Send the WRITE ENABLE command (8 bit opcode ) */ 3951 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 3952 eeprom->opcode_bits); 3953 3954 e1000_standby_eeprom(hw); 3955 3956 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 3957 if ((eeprom->address_bits == 8) && (offset >= 128)) 3958 write_opcode |= EEPROM_A8_OPCODE_SPI; 3959 3960 /* Send the Write command (8-bit opcode + addr) */ 3961 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 3962 3963 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), 3964 eeprom->address_bits); 3965 3966 /* Send the data */ 3967 3968 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 3969 while (widx < words) { 3970 u16 word_out = data[widx]; 3971 word_out = (word_out >> 8) | (word_out << 8); 3972 e1000_shift_out_ee_bits(hw, word_out, 16); 3973 widx++; 3974 3975 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE 3976 * operation, while the smaller eeproms are capable of an 8-byte 3977 * PAGE WRITE operation. Break the inner loop to pass new address 3978 */ 3979 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 3980 e1000_standby_eeprom(hw); 3981 break; 3982 } 3983 } 3984 } 3985 3986 return E1000_SUCCESS; 3987} 3988 3989/** 3990 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. 3991 * @hw: Struct containing variables accessed by shared code 3992 * @offset: offset within the EEPROM to be written to 3993 * @words: number of words to write 3994 * @data: pointer to array of 8 bit words to be written to the EEPROM 3995 */ 3996static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 3997 u16 words, u16 *data) 3998{ 3999 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4000 u32 eecd; 4001 u16 words_written = 0; 4002 u16 i = 0; 4003 4004 e_dbg("e1000_write_eeprom_microwire"); 4005 4006 /* Send the write enable command to the EEPROM (3-bit opcode plus 4007 * 6/8-bit dummy address beginning with 11). It's less work to include 4008 * the 11 of the dummy address as part of the opcode than it is to shift 4009 * it over the correct number of bits for the address. This puts the 4010 * EEPROM into write/erase mode. 4011 */ 4012 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 4013 (u16) (eeprom->opcode_bits + 2)); 4014 4015 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); 4016 4017 /* Prepare the EEPROM */ 4018 e1000_standby_eeprom(hw); 4019 4020 while (words_written < words) { 4021 /* Send the Write command (3-bit opcode + addr) */ 4022 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 4023 eeprom->opcode_bits); 4024 4025 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), 4026 eeprom->address_bits); 4027 4028 /* Send the data */ 4029 e1000_shift_out_ee_bits(hw, data[words_written], 16); 4030 4031 /* Toggle the CS line. This in effect tells the EEPROM to execute 4032 * the previous command. 4033 */ 4034 e1000_standby_eeprom(hw); 4035 4036 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will 4037 * signal that the command has been completed by raising the DO signal. 4038 * If DO does not go high in 10 milliseconds, then error out. 4039 */ 4040 for (i = 0; i < 200; i++) { 4041 eecd = er32(EECD); 4042 if (eecd & E1000_EECD_DO) 4043 break; 4044 udelay(50); 4045 } 4046 if (i == 200) { 4047 e_dbg("EEPROM Write did not complete\n"); 4048 return -E1000_ERR_EEPROM; 4049 } 4050 4051 /* Recover from write */ 4052 e1000_standby_eeprom(hw); 4053 4054 words_written++; 4055 } 4056 4057 /* Send the write disable command to the EEPROM (3-bit opcode plus 4058 * 6/8-bit dummy address beginning with 10). It's less work to include 4059 * the 10 of the dummy address as part of the opcode than it is to shift 4060 * it over the correct number of bits for the address. This takes the 4061 * EEPROM out of write/erase mode. 4062 */ 4063 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 4064 (u16) (eeprom->opcode_bits + 2)); 4065 4066 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); 4067 4068 return E1000_SUCCESS; 4069} 4070 4071/** 4072 * e1000_read_mac_addr - read the adapters MAC from eeprom 4073 * @hw: Struct containing variables accessed by shared code 4074 * 4075 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 4076 * second function of dual function devices 4077 */ 4078s32 e1000_read_mac_addr(struct e1000_hw *hw) 4079{ 4080 u16 offset; 4081 u16 eeprom_data, i; 4082 4083 e_dbg("e1000_read_mac_addr"); 4084 4085 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 4086 offset = i >> 1; 4087 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 4088 e_dbg("EEPROM Read Error\n"); 4089 return -E1000_ERR_EEPROM; 4090 } 4091 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); 4092 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); 4093 } 4094 4095 switch (hw->mac_type) { 4096 default: 4097 break; 4098 case e1000_82546: 4099 case e1000_82546_rev_3: 4100 if (er32(STATUS) & E1000_STATUS_FUNC_1) 4101 hw->perm_mac_addr[5] ^= 0x01; 4102 break; 4103 } 4104 4105 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 4106 hw->mac_addr[i] = hw->perm_mac_addr[i]; 4107 return E1000_SUCCESS; 4108} 4109 4110/** 4111 * e1000_init_rx_addrs - Initializes receive address filters. 4112 * @hw: Struct containing variables accessed by shared code 4113 * 4114 * Places the MAC address in receive address register 0 and clears the rest 4115 * of the receive address registers. Clears the multicast table. Assumes 4116 * the receiver is in reset when the routine is called. 4117 */ 4118static void e1000_init_rx_addrs(struct e1000_hw *hw) 4119{ 4120 u32 i; 4121 u32 rar_num; 4122 4123 e_dbg("e1000_init_rx_addrs"); 4124 4125 /* Setup the receive address. */ 4126 e_dbg("Programming MAC Address into RAR[0]\n"); 4127 4128 e1000_rar_set(hw, hw->mac_addr, 0); 4129 4130 rar_num = E1000_RAR_ENTRIES; 4131 4132 /* Zero out the other 15 receive addresses. */ 4133 e_dbg("Clearing RAR[1-15]\n"); 4134 for (i = 1; i < rar_num; i++) { 4135 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4136 E1000_WRITE_FLUSH(); 4137 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4138 E1000_WRITE_FLUSH(); 4139 } 4140} 4141 4142/** 4143 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table 4144 * @hw: Struct containing variables accessed by shared code 4145 * @mc_addr: the multicast address to hash 4146 */ 4147u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 4148{ 4149 u32 hash_value = 0; 4150 4151 /* The portion of the address that is used for the hash table is 4152 * determined by the mc_filter_type setting. 4153 */ 4154 switch (hw->mc_filter_type) { 4155 /* [0] [1] [2] [3] [4] [5] 4156 * 01 AA 00 12 34 56 4157 * LSB MSB 4158 */ 4159 case 0: 4160 /* [47:36] i.e. 0x563 for above example address */ 4161 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); 4162 break; 4163 case 1: 4164 /* [46:35] i.e. 0xAC6 for above example address */ 4165 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); 4166 break; 4167 case 2: 4168 /* [45:34] i.e. 0x5D8 for above example address */ 4169 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); 4170 break; 4171 case 3: 4172 /* [43:32] i.e. 0x634 for above example address */ 4173 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); 4174 break; 4175 } 4176 4177 hash_value &= 0xFFF; 4178 return hash_value; 4179} 4180 4181/** 4182 * e1000_rar_set - Puts an ethernet address into a receive address register. 4183 * @hw: Struct containing variables accessed by shared code 4184 * @addr: Address to put into receive address register 4185 * @index: Receive address register to write 4186 */ 4187void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 4188{ 4189 u32 rar_low, rar_high; 4190 4191 /* HW expects these in little endian so we reverse the byte order 4192 * from network order (big endian) to little endian 4193 */ 4194 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 4195 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 4196 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 4197 4198 switch (hw->mac_type) { 4199 default: 4200 /* Indicate to hardware the Address is Valid. */ 4201 rar_high |= E1000_RAH_AV; 4202 break; 4203 } 4204 4205 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 4206 E1000_WRITE_FLUSH(); 4207 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 4208 E1000_WRITE_FLUSH(); 4209} 4210 4211/** 4212 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. 4213 * @hw: Struct containing variables accessed by shared code 4214 * @offset: Offset in VLAN filer table to write 4215 * @value: Value to write into VLAN filter table 4216 */ 4217void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 4218{ 4219 u32 temp; 4220 4221 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 4222 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 4223 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4224 E1000_WRITE_FLUSH(); 4225 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 4226 E1000_WRITE_FLUSH(); 4227 } else { 4228 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4229 E1000_WRITE_FLUSH(); 4230 } 4231} 4232 4233/** 4234 * e1000_clear_vfta - Clears the VLAN filer table 4235 * @hw: Struct containing variables accessed by shared code 4236 */ 4237static void e1000_clear_vfta(struct e1000_hw *hw) 4238{ 4239 u32 offset; 4240 u32 vfta_value = 0; 4241 u32 vfta_offset = 0; 4242 u32 vfta_bit_in_reg = 0; 4243 4244 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 4245 /* If the offset we want to clear is the same offset of the 4246 * manageability VLAN ID, then clear all bits except that of the 4247 * manageability unit */ 4248 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 4249 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 4250 E1000_WRITE_FLUSH(); 4251 } 4252} 4253 4254static s32 e1000_id_led_init(struct e1000_hw *hw) 4255{ 4256 u32 ledctl; 4257 const u32 ledctl_mask = 0x000000FF; 4258 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 4259 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 4260 u16 eeprom_data, i, temp; 4261 const u16 led_mask = 0x0F; 4262 4263 e_dbg("e1000_id_led_init"); 4264 4265 if (hw->mac_type < e1000_82540) { 4266 /* Nothing to do */ 4267 return E1000_SUCCESS; 4268 } 4269 4270 ledctl = er32(LEDCTL); 4271 hw->ledctl_default = ledctl; 4272 hw->ledctl_mode1 = hw->ledctl_default; 4273 hw->ledctl_mode2 = hw->ledctl_default; 4274 4275 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 4276 e_dbg("EEPROM Read Error\n"); 4277 return -E1000_ERR_EEPROM; 4278 } 4279 4280 if ((eeprom_data == ID_LED_RESERVED_0000) || 4281 (eeprom_data == ID_LED_RESERVED_FFFF)) { 4282 eeprom_data = ID_LED_DEFAULT; 4283 } 4284 4285 for (i = 0; i < 4; i++) { 4286 temp = (eeprom_data >> (i << 2)) & led_mask; 4287 switch (temp) { 4288 case ID_LED_ON1_DEF2: 4289 case ID_LED_ON1_ON2: 4290 case ID_LED_ON1_OFF2: 4291 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4292 hw->ledctl_mode1 |= ledctl_on << (i << 3); 4293 break; 4294 case ID_LED_OFF1_DEF2: 4295 case ID_LED_OFF1_ON2: 4296 case ID_LED_OFF1_OFF2: 4297 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4298 hw->ledctl_mode1 |= ledctl_off << (i << 3); 4299 break; 4300 default: 4301 /* Do nothing */ 4302 break; 4303 } 4304 switch (temp) { 4305 case ID_LED_DEF1_ON2: 4306 case ID_LED_ON1_ON2: 4307 case ID_LED_OFF1_ON2: 4308 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4309 hw->ledctl_mode2 |= ledctl_on << (i << 3); 4310 break; 4311 case ID_LED_DEF1_OFF2: 4312 case ID_LED_ON1_OFF2: 4313 case ID_LED_OFF1_OFF2: 4314 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4315 hw->ledctl_mode2 |= ledctl_off << (i << 3); 4316 break; 4317 default: 4318 /* Do nothing */ 4319 break; 4320 } 4321 } 4322 return E1000_SUCCESS; 4323} 4324 4325/** 4326 * e1000_setup_led 4327 * @hw: Struct containing variables accessed by shared code 4328 * 4329 * Prepares SW controlable LED for use and saves the current state of the LED. 4330 */ 4331s32 e1000_setup_led(struct e1000_hw *hw) 4332{ 4333 u32 ledctl; 4334 s32 ret_val = E1000_SUCCESS; 4335 4336 e_dbg("e1000_setup_led"); 4337 4338 switch (hw->mac_type) { 4339 case e1000_82542_rev2_0: 4340 case e1000_82542_rev2_1: 4341 case e1000_82543: 4342 case e1000_82544: 4343 /* No setup necessary */ 4344 break; 4345 case e1000_82541: 4346 case e1000_82547: 4347 case e1000_82541_rev_2: 4348 case e1000_82547_rev_2: 4349 /* Turn off PHY Smart Power Down (if enabled) */ 4350 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 4351 &hw->phy_spd_default); 4352 if (ret_val) 4353 return ret_val; 4354 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4355 (u16) (hw->phy_spd_default & 4356 ~IGP01E1000_GMII_SPD)); 4357 if (ret_val) 4358 return ret_val; 4359 /* Fall Through */ 4360 default: 4361 if (hw->media_type == e1000_media_type_fiber) { 4362 ledctl = er32(LEDCTL); 4363 /* Save current LEDCTL settings */ 4364 hw->ledctl_default = ledctl; 4365 /* Turn off LED0 */ 4366 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 4367 E1000_LEDCTL_LED0_BLINK | 4368 E1000_LEDCTL_LED0_MODE_MASK); 4369 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 4370 E1000_LEDCTL_LED0_MODE_SHIFT); 4371 ew32(LEDCTL, ledctl); 4372 } else if (hw->media_type == e1000_media_type_copper) 4373 ew32(LEDCTL, hw->ledctl_mode1); 4374 break; 4375 } 4376 4377 return E1000_SUCCESS; 4378} 4379 4380/** 4381 * e1000_cleanup_led - Restores the saved state of the SW controlable LED. 4382 * @hw: Struct containing variables accessed by shared code 4383 */ 4384s32 e1000_cleanup_led(struct e1000_hw *hw) 4385{ 4386 s32 ret_val = E1000_SUCCESS; 4387 4388 e_dbg("e1000_cleanup_led"); 4389 4390 switch (hw->mac_type) { 4391 case e1000_82542_rev2_0: 4392 case e1000_82542_rev2_1: 4393 case e1000_82543: 4394 case e1000_82544: 4395 /* No cleanup necessary */ 4396 break; 4397 case e1000_82541: 4398 case e1000_82547: 4399 case e1000_82541_rev_2: 4400 case e1000_82547_rev_2: 4401 /* Turn on PHY Smart Power Down (if previously enabled) */ 4402 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4403 hw->phy_spd_default); 4404 if (ret_val) 4405 return ret_val; 4406 /* Fall Through */ 4407 default: 4408 /* Restore LEDCTL settings */ 4409 ew32(LEDCTL, hw->ledctl_default); 4410 break; 4411 } 4412 4413 return E1000_SUCCESS; 4414} 4415 4416/** 4417 * e1000_led_on - Turns on the software controllable LED 4418 * @hw: Struct containing variables accessed by shared code 4419 */ 4420s32 e1000_led_on(struct e1000_hw *hw) 4421{ 4422 u32 ctrl = er32(CTRL); 4423 4424 e_dbg("e1000_led_on"); 4425 4426 switch (hw->mac_type) { 4427 case e1000_82542_rev2_0: 4428 case e1000_82542_rev2_1: 4429 case e1000_82543: 4430 /* Set SW Defineable Pin 0 to turn on the LED */ 4431 ctrl |= E1000_CTRL_SWDPIN0; 4432 ctrl |= E1000_CTRL_SWDPIO0; 4433 break; 4434 case e1000_82544: 4435 if (hw->media_type == e1000_media_type_fiber) { 4436 /* Set SW Defineable Pin 0 to turn on the LED */ 4437 ctrl |= E1000_CTRL_SWDPIN0; 4438 ctrl |= E1000_CTRL_SWDPIO0; 4439 } else { 4440 /* Clear SW Defineable Pin 0 to turn on the LED */ 4441 ctrl &= ~E1000_CTRL_SWDPIN0; 4442 ctrl |= E1000_CTRL_SWDPIO0; 4443 } 4444 break; 4445 default: 4446 if (hw->media_type == e1000_media_type_fiber) { 4447 /* Clear SW Defineable Pin 0 to turn on the LED */ 4448 ctrl &= ~E1000_CTRL_SWDPIN0; 4449 ctrl |= E1000_CTRL_SWDPIO0; 4450 } else if (hw->media_type == e1000_media_type_copper) { 4451 ew32(LEDCTL, hw->ledctl_mode2); 4452 return E1000_SUCCESS; 4453 } 4454 break; 4455 } 4456 4457 ew32(CTRL, ctrl); 4458 4459 return E1000_SUCCESS; 4460} 4461 4462/** 4463 * e1000_led_off - Turns off the software controllable LED 4464 * @hw: Struct containing variables accessed by shared code 4465 */ 4466s32 e1000_led_off(struct e1000_hw *hw) 4467{ 4468 u32 ctrl = er32(CTRL); 4469 4470 e_dbg("e1000_led_off"); 4471 4472 switch (hw->mac_type) { 4473 case e1000_82542_rev2_0: 4474 case e1000_82542_rev2_1: 4475 case e1000_82543: 4476 /* Clear SW Defineable Pin 0 to turn off the LED */ 4477 ctrl &= ~E1000_CTRL_SWDPIN0; 4478 ctrl |= E1000_CTRL_SWDPIO0; 4479 break; 4480 case e1000_82544: 4481 if (hw->media_type == e1000_media_type_fiber) { 4482 /* Clear SW Defineable Pin 0 to turn off the LED */ 4483 ctrl &= ~E1000_CTRL_SWDPIN0; 4484 ctrl |= E1000_CTRL_SWDPIO0; 4485 } else { 4486 /* Set SW Defineable Pin 0 to turn off the LED */ 4487 ctrl |= E1000_CTRL_SWDPIN0; 4488 ctrl |= E1000_CTRL_SWDPIO0; 4489 } 4490 break; 4491 default: 4492 if (hw->media_type == e1000_media_type_fiber) { 4493 /* Set SW Defineable Pin 0 to turn off the LED */ 4494 ctrl |= E1000_CTRL_SWDPIN0; 4495 ctrl |= E1000_CTRL_SWDPIO0; 4496 } else if (hw->media_type == e1000_media_type_copper) { 4497 ew32(LEDCTL, hw->ledctl_mode1); 4498 return E1000_SUCCESS; 4499 } 4500 break; 4501 } 4502 4503 ew32(CTRL, ctrl); 4504 4505 return E1000_SUCCESS; 4506} 4507 4508/** 4509 * e1000_clear_hw_cntrs - Clears all hardware statistics counters. 4510 * @hw: Struct containing variables accessed by shared code 4511 */ 4512static void e1000_clear_hw_cntrs(struct e1000_hw *hw) 4513{ 4514 volatile u32 temp; 4515 4516 temp = er32(CRCERRS); 4517 temp = er32(SYMERRS); 4518 temp = er32(MPC); 4519 temp = er32(SCC); 4520 temp = er32(ECOL); 4521 temp = er32(MCC); 4522 temp = er32(LATECOL); 4523 temp = er32(COLC); 4524 temp = er32(DC); 4525 temp = er32(SEC); 4526 temp = er32(RLEC); 4527 temp = er32(XONRXC); 4528 temp = er32(XONTXC); 4529 temp = er32(XOFFRXC); 4530 temp = er32(XOFFTXC); 4531 temp = er32(FCRUC); 4532 4533 temp = er32(PRC64); 4534 temp = er32(PRC127); 4535 temp = er32(PRC255); 4536 temp = er32(PRC511); 4537 temp = er32(PRC1023); 4538 temp = er32(PRC1522); 4539 4540 temp = er32(GPRC); 4541 temp = er32(BPRC); 4542 temp = er32(MPRC); 4543 temp = er32(GPTC); 4544 temp = er32(GORCL); 4545 temp = er32(GORCH); 4546 temp = er32(GOTCL); 4547 temp = er32(GOTCH); 4548 temp = er32(RNBC); 4549 temp = er32(RUC); 4550 temp = er32(RFC); 4551 temp = er32(ROC); 4552 temp = er32(RJC); 4553 temp = er32(TORL); 4554 temp = er32(TORH); 4555 temp = er32(TOTL); 4556 temp = er32(TOTH); 4557 temp = er32(TPR); 4558 temp = er32(TPT); 4559 4560 temp = er32(PTC64); 4561 temp = er32(PTC127); 4562 temp = er32(PTC255); 4563 temp = er32(PTC511); 4564 temp = er32(PTC1023); 4565 temp = er32(PTC1522); 4566 4567 temp = er32(MPTC); 4568 temp = er32(BPTC); 4569 4570 if (hw->mac_type < e1000_82543) 4571 return; 4572 4573 temp = er32(ALGNERRC); 4574 temp = er32(RXERRC); 4575 temp = er32(TNCRS); 4576 temp = er32(CEXTERR); 4577 temp = er32(TSCTC); 4578 temp = er32(TSCTFC); 4579 4580 if (hw->mac_type <= e1000_82544) 4581 return; 4582 4583 temp = er32(MGTPRC); 4584 temp = er32(MGTPDC); 4585 temp = er32(MGTPTC); 4586} 4587 4588/** 4589 * e1000_reset_adaptive - Resets Adaptive IFS to its default state. 4590 * @hw: Struct containing variables accessed by shared code 4591 * 4592 * Call this after e1000_init_hw. You may override the IFS defaults by setting 4593 * hw->ifs_params_forced to true. However, you must initialize hw-> 4594 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 4595 * before calling this function. 4596 */ 4597void e1000_reset_adaptive(struct e1000_hw *hw) 4598{ 4599 e_dbg("e1000_reset_adaptive"); 4600 4601 if (hw->adaptive_ifs) { 4602 if (!hw->ifs_params_forced) { 4603 hw->current_ifs_val = 0; 4604 hw->ifs_min_val = IFS_MIN; 4605 hw->ifs_max_val = IFS_MAX; 4606 hw->ifs_step_size = IFS_STEP; 4607 hw->ifs_ratio = IFS_RATIO; 4608 } 4609 hw->in_ifs_mode = false; 4610 ew32(AIT, 0); 4611 } else { 4612 e_dbg("Not in Adaptive IFS mode!\n"); 4613 } 4614} 4615 4616/** 4617 * e1000_update_adaptive - update adaptive IFS 4618 * @hw: Struct containing variables accessed by shared code 4619 * @tx_packets: Number of transmits since last callback 4620 * @total_collisions: Number of collisions since last callback 4621 * 4622 * Called during the callback/watchdog routine to update IFS value based on 4623 * the ratio of transmits to collisions. 4624 */ 4625void e1000_update_adaptive(struct e1000_hw *hw) 4626{ 4627 e_dbg("e1000_update_adaptive"); 4628 4629 if (hw->adaptive_ifs) { 4630 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { 4631 if (hw->tx_packet_delta > MIN_NUM_XMITS) { 4632 hw->in_ifs_mode = true; 4633 if (hw->current_ifs_val < hw->ifs_max_val) { 4634 if (hw->current_ifs_val == 0) 4635 hw->current_ifs_val = 4636 hw->ifs_min_val; 4637 else 4638 hw->current_ifs_val += 4639 hw->ifs_step_size; 4640 ew32(AIT, hw->current_ifs_val); 4641 } 4642 } 4643 } else { 4644 if (hw->in_ifs_mode 4645 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 4646 hw->current_ifs_val = 0; 4647 hw->in_ifs_mode = false; 4648 ew32(AIT, 0); 4649 } 4650 } 4651 } else { 4652 e_dbg("Not in Adaptive IFS mode!\n"); 4653 } 4654} 4655 4656/** 4657 * e1000_tbi_adjust_stats 4658 * @hw: Struct containing variables accessed by shared code 4659 * @frame_len: The length of the frame in question 4660 * @mac_addr: The Ethernet destination address of the frame in question 4661 * 4662 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 4663 */ 4664void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, 4665 u32 frame_len, u8 *mac_addr) 4666{ 4667 u64 carry_bit; 4668 4669 /* First adjust the frame length. */ 4670 frame_len--; 4671 /* We need to adjust the statistics counters, since the hardware 4672 * counters overcount this packet as a CRC error and undercount 4673 * the packet as a good packet 4674 */ 4675 /* This packet should not be counted as a CRC error. */ 4676 stats->crcerrs--; 4677 /* This packet does count as a Good Packet Received. */ 4678 stats->gprc++; 4679 4680 /* Adjust the Good Octets received counters */ 4681 carry_bit = 0x80000000 & stats->gorcl; 4682 stats->gorcl += frame_len; 4683 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 4684 * Received Count) was one before the addition, 4685 * AND it is zero after, then we lost the carry out, 4686 * need to add one to Gorch (Good Octets Received Count High). 4687 * This could be simplified if all environments supported 4688 * 64-bit integers. 4689 */ 4690 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 4691 stats->gorch++; 4692 /* Is this a broadcast or multicast? Check broadcast first, 4693 * since the test for a multicast frame will test positive on 4694 * a broadcast frame. 4695 */ 4696 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) 4697 /* Broadcast packet */ 4698 stats->bprc++; 4699 else if (*mac_addr & 0x01) 4700 /* Multicast packet */ 4701 stats->mprc++; 4702 4703 if (frame_len == hw->max_frame_size) { 4704 /* In this case, the hardware has overcounted the number of 4705 * oversize frames. 4706 */ 4707 if (stats->roc > 0) 4708 stats->roc--; 4709 } 4710 4711 /* Adjust the bin counters when the extra byte put the frame in the 4712 * wrong bin. Remember that the frame_len was adjusted above. 4713 */ 4714 if (frame_len == 64) { 4715 stats->prc64++; 4716 stats->prc127--; 4717 } else if (frame_len == 127) { 4718 stats->prc127++; 4719 stats->prc255--; 4720 } else if (frame_len == 255) { 4721 stats->prc255++; 4722 stats->prc511--; 4723 } else if (frame_len == 511) { 4724 stats->prc511++; 4725 stats->prc1023--; 4726 } else if (frame_len == 1023) { 4727 stats->prc1023++; 4728 stats->prc1522--; 4729 } else if (frame_len == 1522) { 4730 stats->prc1522++; 4731 } 4732} 4733 4734/** 4735 * e1000_get_bus_info 4736 * @hw: Struct containing variables accessed by shared code 4737 * 4738 * Gets the current PCI bus type, speed, and width of the hardware 4739 */ 4740void e1000_get_bus_info(struct e1000_hw *hw) 4741{ 4742 u32 status; 4743 4744 switch (hw->mac_type) { 4745 case e1000_82542_rev2_0: 4746 case e1000_82542_rev2_1: 4747 hw->bus_type = e1000_bus_type_pci; 4748 hw->bus_speed = e1000_bus_speed_unknown; 4749 hw->bus_width = e1000_bus_width_unknown; 4750 break; 4751 default: 4752 status = er32(STATUS); 4753 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4754 e1000_bus_type_pcix : e1000_bus_type_pci; 4755 4756 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 4757 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 4758 e1000_bus_speed_66 : e1000_bus_speed_120; 4759 } else if (hw->bus_type == e1000_bus_type_pci) { 4760 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 4761 e1000_bus_speed_66 : e1000_bus_speed_33; 4762 } else { 4763 switch (status & E1000_STATUS_PCIX_SPEED) { 4764 case E1000_STATUS_PCIX_SPEED_66: 4765 hw->bus_speed = e1000_bus_speed_66; 4766 break; 4767 case E1000_STATUS_PCIX_SPEED_100: 4768 hw->bus_speed = e1000_bus_speed_100; 4769 break; 4770 case E1000_STATUS_PCIX_SPEED_133: 4771 hw->bus_speed = e1000_bus_speed_133; 4772 break; 4773 default: 4774 hw->bus_speed = e1000_bus_speed_reserved; 4775 break; 4776 } 4777 } 4778 hw->bus_width = (status & E1000_STATUS_BUS64) ? 4779 e1000_bus_width_64 : e1000_bus_width_32; 4780 break; 4781 } 4782} 4783 4784/** 4785 * e1000_write_reg_io 4786 * @hw: Struct containing variables accessed by shared code 4787 * @offset: offset to write to 4788 * @value: value to write 4789 * 4790 * Writes a value to one of the devices registers using port I/O (as opposed to 4791 * memory mapped I/O). Only 82544 and newer devices support port I/O. 4792 */ 4793static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) 4794{ 4795 unsigned long io_addr = hw->io_base; 4796 unsigned long io_data = hw->io_base + 4; 4797 4798 e1000_io_write(hw, io_addr, offset); 4799 e1000_io_write(hw, io_data, value); 4800} 4801 4802/** 4803 * e1000_get_cable_length - Estimates the cable length. 4804 * @hw: Struct containing variables accessed by shared code 4805 * @min_length: The estimated minimum length 4806 * @max_length: The estimated maximum length 4807 * 4808 * returns: - E1000_ERR_XXX 4809 * E1000_SUCCESS 4810 * 4811 * This function always returns a ranged length (minimum & maximum). 4812 * So for M88 phy's, this function interprets the one value returned from the 4813 * register to the minimum and maximum range. 4814 * For IGP phy's, the function calculates the range by the AGC registers. 4815 */ 4816static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 4817 u16 *max_length) 4818{ 4819 s32 ret_val; 4820 u16 agc_value = 0; 4821 u16 i, phy_data; 4822 u16 cable_length; 4823 4824 e_dbg("e1000_get_cable_length"); 4825 4826 *min_length = *max_length = 0; 4827 4828 /* Use old method for Phy older than IGP */ 4829 if (hw->phy_type == e1000_phy_m88) { 4830 4831 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 4832 &phy_data); 4833 if (ret_val) 4834 return ret_val; 4835 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4836 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 4837 4838 /* Convert the enum value to ranged values */ 4839 switch (cable_length) { 4840 case e1000_cable_length_50: 4841 *min_length = 0; 4842 *max_length = e1000_igp_cable_length_50; 4843 break; 4844 case e1000_cable_length_50_80: 4845 *min_length = e1000_igp_cable_length_50; 4846 *max_length = e1000_igp_cable_length_80; 4847 break; 4848 case e1000_cable_length_80_110: 4849 *min_length = e1000_igp_cable_length_80; 4850 *max_length = e1000_igp_cable_length_110; 4851 break; 4852 case e1000_cable_length_110_140: 4853 *min_length = e1000_igp_cable_length_110; 4854 *max_length = e1000_igp_cable_length_140; 4855 break; 4856 case e1000_cable_length_140: 4857 *min_length = e1000_igp_cable_length_140; 4858 *max_length = e1000_igp_cable_length_170; 4859 break; 4860 default: 4861 return -E1000_ERR_PHY; 4862 break; 4863 } 4864 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 4865 u16 cur_agc_value; 4866 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 4867 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 4868 { IGP01E1000_PHY_AGC_A, 4869 IGP01E1000_PHY_AGC_B, 4870 IGP01E1000_PHY_AGC_C, 4871 IGP01E1000_PHY_AGC_D 4872 }; 4873 /* Read the AGC registers for all channels */ 4874 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 4875 4876 ret_val = 4877 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 4878 if (ret_val) 4879 return ret_val; 4880 4881 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 4882 4883 /* Value bound check. */ 4884 if ((cur_agc_value >= 4885 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) 4886 || (cur_agc_value == 0)) 4887 return -E1000_ERR_PHY; 4888 4889 agc_value += cur_agc_value; 4890 4891 /* Update minimal AGC value. */ 4892 if (min_agc_value > cur_agc_value) 4893 min_agc_value = cur_agc_value; 4894 } 4895 4896 /* Remove the minimal AGC result for length < 50m */ 4897 if (agc_value < 4898 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 4899 agc_value -= min_agc_value; 4900 4901 /* Get the average length of the remaining 3 channels */ 4902 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 4903 } else { 4904 /* Get the average length of all the 4 channels. */ 4905 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 4906 } 4907 4908 /* Set the range of the calculated length. */ 4909 *min_length = ((e1000_igp_cable_length_table[agc_value] - 4910 IGP01E1000_AGC_RANGE) > 0) ? 4911 (e1000_igp_cable_length_table[agc_value] - 4912 IGP01E1000_AGC_RANGE) : 0; 4913 *max_length = e1000_igp_cable_length_table[agc_value] + 4914 IGP01E1000_AGC_RANGE; 4915 } 4916 4917 return E1000_SUCCESS; 4918} 4919 4920/** 4921 * e1000_check_polarity - Check the cable polarity 4922 * @hw: Struct containing variables accessed by shared code 4923 * @polarity: output parameter : 0 - Polarity is not reversed 4924 * 1 - Polarity is reversed. 4925 * 4926 * returns: - E1000_ERR_XXX 4927 * E1000_SUCCESS 4928 * 4929 * For phy's older than IGP, this function simply reads the polarity bit in the 4930 * Phy Status register. For IGP phy's, this bit is valid only if link speed is 4931 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 4932 * return 0. If the link speed is 1000 Mbps the polarity status is in the 4933 * IGP01E1000_PHY_PCS_INIT_REG. 4934 */ 4935static s32 e1000_check_polarity(struct e1000_hw *hw, 4936 e1000_rev_polarity *polarity) 4937{ 4938 s32 ret_val; 4939 u16 phy_data; 4940 4941 e_dbg("e1000_check_polarity"); 4942 4943 if (hw->phy_type == e1000_phy_m88) { 4944 /* return the Polarity bit in the Status register. */ 4945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 4946 &phy_data); 4947 if (ret_val) 4948 return ret_val; 4949 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 4950 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 4951 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 4952 4953 } else if (hw->phy_type == e1000_phy_igp) { 4954 /* Read the Status register to check the speed */ 4955 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 4956 &phy_data); 4957 if (ret_val) 4958 return ret_val; 4959 4960 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 4961 * find the polarity status */ 4962 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 4963 IGP01E1000_PSSR_SPEED_1000MBPS) { 4964 4965 /* Read the GIG initialization PCS register (0x00B4) */ 4966 ret_val = 4967 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 4968 &phy_data); 4969 if (ret_val) 4970 return ret_val; 4971 4972 /* Check the polarity bits */ 4973 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 4974 e1000_rev_polarity_reversed : 4975 e1000_rev_polarity_normal; 4976 } else { 4977 /* For 10 Mbps, read the polarity bit in the status register. (for 4978 * 100 Mbps this bit is always 0) */ 4979 *polarity = 4980 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 4981 e1000_rev_polarity_reversed : 4982 e1000_rev_polarity_normal; 4983 } 4984 } 4985 return E1000_SUCCESS; 4986} 4987 4988/** 4989 * e1000_check_downshift - Check if Downshift occurred 4990 * @hw: Struct containing variables accessed by shared code 4991 * @downshift: output parameter : 0 - No Downshift occurred. 4992 * 1 - Downshift occurred. 4993 * 4994 * returns: - E1000_ERR_XXX 4995 * E1000_SUCCESS 4996 * 4997 * For phy's older than IGP, this function reads the Downshift bit in the Phy 4998 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 4999 * Link Health register. In IGP this bit is latched high, so the driver must 5000 * read it immediately after link is established. 5001 */ 5002static s32 e1000_check_downshift(struct e1000_hw *hw) 5003{ 5004 s32 ret_val; 5005 u16 phy_data; 5006 5007 e_dbg("e1000_check_downshift"); 5008 5009 if (hw->phy_type == e1000_phy_igp) { 5010 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5011 &phy_data); 5012 if (ret_val) 5013 return ret_val; 5014 5015 hw->speed_downgraded = 5016 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 5017 } else if (hw->phy_type == e1000_phy_m88) { 5018 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5019 &phy_data); 5020 if (ret_val) 5021 return ret_val; 5022 5023 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5024 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5025 } 5026 5027 return E1000_SUCCESS; 5028} 5029 5030/** 5031 * e1000_config_dsp_after_link_change 5032 * @hw: Struct containing variables accessed by shared code 5033 * @link_up: was link up at the time this was called 5034 * 5035 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5036 * E1000_SUCCESS at any other case. 5037 * 5038 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 5039 * gigabit link is achieved to improve link quality. 5040 */ 5041 5042static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) 5043{ 5044 s32 ret_val; 5045 u16 phy_data, phy_saved_data, speed, duplex, i; 5046 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 5047 { IGP01E1000_PHY_AGC_PARAM_A, 5048 IGP01E1000_PHY_AGC_PARAM_B, 5049 IGP01E1000_PHY_AGC_PARAM_C, 5050 IGP01E1000_PHY_AGC_PARAM_D 5051 }; 5052 u16 min_length, max_length; 5053 5054 e_dbg("e1000_config_dsp_after_link_change"); 5055 5056 if (hw->phy_type != e1000_phy_igp) 5057 return E1000_SUCCESS; 5058 5059 if (link_up) { 5060 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 5061 if (ret_val) { 5062 e_dbg("Error getting link speed and duplex\n"); 5063 return ret_val; 5064 } 5065 5066 if (speed == SPEED_1000) { 5067 5068 ret_val = 5069 e1000_get_cable_length(hw, &min_length, 5070 &max_length); 5071 if (ret_val) 5072 return ret_val; 5073 5074 if ((hw->dsp_config_state == e1000_dsp_config_enabled) 5075 && min_length >= e1000_igp_cable_length_50) { 5076 5077 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5078 ret_val = 5079 e1000_read_phy_reg(hw, 5080 dsp_reg_array[i], 5081 &phy_data); 5082 if (ret_val) 5083 return ret_val; 5084 5085 phy_data &= 5086 ~IGP01E1000_PHY_EDAC_MU_INDEX; 5087 5088 ret_val = 5089 e1000_write_phy_reg(hw, 5090 dsp_reg_array 5091 [i], phy_data); 5092 if (ret_val) 5093 return ret_val; 5094 } 5095 hw->dsp_config_state = 5096 e1000_dsp_config_activated; 5097 } 5098 5099 if ((hw->ffe_config_state == e1000_ffe_config_enabled) 5100 && (min_length < e1000_igp_cable_length_50)) { 5101 5102 u16 ffe_idle_err_timeout = 5103 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 5104 u32 idle_errs = 0; 5105 5106 /* clear previous idle error counts */ 5107 ret_val = 5108 e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5109 &phy_data); 5110 if (ret_val) 5111 return ret_val; 5112 5113 for (i = 0; i < ffe_idle_err_timeout; i++) { 5114 udelay(1000); 5115 ret_val = 5116 e1000_read_phy_reg(hw, 5117 PHY_1000T_STATUS, 5118 &phy_data); 5119 if (ret_val) 5120 return ret_val; 5121 5122 idle_errs += 5123 (phy_data & 5124 SR_1000T_IDLE_ERROR_CNT); 5125 if (idle_errs > 5126 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) 5127 { 5128 hw->ffe_config_state = 5129 e1000_ffe_config_active; 5130 5131 ret_val = 5132 e1000_write_phy_reg(hw, 5133 IGP01E1000_PHY_DSP_FFE, 5134 IGP01E1000_PHY_DSP_FFE_CM_CP); 5135 if (ret_val) 5136 return ret_val; 5137 break; 5138 } 5139 5140 if (idle_errs) 5141 ffe_idle_err_timeout = 5142 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 5143 } 5144 } 5145 } 5146 } else { 5147 if (hw->dsp_config_state == e1000_dsp_config_activated) { 5148 /* Save off the current value of register 0x2F5B to be restored at 5149 * the end of the routines. */ 5150 ret_val = 5151 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5152 5153 if (ret_val) 5154 return ret_val; 5155 5156 /* Disable the PHY transmitter */ 5157 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5158 5159 if (ret_val) 5160 return ret_val; 5161 5162 mdelay(20); 5163 5164 ret_val = e1000_write_phy_reg(hw, 0x0000, 5165 IGP01E1000_IEEE_FORCE_GIGA); 5166 if (ret_val) 5167 return ret_val; 5168 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5169 ret_val = 5170 e1000_read_phy_reg(hw, dsp_reg_array[i], 5171 &phy_data); 5172 if (ret_val) 5173 return ret_val; 5174 5175 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5176 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 5177 5178 ret_val = 5179 e1000_write_phy_reg(hw, dsp_reg_array[i], 5180 phy_data); 5181 if (ret_val) 5182 return ret_val; 5183 } 5184 5185 ret_val = e1000_write_phy_reg(hw, 0x0000, 5186 IGP01E1000_IEEE_RESTART_AUTONEG); 5187 if (ret_val) 5188 return ret_val; 5189 5190 mdelay(20); 5191 5192 /* Now enable the transmitter */ 5193 ret_val = 5194 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5195 5196 if (ret_val) 5197 return ret_val; 5198 5199 hw->dsp_config_state = e1000_dsp_config_enabled; 5200 } 5201 5202 if (hw->ffe_config_state == e1000_ffe_config_active) { 5203 /* Save off the current value of register 0x2F5B to be restored at 5204 * the end of the routines. */ 5205 ret_val = 5206 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5207 5208 if (ret_val) 5209 return ret_val; 5210 5211 /* Disable the PHY transmitter */ 5212 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5213 5214 if (ret_val) 5215 return ret_val; 5216 5217 mdelay(20); 5218 5219 ret_val = e1000_write_phy_reg(hw, 0x0000, 5220 IGP01E1000_IEEE_FORCE_GIGA); 5221 if (ret_val) 5222 return ret_val; 5223 ret_val = 5224 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 5225 IGP01E1000_PHY_DSP_FFE_DEFAULT); 5226 if (ret_val) 5227 return ret_val; 5228 5229 ret_val = e1000_write_phy_reg(hw, 0x0000, 5230 IGP01E1000_IEEE_RESTART_AUTONEG); 5231 if (ret_val) 5232 return ret_val; 5233 5234 mdelay(20); 5235 5236 /* Now enable the transmitter */ 5237 ret_val = 5238 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5239 5240 if (ret_val) 5241 return ret_val; 5242 5243 hw->ffe_config_state = e1000_ffe_config_enabled; 5244 } 5245 } 5246 return E1000_SUCCESS; 5247} 5248 5249/** 5250 * e1000_set_phy_mode - Set PHY to class A mode 5251 * @hw: Struct containing variables accessed by shared code 5252 * 5253 * Assumes the following operations will follow to enable the new class mode. 5254 * 1. Do a PHY soft reset 5255 * 2. Restart auto-negotiation or force link. 5256 */ 5257static s32 e1000_set_phy_mode(struct e1000_hw *hw) 5258{ 5259 s32 ret_val; 5260 u16 eeprom_data; 5261 5262 e_dbg("e1000_set_phy_mode"); 5263 5264 if ((hw->mac_type == e1000_82545_rev_3) && 5265 (hw->media_type == e1000_media_type_copper)) { 5266 ret_val = 5267 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 5268 &eeprom_data); 5269 if (ret_val) { 5270 return ret_val; 5271 } 5272 5273 if ((eeprom_data != EEPROM_RESERVED_WORD) && 5274 (eeprom_data & EEPROM_PHY_CLASS_A)) { 5275 ret_val = 5276 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 5277 0x000B); 5278 if (ret_val) 5279 return ret_val; 5280 ret_val = 5281 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 5282 0x8104); 5283 if (ret_val) 5284 return ret_val; 5285 5286 hw->phy_reset_disable = false; 5287 } 5288 } 5289 5290 return E1000_SUCCESS; 5291} 5292 5293/** 5294 * e1000_set_d3_lplu_state - set d3 link power state 5295 * @hw: Struct containing variables accessed by shared code 5296 * @active: true to enable lplu false to disable lplu. 5297 * 5298 * This function sets the lplu state according to the active flag. When 5299 * activating lplu this function also disables smart speed and vise versa. 5300 * lplu will not be activated unless the device autonegotiation advertisement 5301 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 5302 * 5303 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5304 * E1000_SUCCESS at any other case. 5305 */ 5306static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 5307{ 5308 s32 ret_val; 5309 u16 phy_data; 5310 e_dbg("e1000_set_d3_lplu_state"); 5311 5312 if (hw->phy_type != e1000_phy_igp) 5313 return E1000_SUCCESS; 5314 5315 /* During driver activity LPLU should not be used or it will attain link 5316 * from the lowest speeds starting from 10Mbps. The capability is used for 5317 * Dx transitions and states */ 5318 if (hw->mac_type == e1000_82541_rev_2 5319 || hw->mac_type == e1000_82547_rev_2) { 5320 ret_val = 5321 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5322 if (ret_val) 5323 return ret_val; 5324 } 5325 5326 if (!active) { 5327 if (hw->mac_type == e1000_82541_rev_2 || 5328 hw->mac_type == e1000_82547_rev_2) { 5329 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 5330 ret_val = 5331 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5332 phy_data); 5333 if (ret_val) 5334 return ret_val; 5335 } 5336 5337 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 5338 * Dx states where the power conservation is most important. During 5339 * driver activity we should enable SmartSpeed, so performance is 5340 * maintained. */ 5341 if (hw->smart_speed == e1000_smart_speed_on) { 5342 ret_val = 5343 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5344 &phy_data); 5345 if (ret_val) 5346 return ret_val; 5347 5348 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 5349 ret_val = 5350 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5351 phy_data); 5352 if (ret_val) 5353 return ret_val; 5354 } else if (hw->smart_speed == e1000_smart_speed_off) { 5355 ret_val = 5356 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5357 &phy_data); 5358 if (ret_val) 5359 return ret_val; 5360 5361 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5362 ret_val = 5363 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5364 phy_data); 5365 if (ret_val) 5366 return ret_val; 5367 } 5368 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 5369 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) 5370 || (hw->autoneg_advertised == 5371 AUTONEG_ADVERTISE_10_100_ALL)) { 5372 5373 if (hw->mac_type == e1000_82541_rev_2 || 5374 hw->mac_type == e1000_82547_rev_2) { 5375 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5376 ret_val = 5377 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5378 phy_data); 5379 if (ret_val) 5380 return ret_val; 5381 } 5382 5383 /* When LPLU is enabled we should disable SmartSpeed */ 5384 ret_val = 5385 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5386 &phy_data); 5387 if (ret_val) 5388 return ret_val; 5389 5390 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5391 ret_val = 5392 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5393 phy_data); 5394 if (ret_val) 5395 return ret_val; 5396 5397 } 5398 return E1000_SUCCESS; 5399} 5400 5401/** 5402 * e1000_set_vco_speed 5403 * @hw: Struct containing variables accessed by shared code 5404 * 5405 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 5406 */ 5407static s32 e1000_set_vco_speed(struct e1000_hw *hw) 5408{ 5409 s32 ret_val; 5410 u16 default_page = 0; 5411 u16 phy_data; 5412 5413 e_dbg("e1000_set_vco_speed"); 5414 5415 switch (hw->mac_type) { 5416 case e1000_82545_rev_3: 5417 case e1000_82546_rev_3: 5418 break; 5419 default: 5420 return E1000_SUCCESS; 5421 } 5422 5423 /* Set PHY register 30, page 5, bit 8 to 0 */ 5424 5425 ret_val = 5426 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 5427 if (ret_val) 5428 return ret_val; 5429 5430 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 5431 if (ret_val) 5432 return ret_val; 5433 5434 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5435 if (ret_val) 5436 return ret_val; 5437 5438 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 5439 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5440 if (ret_val) 5441 return ret_val; 5442 5443 /* Set PHY register 30, page 4, bit 11 to 1 */ 5444 5445 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 5446 if (ret_val) 5447 return ret_val; 5448 5449 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5450 if (ret_val) 5451 return ret_val; 5452 5453 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 5454 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5455 if (ret_val) 5456 return ret_val; 5457 5458 ret_val = 5459 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 5460 if (ret_val) 5461 return ret_val; 5462 5463 return E1000_SUCCESS; 5464} 5465 5466 5467/** 5468 * e1000_enable_mng_pass_thru - check for bmc pass through 5469 * @hw: Struct containing variables accessed by shared code 5470 * 5471 * Verifies the hardware needs to allow ARPs to be processed by the host 5472 * returns: - true/false 5473 */ 5474u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) 5475{ 5476 u32 manc; 5477 5478 if (hw->asf_firmware_present) { 5479 manc = er32(MANC); 5480 5481 if (!(manc & E1000_MANC_RCV_TCO_EN) || 5482 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 5483 return false; 5484 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) 5485 return true; 5486 } 5487 return false; 5488} 5489 5490static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) 5491{ 5492 s32 ret_val; 5493 u16 mii_status_reg; 5494 u16 i; 5495 5496 5497 /* Disable the transmitter on the PHY */ 5498 5499 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5500 if (ret_val) 5501 return ret_val; 5502 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 5503 if (ret_val) 5504 return ret_val; 5505 5506 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5507 if (ret_val) 5508 return ret_val; 5509 5510 /* This loop will early-out if the NO link condition has been met. */ 5511 for (i = PHY_FORCE_TIME; i > 0; i--) { 5512 /* Read the MII Status Register and wait for Link Status bit 5513 * to be clear. 5514 */ 5515 5516 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5517 if (ret_val) 5518 return ret_val; 5519 5520 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5521 if (ret_val) 5522 return ret_val; 5523 5524 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 5525 break; 5526 mdelay(100); 5527 } 5528 5529 /* Recommended delay time after link has been lost */ 5530 mdelay(1000); 5531 5532 /* Now we will re-enable th transmitter on the PHY */ 5533 5534 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5535 if (ret_val) 5536 return ret_val; 5537 mdelay(50); 5538 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 5539 if (ret_val) 5540 return ret_val; 5541 mdelay(50); 5542 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 5543 if (ret_val) 5544 return ret_val; 5545 mdelay(50); 5546 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 5547 if (ret_val) 5548 return ret_val; 5549 5550 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5551 if (ret_val) 5552 return ret_val; 5553 5554 /* This loop will early-out if the link condition has been met. */ 5555 for (i = PHY_FORCE_TIME; i > 0; i--) { 5556 /* Read the MII Status Register and wait for Link Status bit 5557 * to be set. 5558 */ 5559 5560 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5561 if (ret_val) 5562 return ret_val; 5563 5564 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5565 if (ret_val) 5566 return ret_val; 5567 5568 if (mii_status_reg & MII_SR_LINK_STATUS) 5569 break; 5570 mdelay(100); 5571 } 5572 return E1000_SUCCESS; 5573} 5574 5575/** 5576 * e1000_get_auto_rd_done 5577 * @hw: Struct containing variables accessed by shared code 5578 * 5579 * Check for EEPROM Auto Read bit done. 5580 * returns: - E1000_ERR_RESET if fail to reset MAC 5581 * E1000_SUCCESS at any other case. 5582 */ 5583static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5584{ 5585 e_dbg("e1000_get_auto_rd_done"); 5586 msleep(5); 5587 return E1000_SUCCESS; 5588} 5589 5590/** 5591 * e1000_get_phy_cfg_done 5592 * @hw: Struct containing variables accessed by shared code 5593 * 5594 * Checks if the PHY configuration is done 5595 * returns: - E1000_ERR_RESET if fail to reset MAC 5596 * E1000_SUCCESS at any other case. 5597 */ 5598static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5599{ 5600 e_dbg("e1000_get_phy_cfg_done"); 5601 mdelay(10); 5602 return E1000_SUCCESS; 5603} 5604