1/* 2 * drivers/mtd/nand/ppchameleonevb.c 3 * 4 * Copyright (C) 2003 DAVE Srl (info@wawnet.biz) 5 * 6 * Derived from drivers/mtd/nand/edb7312.c 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Overview: 14 * This is a device driver for the NAND flash devices found on the 15 * PPChameleon/PPChameleonEVB system. 16 * PPChameleon options (autodetected): 17 * - BA model: no NAND 18 * - ME model: 32MB (Samsung K9F5608U0B) 19 * - HI model: 128MB (Samsung K9F1G08UOM) 20 * PPChameleonEVB options: 21 * - 32MB (Samsung K9F5608U0B) 22 */ 23 24#include <linux/init.h> 25#include <linux/slab.h> 26#include <linux/module.h> 27#include <linux/mtd/mtd.h> 28#include <linux/mtd/nand.h> 29#include <linux/mtd/partitions.h> 30#include <asm/io.h> 31#include <platforms/PPChameleonEVB.h> 32 33#undef USE_READY_BUSY_PIN 34#define USE_READY_BUSY_PIN 35/* see datasheets (tR) */ 36#define NAND_BIG_DELAY_US 25 37#define NAND_SMALL_DELAY_US 10 38 39/* handy sizes */ 40#define SZ_4M 0x00400000 41#define NAND_SMALL_SIZE 0x02000000 42#define NAND_MTD_NAME "ppchameleon-nand" 43#define NAND_EVB_MTD_NAME "ppchameleonevb-nand" 44 45/* GPIO pins used to drive NAND chip mounted on processor module */ 46#define NAND_nCE_GPIO_PIN (0x80000000 >> 1) 47#define NAND_CLE_GPIO_PIN (0x80000000 >> 2) 48#define NAND_ALE_GPIO_PIN (0x80000000 >> 3) 49#define NAND_RB_GPIO_PIN (0x80000000 >> 4) 50/* GPIO pins used to drive NAND chip mounted on EVB */ 51#define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14) 52#define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15) 53#define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16) 54#define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31) 55 56/* 57 * MTD structure for PPChameleonEVB board 58 */ 59static struct mtd_info *ppchameleon_mtd = NULL; 60static struct mtd_info *ppchameleonevb_mtd = NULL; 61 62/* 63 * Module stuff 64 */ 65static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR; 66static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR; 67 68#ifdef MODULE 69module_param(ppchameleon_fio_pbase, ulong, 0); 70module_param(ppchameleonevb_fio_pbase, ulong, 0); 71#else 72__setup("ppchameleon_fio_pbase=", ppchameleon_fio_pbase); 73__setup("ppchameleonevb_fio_pbase=", ppchameleonevb_fio_pbase); 74#endif 75 76#ifdef CONFIG_MTD_PARTITIONS 77/* 78 * Define static partitions for flash devices 79 */ 80static struct mtd_partition partition_info_hi[] = { 81 { .name = "PPChameleon HI Nand Flash", 82 .offset = 0, 83 .size = 128 * 1024 * 1024 84 } 85}; 86 87static struct mtd_partition partition_info_me[] = { 88 { .name = "PPChameleon ME Nand Flash", 89 .offset = 0, 90 .size = 32 * 1024 * 1024 91 } 92}; 93 94static struct mtd_partition partition_info_evb[] = { 95 { .name = "PPChameleonEVB Nand Flash", 96 .offset = 0, 97 .size = 32 * 1024 * 1024 98 } 99}; 100 101#define NUM_PARTITIONS 1 102 103extern int parse_cmdline_partitions(struct mtd_info *master, struct mtd_partition **pparts, const char *mtd_id); 104#endif 105 106/* 107 * hardware specific access to control-lines 108 */ 109static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd, 110 unsigned int ctrl) 111{ 112 struct nand_chip *chip = mtd->priv; 113 114 if (ctrl & NAND_CTRL_CHANGE) { 115#error Missing headerfiles. No way to fix this. -tglx 116 switch (cmd) { 117 case NAND_CTL_SETCLE: 118 MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR); 119 break; 120 case NAND_CTL_CLRCLE: 121 MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR); 122 break; 123 case NAND_CTL_SETALE: 124 MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR); 125 break; 126 case NAND_CTL_CLRALE: 127 MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR); 128 break; 129 case NAND_CTL_SETNCE: 130 MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR); 131 break; 132 case NAND_CTL_CLRNCE: 133 MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR); 134 break; 135 } 136 } 137 if (cmd != NAND_CMD_NONE) 138 writeb(cmd, chip->IO_ADDR_W); 139} 140 141static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd, 142 unsigned int ctrl) 143{ 144 struct nand_chip *chip = mtd->priv; 145 146 if (ctrl & NAND_CTRL_CHANGE) { 147#error Missing headerfiles. No way to fix this. -tglx 148 switch (cmd) { 149 case NAND_CTL_SETCLE: 150 MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR); 151 break; 152 case NAND_CTL_CLRCLE: 153 MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR); 154 break; 155 case NAND_CTL_SETALE: 156 MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR); 157 break; 158 case NAND_CTL_CLRALE: 159 MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR); 160 break; 161 case NAND_CTL_SETNCE: 162 MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR); 163 break; 164 case NAND_CTL_CLRNCE: 165 MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR); 166 break; 167 } 168 } 169 if (cmd != NAND_CMD_NONE) 170 writeb(cmd, chip->IO_ADDR_W); 171} 172 173#ifdef USE_READY_BUSY_PIN 174/* 175 * read device ready pin 176 */ 177static int ppchameleon_device_ready(struct mtd_info *minfo) 178{ 179 if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN) 180 return 1; 181 return 0; 182} 183 184static int ppchameleonevb_device_ready(struct mtd_info *minfo) 185{ 186 if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN) 187 return 1; 188 return 0; 189} 190#endif 191 192#ifdef CONFIG_MTD_PARTITIONS 193const char *part_probes[] = { "cmdlinepart", NULL }; 194const char *part_probes_evb[] = { "cmdlinepart", NULL }; 195#endif 196 197/* 198 * Main initialization routine 199 */ 200static int __init ppchameleonevb_init(void) 201{ 202 struct nand_chip *this; 203 const char *part_type = 0; 204 int mtd_parts_nb = 0; 205 struct mtd_partition *mtd_parts = 0; 206 void __iomem *ppchameleon_fio_base; 207 void __iomem *ppchameleonevb_fio_base; 208 209 /********************************* 210 * Processor module NAND (if any) * 211 *********************************/ 212 /* Allocate memory for MTD device structure and private data */ 213 ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); 214 if (!ppchameleon_mtd) { 215 printk("Unable to allocate PPChameleon NAND MTD device structure.\n"); 216 return -ENOMEM; 217 } 218 219 /* map physical address */ 220 ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M); 221 if (!ppchameleon_fio_base) { 222 printk("ioremap PPChameleon NAND flash failed\n"); 223 kfree(ppchameleon_mtd); 224 return -EIO; 225 } 226 227 /* Get pointer to private data */ 228 this = (struct nand_chip *)(&ppchameleon_mtd[1]); 229 230 /* Initialize structures */ 231 memset(ppchameleon_mtd, 0, sizeof(struct mtd_info)); 232 memset(this, 0, sizeof(struct nand_chip)); 233 234 /* Link the private data with the MTD structure */ 235 ppchameleon_mtd->priv = this; 236 ppchameleon_mtd->owner = THIS_MODULE; 237 238 /* Initialize GPIOs */ 239 /* Pin mapping for NAND chip */ 240 /* 241 CE GPIO_01 242 CLE GPIO_02 243 ALE GPIO_03 244 R/B GPIO_04 245 */ 246 /* output select */ 247 out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xC0FFFFFF); 248 /* three-state select */ 249 out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xC0FFFFFF); 250 /* enable output driver */ 251 out_be32((volatile unsigned *)GPIO0_TCR, 252 in_be32((volatile unsigned *)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN); 253#ifdef USE_READY_BUSY_PIN 254 /* three-state select */ 255 out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFF3FFFFF); 256 /* high-impedecence */ 257 out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_RB_GPIO_PIN)); 258 /* input select */ 259 out_be32((volatile unsigned *)GPIO0_ISR1H, 260 (in_be32((volatile unsigned *)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000); 261#endif 262 263 /* insert callbacks */ 264 this->IO_ADDR_R = ppchameleon_fio_base; 265 this->IO_ADDR_W = ppchameleon_fio_base; 266 this->cmd_ctrl = ppchameleon_hwcontrol; 267#ifdef USE_READY_BUSY_PIN 268 this->dev_ready = ppchameleon_device_ready; 269#endif 270 this->chip_delay = NAND_BIG_DELAY_US; 271 /* ECC mode */ 272 this->ecc.mode = NAND_ECC_SOFT; 273 274 /* Scan to find existence of the device (it could not be mounted) */ 275 if (nand_scan(ppchameleon_mtd, 1)) { 276 iounmap((void *)ppchameleon_fio_base); 277 ppchameleon_fio_base = NULL; 278 kfree(ppchameleon_mtd); 279 goto nand_evb_init; 280 } 281#ifndef USE_READY_BUSY_PIN 282 /* Adjust delay if necessary */ 283 if (ppchameleon_mtd->size == NAND_SMALL_SIZE) 284 this->chip_delay = NAND_SMALL_DELAY_US; 285#endif 286 287#ifdef CONFIG_MTD_PARTITIONS 288 ppchameleon_mtd->name = "ppchameleon-nand"; 289 mtd_parts_nb = parse_mtd_partitions(ppchameleon_mtd, part_probes, &mtd_parts, 0); 290 if (mtd_parts_nb > 0) 291 part_type = "command line"; 292 else 293 mtd_parts_nb = 0; 294#endif 295 if (mtd_parts_nb == 0) { 296 if (ppchameleon_mtd->size == NAND_SMALL_SIZE) 297 mtd_parts = partition_info_me; 298 else 299 mtd_parts = partition_info_hi; 300 mtd_parts_nb = NUM_PARTITIONS; 301 part_type = "static"; 302 } 303 304 /* Register the partitions */ 305 printk(KERN_NOTICE "Using %s partition definition\n", part_type); 306 add_mtd_partitions(ppchameleon_mtd, mtd_parts, mtd_parts_nb); 307 308 nand_evb_init: 309 /**************************** 310 * EVB NAND (always present) * 311 ****************************/ 312 /* Allocate memory for MTD device structure and private data */ 313 ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); 314 if (!ppchameleonevb_mtd) { 315 printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n"); 316 if (ppchameleon_fio_base) 317 iounmap(ppchameleon_fio_base); 318 return -ENOMEM; 319 } 320 321 /* map physical address */ 322 ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M); 323 if (!ppchameleonevb_fio_base) { 324 printk("ioremap PPChameleonEVB NAND flash failed\n"); 325 kfree(ppchameleonevb_mtd); 326 if (ppchameleon_fio_base) 327 iounmap(ppchameleon_fio_base); 328 return -EIO; 329 } 330 331 /* Get pointer to private data */ 332 this = (struct nand_chip *)(&ppchameleonevb_mtd[1]); 333 334 /* Initialize structures */ 335 memset(ppchameleonevb_mtd, 0, sizeof(struct mtd_info)); 336 memset(this, 0, sizeof(struct nand_chip)); 337 338 /* Link the private data with the MTD structure */ 339 ppchameleonevb_mtd->priv = this; 340 341 /* Initialize GPIOs */ 342 /* Pin mapping for NAND chip */ 343 /* 344 CE GPIO_14 345 CLE GPIO_15 346 ALE GPIO_16 347 R/B GPIO_31 348 */ 349 /* output select */ 350 out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xFFFFFFF0); 351 out_be32((volatile unsigned *)GPIO0_OSRL, in_be32((volatile unsigned *)GPIO0_OSRL) & 0x3FFFFFFF); 352 /* three-state select */ 353 out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFFFFFFF0); 354 out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0x3FFFFFFF); 355 /* enable output driver */ 356 out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN | 357 NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN); 358#ifdef USE_READY_BUSY_PIN 359 /* three-state select */ 360 out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0xFFFFFFFC); 361 /* high-impedecence */ 362 out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN)); 363 /* input select */ 364 out_be32((volatile unsigned *)GPIO0_ISR1L, 365 (in_be32((volatile unsigned *)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001); 366#endif 367 368 /* insert callbacks */ 369 this->IO_ADDR_R = ppchameleonevb_fio_base; 370 this->IO_ADDR_W = ppchameleonevb_fio_base; 371 this->cmd_ctrl = ppchameleonevb_hwcontrol; 372#ifdef USE_READY_BUSY_PIN 373 this->dev_ready = ppchameleonevb_device_ready; 374#endif 375 this->chip_delay = NAND_SMALL_DELAY_US; 376 377 /* ECC mode */ 378 this->ecc.mode = NAND_ECC_SOFT; 379 380 /* Scan to find existence of the device */ 381 if (nand_scan(ppchameleonevb_mtd, 1)) { 382 iounmap((void *)ppchameleonevb_fio_base); 383 kfree(ppchameleonevb_mtd); 384 if (ppchameleon_fio_base) 385 iounmap(ppchameleon_fio_base); 386 return -ENXIO; 387 } 388#ifdef CONFIG_MTD_PARTITIONS 389 ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME; 390 mtd_parts_nb = parse_mtd_partitions(ppchameleonevb_mtd, part_probes_evb, &mtd_parts, 0); 391 if (mtd_parts_nb > 0) 392 part_type = "command line"; 393 else 394 mtd_parts_nb = 0; 395#endif 396 if (mtd_parts_nb == 0) { 397 mtd_parts = partition_info_evb; 398 mtd_parts_nb = NUM_PARTITIONS; 399 part_type = "static"; 400 } 401 402 /* Register the partitions */ 403 printk(KERN_NOTICE "Using %s partition definition\n", part_type); 404 add_mtd_partitions(ppchameleonevb_mtd, mtd_parts, mtd_parts_nb); 405 406 /* Return happy */ 407 return 0; 408} 409 410module_init(ppchameleonevb_init); 411 412/* 413 * Clean up routine 414 */ 415static void __exit ppchameleonevb_cleanup(void) 416{ 417 struct nand_chip *this; 418 419 /* Release resources, unregister device(s) */ 420 nand_release(ppchameleon_mtd); 421 nand_release(ppchameleonevb_mtd); 422 423 /* Release iomaps */ 424 this = (struct nand_chip *) &ppchameleon_mtd[1]; 425 iounmap((void *) this->IO_ADDR_R); 426 this = (struct nand_chip *) &ppchameleonevb_mtd[1]; 427 iounmap((void *) this->IO_ADDR_R); 428 429 /* Free the MTD device structure */ 430 kfree (ppchameleon_mtd); 431 kfree (ppchameleonevb_mtd); 432} 433module_exit(ppchameleonevb_cleanup); 434 435MODULE_LICENSE("GPL"); 436MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>"); 437MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board"); 438