1/* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18#include <linux/module.h> 19#include <linux/init.h> 20#include <linux/debugfs.h> 21#include <linux/seq_file.h> 22#include <linux/interrupt.h> 23#include <linux/delay.h> 24#include <linux/dma-mapping.h> 25#include <linux/platform_device.h> 26#include <linux/workqueue.h> 27#include <linux/timer.h> 28#include <linux/clk.h> 29#include <linux/mmc/host.h> 30#include <linux/mmc/core.h> 31#include <linux/mmc/mmc.h> 32#include <linux/io.h> 33#include <linux/semaphore.h> 34#include <linux/gpio.h> 35#include <linux/regulator/consumer.h> 36#include <plat/dma.h> 37#include <mach/hardware.h> 38#include <plat/board.h> 39#include <plat/mmc.h> 40#include <plat/cpu.h> 41 42/* OMAP HSMMC Host Controller Registers */ 43#define OMAP_HSMMC_SYSCONFIG 0x0010 44#define OMAP_HSMMC_SYSSTATUS 0x0014 45#define OMAP_HSMMC_CON 0x002C 46#define OMAP_HSMMC_BLK 0x0104 47#define OMAP_HSMMC_ARG 0x0108 48#define OMAP_HSMMC_CMD 0x010C 49#define OMAP_HSMMC_RSP10 0x0110 50#define OMAP_HSMMC_RSP32 0x0114 51#define OMAP_HSMMC_RSP54 0x0118 52#define OMAP_HSMMC_RSP76 0x011C 53#define OMAP_HSMMC_DATA 0x0120 54#define OMAP_HSMMC_HCTL 0x0128 55#define OMAP_HSMMC_SYSCTL 0x012C 56#define OMAP_HSMMC_STAT 0x0130 57#define OMAP_HSMMC_IE 0x0134 58#define OMAP_HSMMC_ISE 0x0138 59#define OMAP_HSMMC_CAPA 0x0140 60 61#define VS18 (1 << 26) 62#define VS30 (1 << 25) 63#define SDVS18 (0x5 << 9) 64#define SDVS30 (0x6 << 9) 65#define SDVS33 (0x7 << 9) 66#define SDVS_MASK 0x00000E00 67#define SDVSCLR 0xFFFFF1FF 68#define SDVSDET 0x00000400 69#define AUTOIDLE 0x1 70#define SDBP (1 << 8) 71#define DTO 0xe 72#define ICE 0x1 73#define ICS 0x2 74#define CEN (1 << 2) 75#define CLKD_MASK 0x0000FFC0 76#define CLKD_SHIFT 6 77#define DTO_MASK 0x000F0000 78#define DTO_SHIFT 16 79#define INT_EN_MASK 0x307F0033 80#define BWR_ENABLE (1 << 4) 81#define BRR_ENABLE (1 << 5) 82#define DTO_ENABLE (1 << 20) 83#define INIT_STREAM (1 << 1) 84#define DP_SELECT (1 << 21) 85#define DDIR (1 << 4) 86#define DMA_EN 0x1 87#define MSBS (1 << 5) 88#define BCE (1 << 1) 89#define FOUR_BIT (1 << 1) 90#define DW8 (1 << 5) 91#define CC 0x1 92#define TC 0x02 93#define OD 0x1 94#define ERR (1 << 15) 95#define CMD_TIMEOUT (1 << 16) 96#define DATA_TIMEOUT (1 << 20) 97#define CMD_CRC (1 << 17) 98#define DATA_CRC (1 << 21) 99#define CARD_ERR (1 << 28) 100#define STAT_CLEAR 0xFFFFFFFF 101#define INIT_STREAM_CMD 0x00000000 102#define DUAL_VOLT_OCR_BIT 7 103#define SRC (1 << 25) 104#define SRD (1 << 26) 105#define SOFTRESET (1 << 1) 106#define RESETDONE (1 << 0) 107 108#define OMAP_MMC1_DEVID 0 109#define OMAP_MMC2_DEVID 1 110#define OMAP_MMC3_DEVID 2 111#define OMAP_MMC4_DEVID 3 112#define OMAP_MMC5_DEVID 4 113 114#define MMC_TIMEOUT_MS 20 115#define OMAP_MMC_MASTER_CLOCK 96000000 116#define DRIVER_NAME "mmci-omap-hs" 117 118/* Timeouts for entering power saving states on inactivity, msec */ 119#define OMAP_MMC_DISABLED_TIMEOUT 100 120#define OMAP_MMC_SLEEP_TIMEOUT 1000 121#define OMAP_MMC_OFF_TIMEOUT 8000 122 123/* 124 * One controller can have multiple slots, like on some omap boards using 125 * omap.c controller driver. Luckily this is not currently done on any known 126 * omap_hsmmc.c device. 127 */ 128#define mmc_slot(host) (host->pdata->slots[host->slot_id]) 129 130/* 131 * MMC Host controller read/write API's 132 */ 133#define OMAP_HSMMC_READ(base, reg) \ 134 __raw_readl((base) + OMAP_HSMMC_##reg) 135 136#define OMAP_HSMMC_WRITE(base, reg, val) \ 137 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 138 139struct omap_hsmmc_host { 140 struct device *dev; 141 struct mmc_host *mmc; 142 struct mmc_request *mrq; 143 struct mmc_command *cmd; 144 struct mmc_data *data; 145 struct clk *fclk; 146 struct clk *iclk; 147 struct clk *dbclk; 148 /* 149 * vcc == configured supply 150 * vcc_aux == optional 151 * - MMC1, supply for DAT4..DAT7 152 * - MMC2/MMC2, external level shifter voltage supply, for 153 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 154 */ 155 struct regulator *vcc; 156 struct regulator *vcc_aux; 157 struct work_struct mmc_carddetect_work; 158 void __iomem *base; 159 resource_size_t mapbase; 160 spinlock_t irq_lock; /* Prevent races with irq handler */ 161 unsigned int id; 162 unsigned int dma_len; 163 unsigned int dma_sg_idx; 164 unsigned char bus_mode; 165 unsigned char power_mode; 166 u32 *buffer; 167 u32 bytesleft; 168 int suspended; 169 int irq; 170 int use_dma, dma_ch; 171 int dma_line_tx, dma_line_rx; 172 int slot_id; 173 int got_dbclk; 174 int response_busy; 175 int context_loss; 176 int dpm_state; 177 int vdd; 178 int protect_card; 179 int reqs_blocked; 180 int use_reg; 181 int req_in_progress; 182 183 struct omap_mmc_platform_data *pdata; 184}; 185 186static int omap_hsmmc_card_detect(struct device *dev, int slot) 187{ 188 struct omap_mmc_platform_data *mmc = dev->platform_data; 189 190 /* NOTE: assumes card detect signal is active-low */ 191 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 192} 193 194static int omap_hsmmc_get_wp(struct device *dev, int slot) 195{ 196 struct omap_mmc_platform_data *mmc = dev->platform_data; 197 198 /* NOTE: assumes write protect signal is active-high */ 199 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 200} 201 202static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 203{ 204 struct omap_mmc_platform_data *mmc = dev->platform_data; 205 206 /* NOTE: assumes card detect signal is active-low */ 207 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 208} 209 210#ifdef CONFIG_PM 211 212static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 213{ 214 struct omap_mmc_platform_data *mmc = dev->platform_data; 215 216 disable_irq(mmc->slots[0].card_detect_irq); 217 return 0; 218} 219 220static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 221{ 222 struct omap_mmc_platform_data *mmc = dev->platform_data; 223 224 enable_irq(mmc->slots[0].card_detect_irq); 225 return 0; 226} 227 228#else 229 230#define omap_hsmmc_suspend_cdirq NULL 231#define omap_hsmmc_resume_cdirq NULL 232 233#endif 234 235#ifdef CONFIG_REGULATOR 236 237static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, 238 int vdd) 239{ 240 struct omap_hsmmc_host *host = 241 platform_get_drvdata(to_platform_device(dev)); 242 int ret; 243 244 if (mmc_slot(host).before_set_reg) 245 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 246 247 if (power_on) 248 ret = mmc_regulator_set_ocr(host->vcc, vdd); 249 else 250 ret = mmc_regulator_set_ocr(host->vcc, 0); 251 252 if (mmc_slot(host).after_set_reg) 253 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 254 255 return ret; 256} 257 258static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, 259 int vdd) 260{ 261 struct omap_hsmmc_host *host = 262 platform_get_drvdata(to_platform_device(dev)); 263 int ret = 0; 264 265 /* 266 * If we don't see a Vcc regulator, assume it's a fixed 267 * voltage always-on regulator. 268 */ 269 if (!host->vcc) 270 return 0; 271 272 if (mmc_slot(host).before_set_reg) 273 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 274 275 /* 276 * Assume Vcc regulator is used only to power the card ... OMAP 277 * VDDS is used to power the pins, optionally with a transceiver to 278 * support cards using voltages other than VDDS (1.8V nominal). When a 279 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 280 * 281 * In some cases this regulator won't support enable/disable; 282 * e.g. it's a fixed rail for a WLAN chip. 283 * 284 * In other cases vcc_aux switches interface power. Example, for 285 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 286 * chips/cards need an interface voltage rail too. 287 */ 288 if (power_on) { 289 ret = mmc_regulator_set_ocr(host->vcc, vdd); 290 /* Enable interface voltage rail, if needed */ 291 if (ret == 0 && host->vcc_aux) { 292 ret = regulator_enable(host->vcc_aux); 293 if (ret < 0) 294 ret = mmc_regulator_set_ocr(host->vcc, 0); 295 } 296 } else { 297 if (host->vcc_aux) 298 ret = regulator_disable(host->vcc_aux); 299 if (ret == 0) 300 ret = mmc_regulator_set_ocr(host->vcc, 0); 301 } 302 303 if (mmc_slot(host).after_set_reg) 304 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 305 306 return ret; 307} 308 309static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, 310 int vdd, int cardsleep) 311{ 312 struct omap_hsmmc_host *host = 313 platform_get_drvdata(to_platform_device(dev)); 314 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 315 316 return regulator_set_mode(host->vcc, mode); 317} 318 319static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, 320 int vdd, int cardsleep) 321{ 322 struct omap_hsmmc_host *host = 323 platform_get_drvdata(to_platform_device(dev)); 324 int err, mode; 325 326 /* 327 * If we don't see a Vcc regulator, assume it's a fixed 328 * voltage always-on regulator. 329 */ 330 if (!host->vcc) 331 return 0; 332 333 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 334 335 if (!host->vcc_aux) 336 return regulator_set_mode(host->vcc, mode); 337 338 if (cardsleep) { 339 /* VCC can be turned off if card is asleep */ 340 if (sleep) 341 err = mmc_regulator_set_ocr(host->vcc, 0); 342 else 343 err = mmc_regulator_set_ocr(host->vcc, vdd); 344 } else 345 err = regulator_set_mode(host->vcc, mode); 346 if (err) 347 return err; 348 349 if (!mmc_slot(host).vcc_aux_disable_is_sleep) 350 return regulator_set_mode(host->vcc_aux, mode); 351 352 if (sleep) 353 return regulator_disable(host->vcc_aux); 354 else 355 return regulator_enable(host->vcc_aux); 356} 357 358static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 359{ 360 struct regulator *reg; 361 int ret = 0; 362 363 switch (host->id) { 364 case OMAP_MMC1_DEVID: 365 /* On-chip level shifting via PBIAS0/PBIAS1 */ 366 mmc_slot(host).set_power = omap_hsmmc_1_set_power; 367 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; 368 break; 369 case OMAP_MMC2_DEVID: 370 case OMAP_MMC3_DEVID: 371 /* Off-chip level shifting, or none */ 372 mmc_slot(host).set_power = omap_hsmmc_23_set_power; 373 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; 374 break; 375 default: 376 pr_err("MMC%d configuration not supported!\n", host->id); 377 return -EINVAL; 378 } 379 380 reg = regulator_get(host->dev, "vmmc"); 381 if (IS_ERR(reg)) { 382 dev_dbg(host->dev, "vmmc regulator missing\n"); 383 /* 384 * HACK: until fixed.c regulator is usable, 385 * we don't require a main regulator 386 * for MMC2 or MMC3 387 */ 388 if (host->id == OMAP_MMC1_DEVID) { 389 ret = PTR_ERR(reg); 390 goto err; 391 } 392 } else { 393 host->vcc = reg; 394 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); 395 396 /* Allow an aux regulator */ 397 reg = regulator_get(host->dev, "vmmc_aux"); 398 host->vcc_aux = IS_ERR(reg) ? NULL : reg; 399 400 if (regulator_is_enabled(host->vcc) > 0) { 401 regulator_enable(host->vcc); 402 regulator_disable(host->vcc); 403 } 404 if (host->vcc_aux) { 405 if (regulator_is_enabled(reg) > 0) { 406 regulator_enable(reg); 407 regulator_disable(reg); 408 } 409 } 410 } 411 412 return 0; 413 414err: 415 mmc_slot(host).set_power = NULL; 416 mmc_slot(host).set_sleep = NULL; 417 return ret; 418} 419 420static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 421{ 422 regulator_put(host->vcc); 423 regulator_put(host->vcc_aux); 424 mmc_slot(host).set_power = NULL; 425 mmc_slot(host).set_sleep = NULL; 426} 427 428static inline int omap_hsmmc_have_reg(void) 429{ 430 return 1; 431} 432 433#else 434 435static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 436{ 437 return -EINVAL; 438} 439 440static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 441{ 442} 443 444static inline int omap_hsmmc_have_reg(void) 445{ 446 return 0; 447} 448 449#endif 450 451static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 452{ 453 int ret; 454 455 if (gpio_is_valid(pdata->slots[0].switch_pin)) { 456 pdata->suspend = omap_hsmmc_suspend_cdirq; 457 pdata->resume = omap_hsmmc_resume_cdirq; 458 if (pdata->slots[0].cover) 459 pdata->slots[0].get_cover_state = 460 omap_hsmmc_get_cover_state; 461 else 462 pdata->slots[0].card_detect = omap_hsmmc_card_detect; 463 pdata->slots[0].card_detect_irq = 464 gpio_to_irq(pdata->slots[0].switch_pin); 465 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 466 if (ret) 467 return ret; 468 ret = gpio_direction_input(pdata->slots[0].switch_pin); 469 if (ret) 470 goto err_free_sp; 471 } else 472 pdata->slots[0].switch_pin = -EINVAL; 473 474 if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 475 pdata->slots[0].get_ro = omap_hsmmc_get_wp; 476 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 477 if (ret) 478 goto err_free_cd; 479 ret = gpio_direction_input(pdata->slots[0].gpio_wp); 480 if (ret) 481 goto err_free_wp; 482 } else 483 pdata->slots[0].gpio_wp = -EINVAL; 484 485 return 0; 486 487err_free_wp: 488 gpio_free(pdata->slots[0].gpio_wp); 489err_free_cd: 490 if (gpio_is_valid(pdata->slots[0].switch_pin)) 491err_free_sp: 492 gpio_free(pdata->slots[0].switch_pin); 493 return ret; 494} 495 496static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 497{ 498 if (gpio_is_valid(pdata->slots[0].gpio_wp)) 499 gpio_free(pdata->slots[0].gpio_wp); 500 if (gpio_is_valid(pdata->slots[0].switch_pin)) 501 gpio_free(pdata->slots[0].switch_pin); 502} 503 504/* 505 * Stop clock to the card 506 */ 507static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 508{ 509 OMAP_HSMMC_WRITE(host->base, SYSCTL, 510 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 511 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 512 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 513} 514 515static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 516 struct mmc_command *cmd) 517{ 518 unsigned int irq_mask; 519 520 if (host->use_dma) 521 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 522 else 523 irq_mask = INT_EN_MASK; 524 525 /* Disable timeout for erases */ 526 if (cmd->opcode == MMC_ERASE) 527 irq_mask &= ~DTO_ENABLE; 528 529 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 530 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 531 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 532} 533 534static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 535{ 536 OMAP_HSMMC_WRITE(host->base, ISE, 0); 537 OMAP_HSMMC_WRITE(host->base, IE, 0); 538 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 539} 540 541#ifdef CONFIG_PM 542 543/* 544 * Restore the MMC host context, if it was lost as result of a 545 * power state change. 546 */ 547static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 548{ 549 struct mmc_ios *ios = &host->mmc->ios; 550 struct omap_mmc_platform_data *pdata = host->pdata; 551 int context_loss = 0; 552 u32 hctl, capa, con; 553 u16 dsor = 0; 554 unsigned long timeout; 555 556 if (pdata->get_context_loss_count) { 557 context_loss = pdata->get_context_loss_count(host->dev); 558 if (context_loss < 0) 559 return 1; 560 } 561 562 dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 563 context_loss == host->context_loss ? "not " : ""); 564 if (host->context_loss == context_loss) 565 return 1; 566 567 /* Wait for hardware reset */ 568 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 569 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 570 && time_before(jiffies, timeout)) 571 ; 572 573 /* Do software reset */ 574 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 575 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 576 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 577 && time_before(jiffies, timeout)) 578 ; 579 580 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 581 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 582 583 if (host->id == OMAP_MMC1_DEVID) { 584 if (host->power_mode != MMC_POWER_OFF && 585 (1 << ios->vdd) <= MMC_VDD_23_24) 586 hctl = SDVS18; 587 else 588 hctl = SDVS30; 589 capa = VS30 | VS18; 590 } else { 591 hctl = SDVS18; 592 capa = VS18; 593 } 594 595 OMAP_HSMMC_WRITE(host->base, HCTL, 596 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 597 598 OMAP_HSMMC_WRITE(host->base, CAPA, 599 OMAP_HSMMC_READ(host->base, CAPA) | capa); 600 601 OMAP_HSMMC_WRITE(host->base, HCTL, 602 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 603 604 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 605 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 606 && time_before(jiffies, timeout)) 607 ; 608 609 omap_hsmmc_disable_irq(host); 610 611 /* Do not initialize card-specific things if the power is off */ 612 if (host->power_mode == MMC_POWER_OFF) 613 goto out; 614 615 con = OMAP_HSMMC_READ(host->base, CON); 616 switch (ios->bus_width) { 617 case MMC_BUS_WIDTH_8: 618 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 619 break; 620 case MMC_BUS_WIDTH_4: 621 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 622 OMAP_HSMMC_WRITE(host->base, HCTL, 623 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 624 break; 625 case MMC_BUS_WIDTH_1: 626 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 627 OMAP_HSMMC_WRITE(host->base, HCTL, 628 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 629 break; 630 } 631 632 if (ios->clock) { 633 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 634 if (dsor < 1) 635 dsor = 1; 636 637 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 638 dsor++; 639 640 if (dsor > 250) 641 dsor = 250; 642 } 643 644 OMAP_HSMMC_WRITE(host->base, SYSCTL, 645 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 646 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); 647 OMAP_HSMMC_WRITE(host->base, SYSCTL, 648 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 649 650 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 651 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 652 && time_before(jiffies, timeout)) 653 ; 654 655 OMAP_HSMMC_WRITE(host->base, SYSCTL, 656 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 657 658 con = OMAP_HSMMC_READ(host->base, CON); 659 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 660 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 661 else 662 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 663out: 664 host->context_loss = context_loss; 665 666 dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 667 return 0; 668} 669 670/* 671 * Save the MMC host context (store the number of power state changes so far). 672 */ 673static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 674{ 675 struct omap_mmc_platform_data *pdata = host->pdata; 676 int context_loss; 677 678 if (pdata->get_context_loss_count) { 679 context_loss = pdata->get_context_loss_count(host->dev); 680 if (context_loss < 0) 681 return; 682 host->context_loss = context_loss; 683 } 684} 685 686#else 687 688static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 689{ 690 return 0; 691} 692 693static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 694{ 695} 696 697#endif 698 699/* 700 * Send init stream sequence to card 701 * before sending IDLE command 702 */ 703static void send_init_stream(struct omap_hsmmc_host *host) 704{ 705 int reg = 0; 706 unsigned long timeout; 707 708 if (host->protect_card) 709 return; 710 711 disable_irq(host->irq); 712 713 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 714 OMAP_HSMMC_WRITE(host->base, CON, 715 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 716 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 717 718 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 719 while ((reg != CC) && time_before(jiffies, timeout)) 720 reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 721 722 OMAP_HSMMC_WRITE(host->base, CON, 723 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 724 725 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 726 OMAP_HSMMC_READ(host->base, STAT); 727 728 enable_irq(host->irq); 729} 730 731static inline 732int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 733{ 734 int r = 1; 735 736 if (mmc_slot(host).get_cover_state) 737 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 738 return r; 739} 740 741static ssize_t 742omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 743 char *buf) 744{ 745 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 746 struct omap_hsmmc_host *host = mmc_priv(mmc); 747 748 return sprintf(buf, "%s\n", 749 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 750} 751 752static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 753 754static ssize_t 755omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 756 char *buf) 757{ 758 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 759 struct omap_hsmmc_host *host = mmc_priv(mmc); 760 761 return sprintf(buf, "%s\n", mmc_slot(host).name); 762} 763 764static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 765 766/* 767 * Configure the response type and send the cmd. 768 */ 769static void 770omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 771 struct mmc_data *data) 772{ 773 int cmdreg = 0, resptype = 0, cmdtype = 0; 774 775 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 776 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 777 host->cmd = cmd; 778 779 omap_hsmmc_enable_irq(host, cmd); 780 781 host->response_busy = 0; 782 if (cmd->flags & MMC_RSP_PRESENT) { 783 if (cmd->flags & MMC_RSP_136) 784 resptype = 1; 785 else if (cmd->flags & MMC_RSP_BUSY) { 786 resptype = 3; 787 host->response_busy = 1; 788 } else 789 resptype = 2; 790 } 791 792 /* 793 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 794 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 795 * a val of 0x3, rest 0x0. 796 */ 797 if (cmd == host->mrq->stop) 798 cmdtype = 0x3; 799 800 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 801 802 if (data) { 803 cmdreg |= DP_SELECT | MSBS | BCE; 804 if (data->flags & MMC_DATA_READ) 805 cmdreg |= DDIR; 806 else 807 cmdreg &= ~(DDIR); 808 } 809 810 if (host->use_dma) 811 cmdreg |= DMA_EN; 812 813 host->req_in_progress = 1; 814 815 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 816 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 817} 818 819static int 820omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 821{ 822 if (data->flags & MMC_DATA_WRITE) 823 return DMA_TO_DEVICE; 824 else 825 return DMA_FROM_DEVICE; 826} 827 828static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 829{ 830 int dma_ch; 831 832 spin_lock(&host->irq_lock); 833 host->req_in_progress = 0; 834 dma_ch = host->dma_ch; 835 spin_unlock(&host->irq_lock); 836 837 omap_hsmmc_disable_irq(host); 838 /* Do not complete the request if DMA is still in progress */ 839 if (mrq->data && host->use_dma && dma_ch != -1) 840 return; 841 host->mrq = NULL; 842 mmc_request_done(host->mmc, mrq); 843} 844 845/* 846 * Notify the transfer complete to MMC core 847 */ 848static void 849omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 850{ 851 if (!data) { 852 struct mmc_request *mrq = host->mrq; 853 854 /* TC before CC from CMD6 - don't know why, but it happens */ 855 if (host->cmd && host->cmd->opcode == 6 && 856 host->response_busy) { 857 host->response_busy = 0; 858 return; 859 } 860 861 omap_hsmmc_request_done(host, mrq); 862 return; 863 } 864 865 host->data = NULL; 866 867 if (!data->error) 868 data->bytes_xfered += data->blocks * (data->blksz); 869 else 870 data->bytes_xfered = 0; 871 872 if (!data->stop) { 873 omap_hsmmc_request_done(host, data->mrq); 874 return; 875 } 876 omap_hsmmc_start_command(host, data->stop, NULL); 877} 878 879/* 880 * Notify the core about command completion 881 */ 882static void 883omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 884{ 885 host->cmd = NULL; 886 887 if (cmd->flags & MMC_RSP_PRESENT) { 888 if (cmd->flags & MMC_RSP_136) { 889 /* response type 2 */ 890 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 891 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 892 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 893 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 894 } else { 895 /* response types 1, 1b, 3, 4, 5, 6 */ 896 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 897 } 898 } 899 if ((host->data == NULL && !host->response_busy) || cmd->error) 900 omap_hsmmc_request_done(host, cmd->mrq); 901} 902 903/* 904 * DMA clean up for command errors 905 */ 906static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 907{ 908 int dma_ch; 909 910 host->data->error = errno; 911 912 spin_lock(&host->irq_lock); 913 dma_ch = host->dma_ch; 914 host->dma_ch = -1; 915 spin_unlock(&host->irq_lock); 916 917 if (host->use_dma && dma_ch != -1) { 918 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, 919 omap_hsmmc_get_dma_dir(host, host->data)); 920 omap_free_dma(dma_ch); 921 } 922 host->data = NULL; 923} 924 925/* 926 * Readable error output 927 */ 928#ifdef CONFIG_MMC_DEBUG 929static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) 930{ 931 /* --- means reserved bit without definition at documentation */ 932 static const char *omap_hsmmc_status_bits[] = { 933 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", 934 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", 935 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", 936 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" 937 }; 938 char res[256]; 939 char *buf = res; 940 int len, i; 941 942 len = sprintf(buf, "MMC IRQ 0x%x :", status); 943 buf += len; 944 945 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 946 if (status & (1 << i)) { 947 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 948 buf += len; 949 } 950 951 dev_dbg(mmc_dev(host->mmc), "%s\n", res); 952} 953#endif /* CONFIG_MMC_DEBUG */ 954 955/* 956 * MMC controller internal state machines reset 957 * 958 * Used to reset command or data internal state machines, using respectively 959 * SRC or SRD bit of SYSCTL register 960 * Can be called from interrupt context 961 */ 962static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 963 unsigned long bit) 964{ 965 unsigned long i = 0; 966 unsigned long limit = (loops_per_jiffy * 967 msecs_to_jiffies(MMC_TIMEOUT_MS)); 968 969 OMAP_HSMMC_WRITE(host->base, SYSCTL, 970 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 971 972 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 973 (i++ < limit)) 974 cpu_relax(); 975 976 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 977 dev_err(mmc_dev(host->mmc), 978 "Timeout waiting on controller reset in %s\n", 979 __func__); 980} 981 982static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 983{ 984 struct mmc_data *data; 985 int end_cmd = 0, end_trans = 0; 986 987 if (!host->req_in_progress) { 988 do { 989 OMAP_HSMMC_WRITE(host->base, STAT, status); 990 /* Flush posted write */ 991 status = OMAP_HSMMC_READ(host->base, STAT); 992 } while (status & INT_EN_MASK); 993 return; 994 } 995 996 data = host->data; 997 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 998 999 if (status & ERR) { 1000#ifdef CONFIG_MMC_DEBUG 1001 omap_hsmmc_report_irq(host, status); 1002#endif 1003 if ((status & CMD_TIMEOUT) || 1004 (status & CMD_CRC)) { 1005 if (host->cmd) { 1006 if (status & CMD_TIMEOUT) { 1007 omap_hsmmc_reset_controller_fsm(host, 1008 SRC); 1009 host->cmd->error = -ETIMEDOUT; 1010 } else { 1011 host->cmd->error = -EILSEQ; 1012 } 1013 end_cmd = 1; 1014 } 1015 if (host->data || host->response_busy) { 1016 if (host->data) 1017 omap_hsmmc_dma_cleanup(host, 1018 -ETIMEDOUT); 1019 host->response_busy = 0; 1020 omap_hsmmc_reset_controller_fsm(host, SRD); 1021 } 1022 } 1023 if ((status & DATA_TIMEOUT) || 1024 (status & DATA_CRC)) { 1025 if (host->data || host->response_busy) { 1026 int err = (status & DATA_TIMEOUT) ? 1027 -ETIMEDOUT : -EILSEQ; 1028 1029 if (host->data) 1030 omap_hsmmc_dma_cleanup(host, err); 1031 else 1032 host->mrq->cmd->error = err; 1033 host->response_busy = 0; 1034 omap_hsmmc_reset_controller_fsm(host, SRD); 1035 end_trans = 1; 1036 } 1037 } 1038 if (status & CARD_ERR) { 1039 dev_dbg(mmc_dev(host->mmc), 1040 "Ignoring card err CMD%d\n", host->cmd->opcode); 1041 if (host->cmd) 1042 end_cmd = 1; 1043 if (host->data) 1044 end_trans = 1; 1045 } 1046 } 1047 1048 OMAP_HSMMC_WRITE(host->base, STAT, status); 1049 1050 if (end_cmd || ((status & CC) && host->cmd)) 1051 omap_hsmmc_cmd_done(host, host->cmd); 1052 if ((end_trans || (status & TC)) && host->mrq) 1053 omap_hsmmc_xfer_done(host, data); 1054} 1055 1056/* 1057 * MMC controller IRQ handler 1058 */ 1059static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1060{ 1061 struct omap_hsmmc_host *host = dev_id; 1062 int status; 1063 1064 status = OMAP_HSMMC_READ(host->base, STAT); 1065 do { 1066 omap_hsmmc_do_irq(host, status); 1067 /* Flush posted write */ 1068 status = OMAP_HSMMC_READ(host->base, STAT); 1069 } while (status & INT_EN_MASK); 1070 1071 return IRQ_HANDLED; 1072} 1073 1074static void set_sd_bus_power(struct omap_hsmmc_host *host) 1075{ 1076 unsigned long i; 1077 1078 OMAP_HSMMC_WRITE(host->base, HCTL, 1079 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1080 for (i = 0; i < loops_per_jiffy; i++) { 1081 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1082 break; 1083 cpu_relax(); 1084 } 1085} 1086 1087/* 1088 * Switch MMC interface voltage ... only relevant for MMC1. 1089 * 1090 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1091 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1092 * Some chips, like eMMC ones, use internal transceivers. 1093 */ 1094static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1095{ 1096 u32 reg_val = 0; 1097 int ret; 1098 1099 /* Disable the clocks */ 1100 clk_disable(host->fclk); 1101 clk_disable(host->iclk); 1102 if (host->got_dbclk) 1103 clk_disable(host->dbclk); 1104 1105 /* Turn the power off */ 1106 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1107 1108 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1109 if (!ret) 1110 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 1111 vdd); 1112 clk_enable(host->iclk); 1113 clk_enable(host->fclk); 1114 if (host->got_dbclk) 1115 clk_enable(host->dbclk); 1116 1117 if (ret != 0) 1118 goto err; 1119 1120 OMAP_HSMMC_WRITE(host->base, HCTL, 1121 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1122 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1123 1124 /* 1125 * If a MMC dual voltage card is detected, the set_ios fn calls 1126 * this fn with VDD bit set for 1.8V. Upon card removal from the 1127 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1128 * 1129 * Cope with a bit of slop in the range ... per data sheets: 1130 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1131 * but recommended values are 1.71V to 1.89V 1132 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1133 * but recommended values are 2.7V to 3.3V 1134 * 1135 * Board setup code shouldn't permit anything very out-of-range. 1136 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1137 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1138 */ 1139 if ((1 << vdd) <= MMC_VDD_23_24) 1140 reg_val |= SDVS18; 1141 else 1142 reg_val |= SDVS30; 1143 1144 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1145 set_sd_bus_power(host); 1146 1147 return 0; 1148err: 1149 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1150 return ret; 1151} 1152 1153/* Protect the card while the cover is open */ 1154static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1155{ 1156 if (!mmc_slot(host).get_cover_state) 1157 return; 1158 1159 host->reqs_blocked = 0; 1160 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1161 if (host->protect_card) { 1162 printk(KERN_INFO "%s: cover is closed, " 1163 "card is now accessible\n", 1164 mmc_hostname(host->mmc)); 1165 host->protect_card = 0; 1166 } 1167 } else { 1168 if (!host->protect_card) { 1169 printk(KERN_INFO "%s: cover is open, " 1170 "card is now inaccessible\n", 1171 mmc_hostname(host->mmc)); 1172 host->protect_card = 1; 1173 } 1174 } 1175} 1176 1177/* 1178 * Work Item to notify the core about card insertion/removal 1179 */ 1180static void omap_hsmmc_detect(struct work_struct *work) 1181{ 1182 struct omap_hsmmc_host *host = 1183 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); 1184 struct omap_mmc_slot_data *slot = &mmc_slot(host); 1185 int carddetect; 1186 1187 if (host->suspended) 1188 return; 1189 1190 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1191 1192 if (slot->card_detect) 1193 carddetect = slot->card_detect(host->dev, host->slot_id); 1194 else { 1195 omap_hsmmc_protect_card(host); 1196 carddetect = -ENOSYS; 1197 } 1198 1199 if (carddetect) 1200 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1201 else 1202 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1203} 1204 1205/* 1206 * ISR for handling card insertion and removal 1207 */ 1208static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) 1209{ 1210 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; 1211 1212 if (host->suspended) 1213 return IRQ_HANDLED; 1214 schedule_work(&host->mmc_carddetect_work); 1215 1216 return IRQ_HANDLED; 1217} 1218 1219static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 1220 struct mmc_data *data) 1221{ 1222 int sync_dev; 1223 1224 if (data->flags & MMC_DATA_WRITE) 1225 sync_dev = host->dma_line_tx; 1226 else 1227 sync_dev = host->dma_line_rx; 1228 return sync_dev; 1229} 1230 1231static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 1232 struct mmc_data *data, 1233 struct scatterlist *sgl) 1234{ 1235 int blksz, nblk, dma_ch; 1236 1237 dma_ch = host->dma_ch; 1238 if (data->flags & MMC_DATA_WRITE) { 1239 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1240 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1241 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1242 sg_dma_address(sgl), 0, 0); 1243 } else { 1244 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1245 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1246 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1247 sg_dma_address(sgl), 0, 0); 1248 } 1249 1250 blksz = host->data->blksz; 1251 nblk = sg_dma_len(sgl) / blksz; 1252 1253 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 1254 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 1255 omap_hsmmc_get_dma_sync_dev(host, data), 1256 !(data->flags & MMC_DATA_WRITE)); 1257 1258 omap_start_dma(dma_ch); 1259} 1260 1261/* 1262 * DMA call back function 1263 */ 1264static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1265{ 1266 struct omap_hsmmc_host *host = cb_data; 1267 struct mmc_data *data = host->mrq->data; 1268 int dma_ch, req_in_progress; 1269 1270 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 1271 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", 1272 ch_status); 1273 return; 1274 } 1275 1276 spin_lock(&host->irq_lock); 1277 if (host->dma_ch < 0) { 1278 spin_unlock(&host->irq_lock); 1279 return; 1280 } 1281 1282 host->dma_sg_idx++; 1283 if (host->dma_sg_idx < host->dma_len) { 1284 /* Fire up the next transfer. */ 1285 omap_hsmmc_config_dma_params(host, data, 1286 data->sg + host->dma_sg_idx); 1287 spin_unlock(&host->irq_lock); 1288 return; 1289 } 1290 1291 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, 1292 omap_hsmmc_get_dma_dir(host, data)); 1293 1294 req_in_progress = host->req_in_progress; 1295 dma_ch = host->dma_ch; 1296 host->dma_ch = -1; 1297 spin_unlock(&host->irq_lock); 1298 1299 omap_free_dma(dma_ch); 1300 1301 /* If DMA has finished after TC, complete the request */ 1302 if (!req_in_progress) { 1303 struct mmc_request *mrq = host->mrq; 1304 1305 host->mrq = NULL; 1306 mmc_request_done(host->mmc, mrq); 1307 } 1308} 1309 1310/* 1311 * Routine to configure and start DMA for the MMC card 1312 */ 1313static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 1314 struct mmc_request *req) 1315{ 1316 int dma_ch = 0, ret = 0, i; 1317 struct mmc_data *data = req->data; 1318 1319 /* Sanity check: all the SG entries must be aligned by block size. */ 1320 for (i = 0; i < data->sg_len; i++) { 1321 struct scatterlist *sgl; 1322 1323 sgl = data->sg + i; 1324 if (sgl->length % data->blksz) 1325 return -EINVAL; 1326 } 1327 if ((data->blksz % 4) != 0) 1328 /* REVISIT: The MMC buffer increments only when MSB is written. 1329 * Return error for blksz which is non multiple of four. 1330 */ 1331 return -EINVAL; 1332 1333 BUG_ON(host->dma_ch != -1); 1334 1335 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 1336 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1337 if (ret != 0) { 1338 dev_err(mmc_dev(host->mmc), 1339 "%s: omap_request_dma() failed with %d\n", 1340 mmc_hostname(host->mmc), ret); 1341 return ret; 1342 } 1343 1344 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 1345 data->sg_len, omap_hsmmc_get_dma_dir(host, data)); 1346 host->dma_ch = dma_ch; 1347 host->dma_sg_idx = 0; 1348 1349 omap_hsmmc_config_dma_params(host, data, data->sg); 1350 1351 return 0; 1352} 1353 1354static void set_data_timeout(struct omap_hsmmc_host *host, 1355 unsigned int timeout_ns, 1356 unsigned int timeout_clks) 1357{ 1358 unsigned int timeout, cycle_ns; 1359 uint32_t reg, clkd, dto = 0; 1360 1361 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1362 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1363 if (clkd == 0) 1364 clkd = 1; 1365 1366 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1367 timeout = timeout_ns / cycle_ns; 1368 timeout += timeout_clks; 1369 if (timeout) { 1370 while ((timeout & 0x80000000) == 0) { 1371 dto += 1; 1372 timeout <<= 1; 1373 } 1374 dto = 31 - dto; 1375 timeout <<= 1; 1376 if (timeout && dto) 1377 dto += 1; 1378 if (dto >= 13) 1379 dto -= 13; 1380 else 1381 dto = 0; 1382 if (dto > 14) 1383 dto = 14; 1384 } 1385 1386 reg &= ~DTO_MASK; 1387 reg |= dto << DTO_SHIFT; 1388 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1389} 1390 1391/* 1392 * Configure block length for MMC/SD cards and initiate the transfer. 1393 */ 1394static int 1395omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1396{ 1397 int ret; 1398 host->data = req->data; 1399 1400 if (req->data == NULL) { 1401 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1402 /* 1403 * Set an arbitrary 100ms data timeout for commands with 1404 * busy signal. 1405 */ 1406 if (req->cmd->flags & MMC_RSP_BUSY) 1407 set_data_timeout(host, 100000000U, 0); 1408 return 0; 1409 } 1410 1411 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1412 | (req->data->blocks << 16)); 1413 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1414 1415 if (host->use_dma) { 1416 ret = omap_hsmmc_start_dma_transfer(host, req); 1417 if (ret != 0) { 1418 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1419 return ret; 1420 } 1421 } 1422 return 0; 1423} 1424 1425/* 1426 * Request function. for read/write operation 1427 */ 1428static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1429{ 1430 struct omap_hsmmc_host *host = mmc_priv(mmc); 1431 int err; 1432 1433 BUG_ON(host->req_in_progress); 1434 BUG_ON(host->dma_ch != -1); 1435 if (host->protect_card) { 1436 if (host->reqs_blocked < 3) { 1437 /* 1438 * Ensure the controller is left in a consistent 1439 * state by resetting the command and data state 1440 * machines. 1441 */ 1442 omap_hsmmc_reset_controller_fsm(host, SRD); 1443 omap_hsmmc_reset_controller_fsm(host, SRC); 1444 host->reqs_blocked += 1; 1445 } 1446 req->cmd->error = -EBADF; 1447 if (req->data) 1448 req->data->error = -EBADF; 1449 req->cmd->retries = 0; 1450 mmc_request_done(mmc, req); 1451 return; 1452 } else if (host->reqs_blocked) 1453 host->reqs_blocked = 0; 1454 WARN_ON(host->mrq != NULL); 1455 host->mrq = req; 1456 err = omap_hsmmc_prepare_data(host, req); 1457 if (err) { 1458 req->cmd->error = err; 1459 if (req->data) 1460 req->data->error = err; 1461 host->mrq = NULL; 1462 mmc_request_done(mmc, req); 1463 return; 1464 } 1465 1466 omap_hsmmc_start_command(host, req->cmd, req->data); 1467} 1468 1469/* Routine to configure clock values. Exposed API to core */ 1470static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1471{ 1472 struct omap_hsmmc_host *host = mmc_priv(mmc); 1473 u16 dsor = 0; 1474 unsigned long regval; 1475 unsigned long timeout; 1476 u32 con; 1477 int do_send_init_stream = 0; 1478 1479 mmc_host_enable(host->mmc); 1480 1481 if (ios->power_mode != host->power_mode) { 1482 switch (ios->power_mode) { 1483 case MMC_POWER_OFF: 1484 mmc_slot(host).set_power(host->dev, host->slot_id, 1485 0, 0); 1486 host->vdd = 0; 1487 break; 1488 case MMC_POWER_UP: 1489 mmc_slot(host).set_power(host->dev, host->slot_id, 1490 1, ios->vdd); 1491 host->vdd = ios->vdd; 1492 break; 1493 case MMC_POWER_ON: 1494 do_send_init_stream = 1; 1495 break; 1496 } 1497 host->power_mode = ios->power_mode; 1498 } 1499 1500 1501 con = OMAP_HSMMC_READ(host->base, CON); 1502 switch (mmc->ios.bus_width) { 1503 case MMC_BUS_WIDTH_8: 1504 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 1505 break; 1506 case MMC_BUS_WIDTH_4: 1507 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1508 OMAP_HSMMC_WRITE(host->base, HCTL, 1509 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 1510 break; 1511 case MMC_BUS_WIDTH_1: 1512 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1513 OMAP_HSMMC_WRITE(host->base, HCTL, 1514 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 1515 break; 1516 } 1517 1518 if (host->id == OMAP_MMC1_DEVID) { 1519 /* Only MMC1 can interface at 3V without some flavor 1520 * of external transceiver; but they all handle 1.8V. 1521 */ 1522 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1523 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1524 /* 1525 * The mmc_select_voltage fn of the core does 1526 * not seem to set the power_mode to 1527 * MMC_POWER_UP upon recalculating the voltage. 1528 * vdd 1.8v. 1529 */ 1530 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1531 dev_dbg(mmc_dev(host->mmc), 1532 "Switch operation failed\n"); 1533 } 1534 } 1535 1536 if (ios->clock) { 1537 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 1538 if (dsor < 1) 1539 dsor = 1; 1540 1541 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 1542 dsor++; 1543 1544 if (dsor > 250) 1545 dsor = 250; 1546 } 1547 omap_hsmmc_stop_clock(host); 1548 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 1549 regval = regval & ~(CLKD_MASK); 1550 regval = regval | (dsor << 6) | (DTO << 16); 1551 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 1552 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1553 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 1554 1555 /* Wait till the ICS bit is set */ 1556 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 1557 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 1558 && time_before(jiffies, timeout)) 1559 msleep(1); 1560 1561 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1562 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 1563 1564 if (do_send_init_stream) 1565 send_init_stream(host); 1566 1567 con = OMAP_HSMMC_READ(host->base, CON); 1568 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1569 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 1570 else 1571 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 1572 1573 if (host->power_mode == MMC_POWER_OFF) 1574 mmc_host_disable(host->mmc); 1575 else 1576 mmc_host_lazy_disable(host->mmc); 1577} 1578 1579static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1580{ 1581 struct omap_hsmmc_host *host = mmc_priv(mmc); 1582 1583 if (!mmc_slot(host).card_detect) 1584 return -ENOSYS; 1585 return mmc_slot(host).card_detect(host->dev, host->slot_id); 1586} 1587 1588static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1589{ 1590 struct omap_hsmmc_host *host = mmc_priv(mmc); 1591 1592 if (!mmc_slot(host).get_ro) 1593 return -ENOSYS; 1594 return mmc_slot(host).get_ro(host->dev, 0); 1595} 1596 1597static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1598{ 1599 struct omap_hsmmc_host *host = mmc_priv(mmc); 1600 1601 if (mmc_slot(host).init_card) 1602 mmc_slot(host).init_card(card); 1603} 1604 1605static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1606{ 1607 u32 hctl, capa, value; 1608 1609 /* Only MMC1 supports 3.0V */ 1610 if (host->id == OMAP_MMC1_DEVID) { 1611 hctl = SDVS30; 1612 capa = VS30 | VS18; 1613 } else { 1614 hctl = SDVS18; 1615 capa = VS18; 1616 } 1617 1618 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1619 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1620 1621 value = OMAP_HSMMC_READ(host->base, CAPA); 1622 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1623 1624 /* Set the controller to AUTO IDLE mode */ 1625 value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 1626 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 1627 1628 /* Set SD bus power bit */ 1629 set_sd_bus_power(host); 1630} 1631 1632/* 1633 * Dynamic power saving handling, FSM: 1634 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF 1635 * ^___________| | | 1636 * |______________________|______________________| 1637 * 1638 * ENABLED: mmc host is fully functional 1639 * DISABLED: fclk is off 1640 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep 1641 * REGSLEEP: fclk is off, voltage regulator is asleep 1642 * OFF: fclk is off, voltage regulator is off 1643 * 1644 * Transition handlers return the timeout for the next state transition 1645 * or negative error. 1646 */ 1647 1648enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; 1649 1650/* Handler for [ENABLED -> DISABLED] transition */ 1651static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) 1652{ 1653 omap_hsmmc_context_save(host); 1654 clk_disable(host->fclk); 1655 host->dpm_state = DISABLED; 1656 1657 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); 1658 1659 if (host->power_mode == MMC_POWER_OFF) 1660 return 0; 1661 1662 return OMAP_MMC_SLEEP_TIMEOUT; 1663} 1664 1665/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ 1666static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) 1667{ 1668 int err, new_state; 1669 1670 if (!mmc_try_claim_host(host->mmc)) 1671 return 0; 1672 1673 clk_enable(host->fclk); 1674 omap_hsmmc_context_restore(host); 1675 if (mmc_card_can_sleep(host->mmc)) { 1676 err = mmc_card_sleep(host->mmc); 1677 if (err < 0) { 1678 clk_disable(host->fclk); 1679 mmc_release_host(host->mmc); 1680 return err; 1681 } 1682 new_state = CARDSLEEP; 1683 } else { 1684 new_state = REGSLEEP; 1685 } 1686 if (mmc_slot(host).set_sleep) 1687 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, 1688 new_state == CARDSLEEP); 1689 clk_disable(host->fclk); 1690 host->dpm_state = new_state; 1691 1692 mmc_release_host(host->mmc); 1693 1694 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", 1695 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1696 1697 if (mmc_slot(host).no_off) 1698 return 0; 1699 1700 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1701 mmc_slot(host).card_detect || 1702 (mmc_slot(host).get_cover_state && 1703 mmc_slot(host).get_cover_state(host->dev, host->slot_id))) 1704 return OMAP_MMC_OFF_TIMEOUT; 1705 1706 return 0; 1707} 1708 1709/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ 1710static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) 1711{ 1712 if (!mmc_try_claim_host(host->mmc)) 1713 return 0; 1714 1715 if (mmc_slot(host).no_off) 1716 return 0; 1717 1718 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1719 mmc_slot(host).card_detect || 1720 (mmc_slot(host).get_cover_state && 1721 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { 1722 mmc_release_host(host->mmc); 1723 return 0; 1724 } 1725 1726 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1727 host->vdd = 0; 1728 host->power_mode = MMC_POWER_OFF; 1729 1730 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", 1731 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1732 1733 host->dpm_state = OFF; 1734 1735 mmc_release_host(host->mmc); 1736 1737 return 0; 1738} 1739 1740/* Handler for [DISABLED -> ENABLED] transition */ 1741static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) 1742{ 1743 int err; 1744 1745 err = clk_enable(host->fclk); 1746 if (err < 0) 1747 return err; 1748 1749 omap_hsmmc_context_restore(host); 1750 host->dpm_state = ENABLED; 1751 1752 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); 1753 1754 return 0; 1755} 1756 1757/* Handler for [SLEEP -> ENABLED] transition */ 1758static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) 1759{ 1760 if (!mmc_try_claim_host(host->mmc)) 1761 return 0; 1762 1763 clk_enable(host->fclk); 1764 omap_hsmmc_context_restore(host); 1765 if (mmc_slot(host).set_sleep) 1766 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, 1767 host->vdd, host->dpm_state == CARDSLEEP); 1768 if (mmc_card_can_sleep(host->mmc)) 1769 mmc_card_awake(host->mmc); 1770 1771 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", 1772 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1773 1774 host->dpm_state = ENABLED; 1775 1776 mmc_release_host(host->mmc); 1777 1778 return 0; 1779} 1780 1781/* Handler for [OFF -> ENABLED] transition */ 1782static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) 1783{ 1784 clk_enable(host->fclk); 1785 1786 omap_hsmmc_context_restore(host); 1787 omap_hsmmc_conf_bus_power(host); 1788 mmc_power_restore_host(host->mmc); 1789 1790 host->dpm_state = ENABLED; 1791 1792 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); 1793 1794 return 0; 1795} 1796 1797/* 1798 * Bring MMC host to ENABLED from any other PM state. 1799 */ 1800static int omap_hsmmc_enable(struct mmc_host *mmc) 1801{ 1802 struct omap_hsmmc_host *host = mmc_priv(mmc); 1803 1804 switch (host->dpm_state) { 1805 case DISABLED: 1806 return omap_hsmmc_disabled_to_enabled(host); 1807 case CARDSLEEP: 1808 case REGSLEEP: 1809 return omap_hsmmc_sleep_to_enabled(host); 1810 case OFF: 1811 return omap_hsmmc_off_to_enabled(host); 1812 default: 1813 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1814 return -EINVAL; 1815 } 1816} 1817 1818/* 1819 * Bring MMC host in PM state (one level deeper). 1820 */ 1821static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) 1822{ 1823 struct omap_hsmmc_host *host = mmc_priv(mmc); 1824 1825 switch (host->dpm_state) { 1826 case ENABLED: { 1827 int delay; 1828 1829 delay = omap_hsmmc_enabled_to_disabled(host); 1830 if (lazy || delay < 0) 1831 return delay; 1832 return 0; 1833 } 1834 case DISABLED: 1835 return omap_hsmmc_disabled_to_sleep(host); 1836 case CARDSLEEP: 1837 case REGSLEEP: 1838 return omap_hsmmc_sleep_to_off(host); 1839 default: 1840 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1841 return -EINVAL; 1842 } 1843} 1844 1845static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1846{ 1847 struct omap_hsmmc_host *host = mmc_priv(mmc); 1848 int err; 1849 1850 err = clk_enable(host->fclk); 1851 if (err) 1852 return err; 1853 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); 1854 omap_hsmmc_context_restore(host); 1855 return 0; 1856} 1857 1858static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1859{ 1860 struct omap_hsmmc_host *host = mmc_priv(mmc); 1861 1862 omap_hsmmc_context_save(host); 1863 clk_disable(host->fclk); 1864 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); 1865 return 0; 1866} 1867 1868static const struct mmc_host_ops omap_hsmmc_ops = { 1869 .enable = omap_hsmmc_enable_fclk, 1870 .disable = omap_hsmmc_disable_fclk, 1871 .request = omap_hsmmc_request, 1872 .set_ios = omap_hsmmc_set_ios, 1873 .get_cd = omap_hsmmc_get_cd, 1874 .get_ro = omap_hsmmc_get_ro, 1875 .init_card = omap_hsmmc_init_card, 1876 /* NYET -- enable_sdio_irq */ 1877}; 1878 1879static const struct mmc_host_ops omap_hsmmc_ps_ops = { 1880 .enable = omap_hsmmc_enable, 1881 .disable = omap_hsmmc_disable, 1882 .request = omap_hsmmc_request, 1883 .set_ios = omap_hsmmc_set_ios, 1884 .get_cd = omap_hsmmc_get_cd, 1885 .get_ro = omap_hsmmc_get_ro, 1886 .init_card = omap_hsmmc_init_card, 1887 /* NYET -- enable_sdio_irq */ 1888}; 1889 1890#ifdef CONFIG_DEBUG_FS 1891 1892static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1893{ 1894 struct mmc_host *mmc = s->private; 1895 struct omap_hsmmc_host *host = mmc_priv(mmc); 1896 int context_loss = 0; 1897 1898 if (host->pdata->get_context_loss_count) 1899 context_loss = host->pdata->get_context_loss_count(host->dev); 1900 1901 seq_printf(s, "mmc%d:\n" 1902 " enabled:\t%d\n" 1903 " dpm_state:\t%d\n" 1904 " nesting_cnt:\t%d\n" 1905 " ctx_loss:\t%d:%d\n" 1906 "\nregs:\n", 1907 mmc->index, mmc->enabled ? 1 : 0, 1908 host->dpm_state, mmc->nesting_cnt, 1909 host->context_loss, context_loss); 1910 1911 if (host->suspended || host->dpm_state == OFF) { 1912 seq_printf(s, "host suspended, can't read registers\n"); 1913 return 0; 1914 } 1915 1916 if (clk_enable(host->fclk) != 0) { 1917 seq_printf(s, "can't read the regs\n"); 1918 return 0; 1919 } 1920 1921 seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1922 OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1923 seq_printf(s, "CON:\t\t0x%08x\n", 1924 OMAP_HSMMC_READ(host->base, CON)); 1925 seq_printf(s, "HCTL:\t\t0x%08x\n", 1926 OMAP_HSMMC_READ(host->base, HCTL)); 1927 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1928 OMAP_HSMMC_READ(host->base, SYSCTL)); 1929 seq_printf(s, "IE:\t\t0x%08x\n", 1930 OMAP_HSMMC_READ(host->base, IE)); 1931 seq_printf(s, "ISE:\t\t0x%08x\n", 1932 OMAP_HSMMC_READ(host->base, ISE)); 1933 seq_printf(s, "CAPA:\t\t0x%08x\n", 1934 OMAP_HSMMC_READ(host->base, CAPA)); 1935 1936 clk_disable(host->fclk); 1937 1938 return 0; 1939} 1940 1941static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1942{ 1943 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1944} 1945 1946static const struct file_operations mmc_regs_fops = { 1947 .open = omap_hsmmc_regs_open, 1948 .read = seq_read, 1949 .llseek = seq_lseek, 1950 .release = single_release, 1951}; 1952 1953static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1954{ 1955 if (mmc->debugfs_root) 1956 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1957 mmc, &mmc_regs_fops); 1958} 1959 1960#else 1961 1962static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1963{ 1964} 1965 1966#endif 1967 1968static int __init omap_hsmmc_probe(struct platform_device *pdev) 1969{ 1970 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1971 struct mmc_host *mmc; 1972 struct omap_hsmmc_host *host = NULL; 1973 struct resource *res; 1974 int ret, irq; 1975 1976 if (pdata == NULL) { 1977 dev_err(&pdev->dev, "Platform Data is missing\n"); 1978 return -ENXIO; 1979 } 1980 1981 if (pdata->nr_slots == 0) { 1982 dev_err(&pdev->dev, "No Slots\n"); 1983 return -ENXIO; 1984 } 1985 1986 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1987 irq = platform_get_irq(pdev, 0); 1988 if (res == NULL || irq < 0) 1989 return -ENXIO; 1990 1991 res = request_mem_region(res->start, res->end - res->start + 1, 1992 pdev->name); 1993 if (res == NULL) 1994 return -EBUSY; 1995 1996 ret = omap_hsmmc_gpio_init(pdata); 1997 if (ret) 1998 goto err; 1999 2000 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2001 if (!mmc) { 2002 ret = -ENOMEM; 2003 goto err_alloc; 2004 } 2005 2006 host = mmc_priv(mmc); 2007 host->mmc = mmc; 2008 host->pdata = pdata; 2009 host->dev = &pdev->dev; 2010 host->use_dma = 1; 2011 host->dev->dma_mask = &pdata->dma_mask; 2012 host->dma_ch = -1; 2013 host->irq = irq; 2014 host->id = pdev->id; 2015 host->slot_id = 0; 2016 host->mapbase = res->start; 2017 host->base = ioremap(host->mapbase, SZ_4K); 2018 host->power_mode = MMC_POWER_OFF; 2019 2020 platform_set_drvdata(pdev, host); 2021 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 2022 2023 if (mmc_slot(host).power_saving) 2024 mmc->ops = &omap_hsmmc_ps_ops; 2025 else 2026 mmc->ops = &omap_hsmmc_ops; 2027 2028 /* 2029 * If regulator_disable can only put vcc_aux to sleep then there is 2030 * no off state. 2031 */ 2032 if (mmc_slot(host).vcc_aux_disable_is_sleep) 2033 mmc_slot(host).no_off = 1; 2034 2035 mmc->f_min = 400000; 2036 mmc->f_max = 52000000; 2037 2038 spin_lock_init(&host->irq_lock); 2039 2040 host->iclk = clk_get(&pdev->dev, "ick"); 2041 if (IS_ERR(host->iclk)) { 2042 ret = PTR_ERR(host->iclk); 2043 host->iclk = NULL; 2044 goto err1; 2045 } 2046 host->fclk = clk_get(&pdev->dev, "fck"); 2047 if (IS_ERR(host->fclk)) { 2048 ret = PTR_ERR(host->fclk); 2049 host->fclk = NULL; 2050 clk_put(host->iclk); 2051 goto err1; 2052 } 2053 2054 omap_hsmmc_context_save(host); 2055 2056 mmc->caps |= MMC_CAP_DISABLE; 2057 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); 2058 /* we start off in DISABLED state */ 2059 host->dpm_state = DISABLED; 2060 2061 if (mmc_host_enable(host->mmc) != 0) { 2062 clk_put(host->iclk); 2063 clk_put(host->fclk); 2064 goto err1; 2065 } 2066 2067 if (clk_enable(host->iclk) != 0) { 2068 mmc_host_disable(host->mmc); 2069 clk_put(host->iclk); 2070 clk_put(host->fclk); 2071 goto err1; 2072 } 2073 2074 if (cpu_is_omap2430()) { 2075 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 2076 /* 2077 * MMC can still work without debounce clock. 2078 */ 2079 if (IS_ERR(host->dbclk)) 2080 dev_warn(mmc_dev(host->mmc), 2081 "Failed to get debounce clock\n"); 2082 else 2083 host->got_dbclk = 1; 2084 2085 if (host->got_dbclk) 2086 if (clk_enable(host->dbclk) != 0) 2087 dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 2088 " clk failed\n"); 2089 } 2090 2091 /* Since we do only SG emulation, we can have as many segs 2092 * as we want. */ 2093 mmc->max_phys_segs = 1024; 2094 mmc->max_hw_segs = 1024; 2095 2096 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2097 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2098 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2099 mmc->max_seg_size = mmc->max_req_size; 2100 2101 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2102 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2103 2104 switch (mmc_slot(host).wires) { 2105 case 8: 2106 mmc->caps |= MMC_CAP_8_BIT_DATA; 2107 /* Fall through */ 2108 case 4: 2109 mmc->caps |= MMC_CAP_4_BIT_DATA; 2110 break; 2111 case 1: 2112 /* Nothing to crib here */ 2113 case 0: 2114 /* Assuming nothing was given by board, Core use's 1-Bit */ 2115 break; 2116 default: 2117 /* Completely unexpected.. Core goes with 1-Bit Width */ 2118 dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!" 2119 "using 1 instead\n", mmc_slot(host).wires); 2120 } 2121 2122 if (mmc_slot(host).nonremovable) 2123 mmc->caps |= MMC_CAP_NONREMOVABLE; 2124 2125 omap_hsmmc_conf_bus_power(host); 2126 2127 /* Select DMA lines */ 2128 switch (host->id) { 2129 case OMAP_MMC1_DEVID: 2130 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; 2131 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; 2132 break; 2133 case OMAP_MMC2_DEVID: 2134 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; 2135 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; 2136 break; 2137 case OMAP_MMC3_DEVID: 2138 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; 2139 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; 2140 break; 2141 case OMAP_MMC4_DEVID: 2142 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; 2143 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; 2144 break; 2145 case OMAP_MMC5_DEVID: 2146 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; 2147 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; 2148 break; 2149 default: 2150 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); 2151 goto err_irq; 2152 } 2153 2154 /* Request IRQ for MMC operations */ 2155 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, 2156 mmc_hostname(mmc), host); 2157 if (ret) { 2158 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2159 goto err_irq; 2160 } 2161 2162 if (pdata->init != NULL) { 2163 if (pdata->init(&pdev->dev) != 0) { 2164 dev_dbg(mmc_dev(host->mmc), 2165 "Unable to configure MMC IRQs\n"); 2166 goto err_irq_cd_init; 2167 } 2168 } 2169 2170 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2171 ret = omap_hsmmc_reg_get(host); 2172 if (ret) 2173 goto err_reg; 2174 host->use_reg = 1; 2175 } 2176 2177 mmc->ocr_avail = mmc_slot(host).ocr_mask; 2178 2179 /* Request IRQ for card detect */ 2180 if ((mmc_slot(host).card_detect_irq)) { 2181 ret = request_irq(mmc_slot(host).card_detect_irq, 2182 omap_hsmmc_cd_handler, 2183 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2184 | IRQF_DISABLED, 2185 mmc_hostname(mmc), host); 2186 if (ret) { 2187 dev_dbg(mmc_dev(host->mmc), 2188 "Unable to grab MMC CD IRQ\n"); 2189 goto err_irq_cd; 2190 } 2191 } 2192 2193 omap_hsmmc_disable_irq(host); 2194 2195 mmc_host_lazy_disable(host->mmc); 2196 2197 omap_hsmmc_protect_card(host); 2198 2199 mmc_add_host(mmc); 2200 2201 if (mmc_slot(host).name != NULL) { 2202 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2203 if (ret < 0) 2204 goto err_slot_name; 2205 } 2206 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2207 ret = device_create_file(&mmc->class_dev, 2208 &dev_attr_cover_switch); 2209 if (ret < 0) 2210 goto err_slot_name; 2211 } 2212 2213 omap_hsmmc_debugfs(mmc); 2214 2215 return 0; 2216 2217err_slot_name: 2218 mmc_remove_host(mmc); 2219 free_irq(mmc_slot(host).card_detect_irq, host); 2220err_irq_cd: 2221 if (host->use_reg) 2222 omap_hsmmc_reg_put(host); 2223err_reg: 2224 if (host->pdata->cleanup) 2225 host->pdata->cleanup(&pdev->dev); 2226err_irq_cd_init: 2227 free_irq(host->irq, host); 2228err_irq: 2229 mmc_host_disable(host->mmc); 2230 clk_disable(host->iclk); 2231 clk_put(host->fclk); 2232 clk_put(host->iclk); 2233 if (host->got_dbclk) { 2234 clk_disable(host->dbclk); 2235 clk_put(host->dbclk); 2236 } 2237err1: 2238 iounmap(host->base); 2239 platform_set_drvdata(pdev, NULL); 2240 mmc_free_host(mmc); 2241err_alloc: 2242 omap_hsmmc_gpio_free(pdata); 2243err: 2244 release_mem_region(res->start, res->end - res->start + 1); 2245 return ret; 2246} 2247 2248static int omap_hsmmc_remove(struct platform_device *pdev) 2249{ 2250 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2251 struct resource *res; 2252 2253 if (host) { 2254 mmc_host_enable(host->mmc); 2255 mmc_remove_host(host->mmc); 2256 if (host->use_reg) 2257 omap_hsmmc_reg_put(host); 2258 if (host->pdata->cleanup) 2259 host->pdata->cleanup(&pdev->dev); 2260 free_irq(host->irq, host); 2261 if (mmc_slot(host).card_detect_irq) 2262 free_irq(mmc_slot(host).card_detect_irq, host); 2263 flush_scheduled_work(); 2264 2265 mmc_host_disable(host->mmc); 2266 clk_disable(host->iclk); 2267 clk_put(host->fclk); 2268 clk_put(host->iclk); 2269 if (host->got_dbclk) { 2270 clk_disable(host->dbclk); 2271 clk_put(host->dbclk); 2272 } 2273 2274 mmc_free_host(host->mmc); 2275 iounmap(host->base); 2276 omap_hsmmc_gpio_free(pdev->dev.platform_data); 2277 } 2278 2279 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2280 if (res) 2281 release_mem_region(res->start, res->end - res->start + 1); 2282 platform_set_drvdata(pdev, NULL); 2283 2284 return 0; 2285} 2286 2287#ifdef CONFIG_PM 2288static int omap_hsmmc_suspend(struct device *dev) 2289{ 2290 int ret = 0; 2291 struct platform_device *pdev = to_platform_device(dev); 2292 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2293 2294 if (host && host->suspended) 2295 return 0; 2296 2297 if (host) { 2298 host->suspended = 1; 2299 if (host->pdata->suspend) { 2300 ret = host->pdata->suspend(&pdev->dev, 2301 host->slot_id); 2302 if (ret) { 2303 dev_dbg(mmc_dev(host->mmc), 2304 "Unable to handle MMC board" 2305 " level suspend\n"); 2306 host->suspended = 0; 2307 return ret; 2308 } 2309 } 2310 cancel_work_sync(&host->mmc_carddetect_work); 2311 ret = mmc_suspend_host(host->mmc); 2312 mmc_host_enable(host->mmc); 2313 if (ret == 0) { 2314 omap_hsmmc_disable_irq(host); 2315 OMAP_HSMMC_WRITE(host->base, HCTL, 2316 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2317 mmc_host_disable(host->mmc); 2318 clk_disable(host->iclk); 2319 if (host->got_dbclk) 2320 clk_disable(host->dbclk); 2321 } else { 2322 host->suspended = 0; 2323 if (host->pdata->resume) { 2324 ret = host->pdata->resume(&pdev->dev, 2325 host->slot_id); 2326 if (ret) 2327 dev_dbg(mmc_dev(host->mmc), 2328 "Unmask interrupt failed\n"); 2329 } 2330 mmc_host_disable(host->mmc); 2331 } 2332 2333 } 2334 return ret; 2335} 2336 2337/* Routine to resume the MMC device */ 2338static int omap_hsmmc_resume(struct device *dev) 2339{ 2340 int ret = 0; 2341 struct platform_device *pdev = to_platform_device(dev); 2342 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2343 2344 if (host && !host->suspended) 2345 return 0; 2346 2347 if (host) { 2348 ret = clk_enable(host->iclk); 2349 if (ret) 2350 goto clk_en_err; 2351 2352 if (mmc_host_enable(host->mmc) != 0) { 2353 clk_disable(host->iclk); 2354 goto clk_en_err; 2355 } 2356 2357 if (host->got_dbclk) 2358 clk_enable(host->dbclk); 2359 2360 omap_hsmmc_conf_bus_power(host); 2361 2362 if (host->pdata->resume) { 2363 ret = host->pdata->resume(&pdev->dev, host->slot_id); 2364 if (ret) 2365 dev_dbg(mmc_dev(host->mmc), 2366 "Unmask interrupt failed\n"); 2367 } 2368 2369 omap_hsmmc_protect_card(host); 2370 2371 /* Notify the core to resume the host */ 2372 ret = mmc_resume_host(host->mmc); 2373 if (ret == 0) 2374 host->suspended = 0; 2375 2376 mmc_host_lazy_disable(host->mmc); 2377 } 2378 2379 return ret; 2380 2381clk_en_err: 2382 dev_dbg(mmc_dev(host->mmc), 2383 "Failed to enable MMC clocks during resume\n"); 2384 return ret; 2385} 2386 2387#else 2388#define omap_hsmmc_suspend NULL 2389#define omap_hsmmc_resume NULL 2390#endif 2391 2392static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2393 .suspend = omap_hsmmc_suspend, 2394 .resume = omap_hsmmc_resume, 2395}; 2396 2397static struct platform_driver omap_hsmmc_driver = { 2398 .remove = omap_hsmmc_remove, 2399 .driver = { 2400 .name = DRIVER_NAME, 2401 .owner = THIS_MODULE, 2402 .pm = &omap_hsmmc_dev_pm_ops, 2403 }, 2404}; 2405 2406static int __init omap_hsmmc_init(void) 2407{ 2408 /* Register the MMC driver */ 2409 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); 2410} 2411 2412static void __exit omap_hsmmc_cleanup(void) 2413{ 2414 /* Unregister MMC driver */ 2415 platform_driver_unregister(&omap_hsmmc_driver); 2416} 2417 2418module_init(omap_hsmmc_init); 2419module_exit(omap_hsmmc_cleanup); 2420 2421MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2422MODULE_LICENSE("GPL"); 2423MODULE_ALIAS("platform:" DRIVER_NAME); 2424MODULE_AUTHOR("Texas Instruments Inc"); 2425