1/* 2 * timberdale.h timberdale FPGA MFD driver defines 3 * Copyright (c) 2009 Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19/* Supports: 20 * Timberdale FPGA 21 */ 22 23#ifndef MFD_TIMBERDALE_H 24#define MFD_TIMBERDALE_H 25 26#define DRV_VERSION "0.2" 27 28/* This driver only support versions >= 3.8 and < 4.0 */ 29#define TIMB_SUPPORTED_MAJOR 3 30 31/* This driver only support minor >= 8 */ 32#define TIMB_REQUIRED_MINOR 8 33 34/* Registers of the control area */ 35#define TIMB_REV_MAJOR 0x00 36#define TIMB_REV_MINOR 0x04 37#define TIMB_HW_CONFIG 0x08 38#define TIMB_SW_RST 0x40 39 40/* bits in the TIMB_HW_CONFIG register */ 41#define TIMB_HW_CONFIG_SPI_8BIT 0x80 42 43#define TIMB_HW_VER_MASK 0x0f 44#define TIMB_HW_VER0 0x00 45#define TIMB_HW_VER1 0x01 46#define TIMB_HW_VER2 0x02 47#define TIMB_HW_VER3 0x03 48 49#define OCORESOFFSET 0x0 50#define OCORESEND 0x1f 51 52#define SPIOFFSET 0x80 53#define SPIEND 0xff 54 55#define UARTLITEOFFSET 0x100 56#define UARTLITEEND 0x10f 57 58#define RDSOFFSET 0x180 59#define RDSEND 0x183 60 61#define ETHOFFSET 0x300 62#define ETHEND 0x3ff 63 64#define GPIOOFFSET 0x400 65#define GPIOEND 0x7ff 66 67#define CHIPCTLOFFSET 0x800 68#define CHIPCTLEND 0x8ff 69#define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET + 1) 70 71#define INTCOFFSET 0xc00 72#define INTCEND 0xfff 73#define INTCSIZE (INTCEND - INTCOFFSET) 74 75#define MOSTOFFSET 0x1000 76#define MOSTEND 0x13ff 77 78#define UARTOFFSET 0x1400 79#define UARTEND 0x17ff 80 81#define XIICOFFSET 0x1800 82#define XIICEND 0x19ff 83 84#define I2SOFFSET 0x1C00 85#define I2SEND 0x1fff 86 87#define LOGIWOFFSET 0x30000 88#define LOGIWEND 0x37fff 89 90#define MLCOREOFFSET 0x40000 91#define MLCOREEND 0x43fff 92 93#define DMAOFFSET 0x01000000 94#define DMAEND 0x013fffff 95 96/* SDHC0 is placed in PCI bar 1 */ 97#define SDHC0OFFSET 0x00 98#define SDHC0END 0xff 99 100/* SDHC1 is placed in PCI bar 2 */ 101#define SDHC1OFFSET 0x00 102#define SDHC1END 0xff 103 104#define PCI_VENDOR_ID_TIMB 0x10ee 105#define PCI_DEVICE_ID_TIMB 0xa123 106 107#define IRQ_TIMBERDALE_INIC 0 108#define IRQ_TIMBERDALE_MLB 1 109#define IRQ_TIMBERDALE_GPIO 2 110#define IRQ_TIMBERDALE_I2C 3 111#define IRQ_TIMBERDALE_UART 4 112#define IRQ_TIMBERDALE_DMA 5 113#define IRQ_TIMBERDALE_I2S 6 114#define IRQ_TIMBERDALE_TSC_INT 7 115#define IRQ_TIMBERDALE_SDHC 8 116#define IRQ_TIMBERDALE_ADV7180 9 117#define IRQ_TIMBERDALE_ETHSW_IF 10 118#define IRQ_TIMBERDALE_SPI 11 119#define IRQ_TIMBERDALE_UARTLITE 12 120#define IRQ_TIMBERDALE_MLCORE 13 121#define IRQ_TIMBERDALE_MLCORE_BUF 14 122#define IRQ_TIMBERDALE_RDS 15 123#define TIMBERDALE_NR_IRQS 16 124 125#define GPIO_PIN_ASCB 8 126#define GPIO_PIN_INIC_RST 14 127#define GPIO_PIN_BT_RST 15 128#define GPIO_NR_PINS 16 129 130/* DMA Channels */ 131#define DMA_UART_RX 0 132#define DMA_UART_TX 1 133#define DMA_MLB_RX 2 134#define DMA_MLB_TX 3 135#define DMA_VIDEO_RX 4 136#define DMA_VIDEO_DROP 5 137#define DMA_SDHCI_RX 6 138#define DMA_SDHCI_TX 7 139#define DMA_ETH_RX 8 140#define DMA_ETH_TX 9 141 142#endif 143