1/* 2 cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB 3 video capture devices 4 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22#ifndef _POLARIS_REG_H_ 23#define _POLARIS_REG_H_ 24 25#define BOARD_CFG_STAT 0x0 26#define TS_MODE_REG 0x4 27#define TS1_CFG_REG 0x8 28#define TS1_LENGTH_REG 0xc 29#define TS2_CFG_REG 0x10 30#define TS2_LENGTH_REG 0x14 31#define EP_MODE_SET 0x18 32#define CIR_PWR_PTN1 0x1c 33#define CIR_PWR_PTN2 0x20 34#define CIR_PWR_PTN3 0x24 35#define CIR_PWR_MASK0 0x28 36#define CIR_PWR_MASK1 0x2c 37#define CIR_PWR_MASK2 0x30 38#define CIR_GAIN 0x34 39#define CIR_CAR_REG 0x38 40#define CIR_OT_CFG1 0x40 41#define CIR_OT_CFG2 0x44 42#define PWR_CTL_EN 0x74 43 44/* Polaris Endpoints capture mask for register EP_MODE_SET */ 45#define ENABLE_EP1 0x01 /* Bit[0]=1 */ 46#define ENABLE_EP2 0x02 /* Bit[1]=1 */ 47#define ENABLE_EP3 0x04 /* Bit[2]=1 */ 48#define ENABLE_EP4 0x08 /* Bit[3]=1 */ 49#define ENABLE_EP5 0x10 /* Bit[4]=1 */ 50#define ENABLE_EP6 0x20 /* Bit[5]=1 */ 51 52/* Bit definition for register PWR_CTL_EN */ 53#define PWR_MODE_MASK 0x17f 54#define PWR_AV_EN 0x08 /* bit3 */ 55#define PWR_ISO_EN 0x40 /* bit6 */ 56#define PWR_AV_MODE 0x30 /* bit4,5 */ 57#define PWR_TUNER_EN 0x04 /* bit2 */ 58#define PWR_DEMOD_EN 0x02 /* bit1 */ 59#define I2C_DEMOD_EN 0x01 /* bit0 */ 60#define PWR_RESETOUT_EN 0x100 /* bit8 */ 61 62enum AV_MODE{ 63 POLARIS_AVMODE_DEFAULT = 0, 64 POLARIS_AVMODE_DIGITAL = 0x10, 65 POLARIS_AVMODE_ANALOGT_TV = 0x20, 66 POLARIS_AVMODE_ENXTERNAL_AV = 0x30, 67 68}; 69 70/* Colibri Registers */ 71 72#define SINGLE_ENDED 0x0 73#define LOW_IF 0x4 74#define EU_IF 0x9 75#define US_IF 0xa 76 77#define SUP_BLK_TUNE1 0x00 78#define SUP_BLK_TUNE2 0x01 79#define SUP_BLK_TUNE3 0x02 80#define SUP_BLK_XTAL 0x03 81#define SUP_BLK_PLL1 0x04 82#define SUP_BLK_PLL2 0x05 83#define SUP_BLK_PLL3 0x06 84#define SUP_BLK_REF 0x07 85#define SUP_BLK_PWRDN 0x08 86#define SUP_BLK_TESTPAD 0x09 87#define ADC_COM_INT5_STAB_REF 0x0a 88#define ADC_COM_QUANT 0x0b 89#define ADC_COM_BIAS1 0x0c 90#define ADC_COM_BIAS2 0x0d 91#define ADC_COM_BIAS3 0x0e 92#define TESTBUS_CTRL 0x12 93 94#define FLD_PWRDN_TUNING_BIAS 0x10 95#define FLD_PWRDN_ENABLE_PLL 0x08 96#define FLD_PWRDN_PD_BANDGAP 0x04 97#define FLD_PWRDN_PD_BIAS 0x02 98#define FLD_PWRDN_PD_TUNECK 0x01 99 100 101#define ADC_STATUS_CH1 0x20 102#define ADC_STATUS_CH2 0x40 103#define ADC_STATUS_CH3 0x60 104 105#define ADC_STATUS2_CH1 0x21 106#define ADC_STATUS2_CH2 0x41 107#define ADC_STATUS2_CH3 0x61 108 109#define ADC_CAL_ATEST_CH1 0x22 110#define ADC_CAL_ATEST_CH2 0x42 111#define ADC_CAL_ATEST_CH3 0x62 112 113#define ADC_PWRDN_CLAMP_CH1 0x23 114#define ADC_PWRDN_CLAMP_CH2 0x43 115#define ADC_PWRDN_CLAMP_CH3 0x63 116 117#define ADC_CTRL_DAC23_CH1 0x24 118#define ADC_CTRL_DAC23_CH2 0x44 119#define ADC_CTRL_DAC23_CH3 0x64 120 121#define ADC_CTRL_DAC1_CH1 0x25 122#define ADC_CTRL_DAC1_CH2 0x45 123#define ADC_CTRL_DAC1_CH3 0x65 124 125#define ADC_DCSERVO_DEM_CH1 0x26 126#define ADC_DCSERVO_DEM_CH2 0x46 127#define ADC_DCSERVO_DEM_CH3 0x66 128 129#define ADC_FB_FRCRST_CH1 0x27 130#define ADC_FB_FRCRST_CH2 0x47 131#define ADC_FB_FRCRST_CH3 0x67 132 133#define ADC_INPUT_CH1 0x28 134#define ADC_INPUT_CH2 0x48 135#define ADC_INPUT_CH3 0x68 136#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ 137 138#define ADC_NTF_PRECLMP_EN_CH1 0x29 139#define ADC_NTF_PRECLMP_EN_CH2 0x49 140#define ADC_NTF_PRECLMP_EN_CH3 0x69 141 142#define ADC_QGAIN_RES_TRM_CH1 0x2a 143#define ADC_QGAIN_RES_TRM_CH2 0x4a 144#define ADC_QGAIN_RES_TRM_CH3 0x6a 145 146#define ADC_SOC_PRECLMP_TERM_CH1 0x2b 147#define ADC_SOC_PRECLMP_TERM_CH2 0x4b 148#define ADC_SOC_PRECLMP_TERM_CH3 0x6b 149 150#define TESTBUS_CTRL_CH1 0x32 151#define TESTBUS_CTRL_CH2 0x52 152#define TESTBUS_CTRL_CH3 0x72 153 154/****************************************************************************** 155 * DIF registers * 156 ******************************************************************************/ 157#define DIRECT_IF_REVB_BASE 0x00300 158 159/*****************************************************************************/ 160#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) 161/*****************************************************************************/ 162#define FLD_DIF_PLL_LOCK 0x80000000 163/* Reserved [30:29] */ 164#define FLD_DIF_PLL_FREE_RUN 0x10000000 165#define FLD_DIF_PLL_FREQ 0x0fffffff 166 167/*****************************************************************************/ 168#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) 169/*****************************************************************************/ 170#define FLD_DIF_KD_PD 0xff000000 171/* Reserved [23:20] */ 172#define FLD_DIF_KDS_PD 0x000f0000 173#define FLD_DIF_KI_PD 0x0000ff00 174/* Reserved [7:4] */ 175#define FLD_DIF_KIS_PD 0x0000000f 176 177/*****************************************************************************/ 178#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) 179/*****************************************************************************/ 180#define FLD_DIF_KD_FD 0xff000000 181/* Reserved [23:20] */ 182#define FLD_DIF_KDS_FD 0x000f0000 183#define FLD_DIF_KI_FD 0x0000ff00 184#define FLD_DIF_SIG_PROP_SZ 0x000000f0 185#define FLD_DIF_KIS_FD 0x0000000f 186 187/*****************************************************************************/ 188#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c) 189/*****************************************************************************/ 190#define FLD_DIF_PLL_AGC_REF 0xfff00000 191#define FLD_DIF_PLL_AGC_KI 0x000f0000 192/* Reserved [15] */ 193#define FLD_DIF_FREQ_LIMIT 0x00007000 194#define FLD_DIF_K_FD 0x00000f00 195#define FLD_DIF_DOWNSMPL_FD 0x000000ff 196 197/*****************************************************************************/ 198#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) 199/*****************************************************************************/ 200/* Reserved [31:16] */ 201#define FLD_DIF_PLL_AGC_EN 0x00008000 202/* Reserved [14:12] */ 203#define FLD_DIF_PLL_MAN_GAIN 0x00000fff 204 205/*****************************************************************************/ 206#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) 207/*****************************************************************************/ 208#define FLD_DIF_K_AGC_RF 0xf0000000 209#define FLD_DIF_K_AGC_IF 0x0f000000 210#define FLD_DIF_K_AGC_INT 0x00f00000 211/* Reserved [19:12] */ 212#define FLD_DIF_IF_REF 0x00000fff 213 214/*****************************************************************************/ 215#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) 216/*****************************************************************************/ 217#define FLD_DIF_IF_MAX 0xff000000 218#define FLD_DIF_IF_MIN 0x00ff0000 219#define FLD_DIF_IF_AGC 0x0000ffff 220 221/*****************************************************************************/ 222#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c) 223/*****************************************************************************/ 224#define FLD_DIF_INT_MAX 0xff000000 225#define FLD_DIF_INT_MIN 0x00ff0000 226#define FLD_DIF_INT_AGC 0x0000ffff 227 228/*****************************************************************************/ 229#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) 230/*****************************************************************************/ 231#define FLD_DIF_RF_MAX 0xff000000 232#define FLD_DIF_RF_MIN 0x00ff0000 233#define FLD_DIF_RF_AGC 0x0000ffff 234 235/*****************************************************************************/ 236#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) 237/*****************************************************************************/ 238#define FLD_DIF_IF_AGC_IN 0xffff0000 239#define FLD_DIF_INT_AGC_IN 0x0000ffff 240 241/*****************************************************************************/ 242#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) 243/*****************************************************************************/ 244/* Reserved [31:16] */ 245#define FLD_DIF_RF_AGC_IN 0x0000ffff 246 247/*****************************************************************************/ 248#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c) 249/*****************************************************************************/ 250#define FLD_DIF_AFD 0xc0000000 251#define FLD_DIF_K_VID_AGC 0x30000000 252#define FLD_DIF_LINE_LENGTH 0x0fff0000 253#define FLD_DIF_AGC_GAIN 0x0000ffff 254 255/*****************************************************************************/ 256#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) 257/*****************************************************************************/ 258#define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 259/* Reserved [30:30] */ 260#define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000 261/* Reserved [23:17] */ 262#define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 263#define FLD_DIF_VID_MAN_GAIN 0x0000ffff 264 265/*****************************************************************************/ 266#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) 267/*****************************************************************************/ 268#define FLD_DIF_LPF_FREQ 0xc0000000 269#define FLD_DIF_AV_PHASE_INC 0x3f000000 270#define FLD_DIF_AUDIO_FREQ 0x00ffffff 271 272/*****************************************************************************/ 273#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) 274/*****************************************************************************/ 275/* Reserved [31:24] */ 276#define FLD_DIF_IIR23_R2 0x00ff0000 277#define FLD_DIF_IIR23_R1 0x0000ff00 278#define FLD_DIF_IIR1_R1 0x000000ff 279 280/*****************************************************************************/ 281#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c) 282/*****************************************************************************/ 283#define FLD_DIF_DIF_BYPASS 0x80000000 284#define FLD_DIF_FM_NYQ_GAIN 0x40000000 285#define FLD_DIF_RF_AGC_ENA 0x20000000 286#define FLD_DIF_INT_AGC_ENA 0x10000000 287#define FLD_DIF_IF_AGC_ENA 0x08000000 288#define FLD_DIF_FORCE_RF_IF_LOCK 0x04000000 289#define FLD_DIF_VIDEO_AGC_ENA 0x02000000 290#define FLD_DIF_RF_AGC_INV 0x01000000 291#define FLD_DIF_INT_AGC_INV 0x00800000 292#define FLD_DIF_IF_AGC_INV 0x00400000 293#define FLD_DIF_SPEC_INV 0x00200000 294#define FLD_DIF_AUD_FULL_BW 0x00100000 295#define FLD_DIF_AUD_SRC_SEL 0x00080000 296/* Reserved [18] */ 297#define FLD_DIF_IF_FREQ 0x00030000 298/* Reserved [15:14] */ 299#define FLD_DIF_TIP_OFFSET 0x00003f00 300/* Reserved [7:5] */ 301#define FLD_DIF_DITHER_ENA 0x00000010 302/* Reserved [3:1] */ 303#define FLD_DIF_RF_IF_LOCK 0x00000001 304 305/*****************************************************************************/ 306#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) 307/*****************************************************************************/ 308/* Reserved [31:29] */ 309#define FLD_DIF_PHASE_INC 0x1fffffff 310 311/*****************************************************************************/ 312#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) 313/*****************************************************************************/ 314/* Reserved [31:16] */ 315#define FLD_DIF_SRC_KI 0x0000ff00 316#define FLD_DIF_SRC_KD 0x000000ff 317 318/*****************************************************************************/ 319#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) 320/*****************************************************************************/ 321/* Reserved [31:19] */ 322#define FLD_DIF_BPF_COEFF_0 0x00070000 323/* Reserved [15:4] */ 324#define FLD_DIF_BPF_COEFF_1 0x0000000f 325 326/*****************************************************************************/ 327#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) 328/*****************************************************************************/ 329/* Reserved [31:22] */ 330#define FLD_DIF_BPF_COEFF_2 0x003f0000 331/* Reserved [15:7] */ 332#define FLD_DIF_BPF_COEFF_3 0x0000007f 333 334/*****************************************************************************/ 335#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) 336/*****************************************************************************/ 337/* Reserved [31:24] */ 338#define FLD_DIF_BPF_COEFF_4 0x00ff0000 339/* Reserved [15:8] */ 340#define FLD_DIF_BPF_COEFF_5 0x000000ff 341 342/*****************************************************************************/ 343#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) 344/*****************************************************************************/ 345/* Reserved [31:25] */ 346#define FLD_DIF_BPF_COEFF_6 0x01ff0000 347/* Reserved [15:9] */ 348#define FLD_DIF_BPF_COEFF_7 0x000001ff 349 350/*****************************************************************************/ 351#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) 352/*****************************************************************************/ 353/* Reserved [31:26] */ 354#define FLD_DIF_BPF_COEFF_8 0x03ff0000 355/* Reserved [15:10] */ 356#define FLD_DIF_BPF_COEFF_9 0x000003ff 357 358/*****************************************************************************/ 359#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c) 360/*****************************************************************************/ 361/* Reserved [31:27] */ 362#define FLD_DIF_BPF_COEFF_10 0x07ff0000 363/* Reserved [15:11] */ 364#define FLD_DIF_BPF_COEFF_11 0x000007ff 365 366/*****************************************************************************/ 367#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) 368/*****************************************************************************/ 369/* Reserved [31:27] */ 370#define FLD_DIF_BPF_COEFF_12 0x07ff0000 371/* Reserved [15:12] */ 372#define FLD_DIF_BPF_COEFF_13 0x00000fff 373 374/*****************************************************************************/ 375#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) 376/*****************************************************************************/ 377/* Reserved [31:28] */ 378#define FLD_DIF_BPF_COEFF_14 0x0fff0000 379/* Reserved [15:12] */ 380#define FLD_DIF_BPF_COEFF_15 0x00000fff 381 382/*****************************************************************************/ 383#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) 384/*****************************************************************************/ 385/* Reserved [31:29] */ 386#define FLD_DIF_BPF_COEFF_16 0x1fff0000 387/* Reserved [15:13] */ 388#define FLD_DIF_BPF_COEFF_17 0x00001fff 389 390/*****************************************************************************/ 391#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c) 392/*****************************************************************************/ 393/* Reserved [31:29] */ 394#define FLD_DIF_BPF_COEFF_18 0x1fff0000 395/* Reserved [15:13] */ 396#define FLD_DIF_BPF_COEFF_19 0x00001fff 397 398/*****************************************************************************/ 399#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) 400/*****************************************************************************/ 401/* Reserved [31:29] */ 402#define FLD_DIF_BPF_COEFF_20 0x1fff0000 403/* Reserved [15:14] */ 404#define FLD_DIF_BPF_COEFF_21 0x00003fff 405 406/*****************************************************************************/ 407#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) 408/*****************************************************************************/ 409/* Reserved [31:30] */ 410#define FLD_DIF_BPF_COEFF_22 0x3fff0000 411/* Reserved [15:14] */ 412#define FLD_DIF_BPF_COEFF_23 0x00003fff 413 414/*****************************************************************************/ 415#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) 416/*****************************************************************************/ 417/* Reserved [31:30] */ 418#define FLD_DIF_BPF_COEFF_24 0x3fff0000 419/* Reserved [15:14] */ 420#define FLD_DIF_BPF_COEFF_25 0x00003fff 421 422/*****************************************************************************/ 423#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c) 424/*****************************************************************************/ 425/* Reserved [31:30] */ 426#define FLD_DIF_BPF_COEFF_26 0x3fff0000 427/* Reserved [15:14] */ 428#define FLD_DIF_BPF_COEFF_27 0x00003fff 429 430/*****************************************************************************/ 431#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) 432/*****************************************************************************/ 433/* Reserved [31:30] */ 434#define FLD_DIF_BPF_COEFF_28 0x3fff0000 435/* Reserved [15:14] */ 436#define FLD_DIF_BPF_COEFF_29 0x00003fff 437 438/*****************************************************************************/ 439#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) 440/*****************************************************************************/ 441/* Reserved [31:30] */ 442#define FLD_DIF_BPF_COEFF_30 0x3fff0000 443/* Reserved [15:14] */ 444#define FLD_DIF_BPF_COEFF_31 0x00003fff 445 446/*****************************************************************************/ 447#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) 448/*****************************************************************************/ 449/* Reserved [31:30] */ 450#define FLD_DIF_BPF_COEFF_32 0x3fff0000 451/* Reserved [15:14] */ 452#define FLD_DIF_BPF_COEFF_33 0x00003fff 453 454/*****************************************************************************/ 455#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c) 456/*****************************************************************************/ 457/* Reserved [31:30] */ 458#define FLD_DIF_BPF_COEFF_34 0x3fff0000 459/* Reserved [15:14] */ 460#define FLD_DIF_BPF_COEFF_35 0x00003fff 461 462/*****************************************************************************/ 463#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) 464/*****************************************************************************/ 465/* Reserved [31:30] */ 466#define FLD_DIF_BPF_COEFF_36 0x3fff0000 467/* Reserved [15:0] */ 468 469/*****************************************************************************/ 470#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) 471/*****************************************************************************/ 472/* Reserved [31:20] */ 473#define FLD_DIF_RPT_VARIANCE 0x000fffff 474 475/*****************************************************************************/ 476#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) 477/*****************************************************************************/ 478/* Reserved [31:8] */ 479#define FLD_DIF_DIF_SOFT_RST 0x00000080 480#define FLD_DIF_DIF_REG_RST_MSK 0x00000040 481#define FLD_DIF_AGC_RST_MSK 0x00000020 482#define FLD_DIF_CMP_RST_MSK 0x00000010 483#define FLD_DIF_AVS_RST_MSK 0x00000008 484#define FLD_DIF_NYQ_RST_MSK 0x00000004 485#define FLD_DIF_DIF_SRC_RST_MSK 0x00000002 486#define FLD_DIF_PLL_RST_MSK 0x00000001 487 488/*****************************************************************************/ 489#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c) 490/*****************************************************************************/ 491/* Reserved [31:25] */ 492#define FLD_DIF_CTL_IP 0x01ffffff 493 494#endif 495