1/* 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 3 USB video capture devices 4 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 6 7 This program contains the specific code to control the avdecoder chip and 8 other related usb control functions for cx231xx based chipset. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25#include <linux/init.h> 26#include <linux/list.h> 27#include <linux/module.h> 28#include <linux/kernel.h> 29#include <linux/bitmap.h> 30#include <linux/usb.h> 31#include <linux/i2c.h> 32#include <linux/mm.h> 33#include <linux/mutex.h> 34 35#include <media/v4l2-common.h> 36#include <media/v4l2-ioctl.h> 37#include <media/v4l2-chip-ident.h> 38 39#include "cx231xx.h" 40 41/****************************************************************************** 42 -: BLOCK ARRANGEMENT :- 43 I2S block ----------------------| 44 [I2S audio] | 45 | 46 Analog Front End --> Direct IF -|-> Cx25840 --> Audio 47 [video & audio] | [Audio] 48 | 49 |-> Cx25840 --> Video 50 [Video] 51 52*******************************************************************************/ 53 54/****************************************************************************** 55 * A F E - B L O C K C O N T R O L functions * 56 * [ANALOG FRONT END] * 57 ******************************************************************************/ 58static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 59{ 60 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 61 saddr, 2, data, 1); 62} 63 64static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 65{ 66 int status; 67 u32 temp = 0; 68 69 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 70 saddr, 2, &temp, 1); 71 *data = (u8) temp; 72 return status; 73} 74 75int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 76{ 77 int status = 0; 78 u8 temp = 0; 79 u8 afe_power_status = 0; 80 int i = 0; 81 82 /* super block initialize */ 83 temp = (u8) (ref_count & 0xff); 84 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 85 if (status < 0) 86 return status; 87 88 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 89 if (status < 0) 90 return status; 91 92 temp = (u8) ((ref_count & 0x300) >> 8); 93 temp |= 0x40; 94 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 95 if (status < 0) 96 return status; 97 98 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 99 if (status < 0) 100 return status; 101 102 /* enable pll */ 103 while (afe_power_status != 0x18) { 104 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 105 if (status < 0) { 106 cx231xx_info( 107 ": Init Super Block failed in send cmd\n"); 108 break; 109 } 110 111 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 112 afe_power_status &= 0xff; 113 if (status < 0) { 114 cx231xx_info( 115 ": Init Super Block failed in receive cmd\n"); 116 break; 117 } 118 i++; 119 if (i == 10) { 120 cx231xx_info( 121 ": Init Super Block force break in loop !!!!\n"); 122 status = -1; 123 break; 124 } 125 } 126 127 if (status < 0) 128 return status; 129 130 /* start tuning filter */ 131 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 132 if (status < 0) 133 return status; 134 135 msleep(5); 136 137 /* exit tuning */ 138 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 139 140 return status; 141} 142 143int cx231xx_afe_init_channels(struct cx231xx *dev) 144{ 145 int status = 0; 146 147 /* power up all 3 channels, clear pd_buffer */ 148 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 149 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 150 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 151 152 /* Enable quantizer calibration */ 153 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 154 155 /* channel initialize, force modulator (fb) reset */ 156 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 157 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 158 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 159 160 /* start quantilizer calibration */ 161 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 162 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 163 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 164 msleep(5); 165 166 /* exit modulator (fb) reset */ 167 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 168 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 169 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 170 171 /* enable the pre_clamp in each channel for single-ended input */ 172 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 173 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 174 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 175 176 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 177 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 178 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 179 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 180 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 181 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 182 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 183 184 /* dynamic element matching off */ 185 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 186 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 187 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 188 189 return status; 190} 191 192int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 193{ 194 u8 c_value = 0; 195 int status = 0; 196 197 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 198 c_value &= (~(0x50)); 199 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 200 201 return status; 202} 203 204/* 205 The Analog Front End in Cx231xx has 3 channels. These 206 channels are used to share between different inputs 207 like tuner, s-video and composite inputs. 208 209 channel 1 ----- pin 1 to pin4(in reg is 1-4) 210 channel 2 ----- pin 5 to pin8(in reg is 5-8) 211 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 212*/ 213int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 214{ 215 u8 ch1_setting = (u8) input_mux; 216 u8 ch2_setting = (u8) (input_mux >> 8); 217 u8 ch3_setting = (u8) (input_mux >> 16); 218 int status = 0; 219 u8 value = 0; 220 221 if (ch1_setting != 0) { 222 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 223 value &= (!INPUT_SEL_MASK); 224 value |= (ch1_setting - 1) << 4; 225 value &= 0xff; 226 status = afe_write_byte(dev, ADC_INPUT_CH1, value); 227 } 228 229 if (ch2_setting != 0) { 230 status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 231 value &= (!INPUT_SEL_MASK); 232 value |= (ch2_setting - 1) << 4; 233 value &= 0xff; 234 status = afe_write_byte(dev, ADC_INPUT_CH2, value); 235 } 236 237 /* For ch3_setting, the value to put in the register is 238 7 less than the input number */ 239 if (ch3_setting != 0) { 240 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 241 value &= (!INPUT_SEL_MASK); 242 value |= (ch3_setting - 1) << 4; 243 value &= 0xff; 244 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 245 } 246 247 return status; 248} 249 250int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 251{ 252 int status = 0; 253 254 255 switch (mode) { 256 case AFE_MODE_LOW_IF: 257 /* SetupAFEforLowIF(); */ 258 break; 259 case AFE_MODE_BASEBAND: 260 status = cx231xx_afe_setup_AFE_for_baseband(dev); 261 break; 262 case AFE_MODE_EU_HI_IF: 263 /* SetupAFEforEuHiIF(); */ 264 break; 265 case AFE_MODE_US_HI_IF: 266 /* SetupAFEforUsHiIF(); */ 267 break; 268 case AFE_MODE_JAPAN_HI_IF: 269 /* SetupAFEforJapanHiIF(); */ 270 break; 271 } 272 273 if ((mode != dev->afe_mode) && 274 (dev->video_input == CX231XX_VMUX_TELEVISION)) 275 status = cx231xx_afe_adjust_ref_count(dev, 276 CX231XX_VMUX_TELEVISION); 277 278 dev->afe_mode = mode; 279 280 return status; 281} 282 283int cx231xx_afe_update_power_control(struct cx231xx *dev, 284 enum AV_MODE avmode) 285{ 286 u8 afe_power_status = 0; 287 int status = 0; 288 289 switch (dev->model) { 290 case CX231XX_BOARD_CNXT_RDE_250: 291 case CX231XX_BOARD_CNXT_RDU_250: 292 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 293 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 294 FLD_PWRDN_ENABLE_PLL)) { 295 status = afe_write_byte(dev, SUP_BLK_PWRDN, 296 FLD_PWRDN_TUNING_BIAS | 297 FLD_PWRDN_ENABLE_PLL); 298 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 299 &afe_power_status); 300 if (status < 0) 301 break; 302 } 303 304 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 305 0x00); 306 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 307 0x00); 308 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 309 0x00); 310 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 311 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 312 0x70); 313 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 314 0x70); 315 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 316 0x70); 317 318 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 319 &afe_power_status); 320 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 321 FLD_PWRDN_PD_BIAS | 322 FLD_PWRDN_PD_TUNECK; 323 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 324 afe_power_status); 325 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 326 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 327 FLD_PWRDN_ENABLE_PLL)) { 328 status = afe_write_byte(dev, SUP_BLK_PWRDN, 329 FLD_PWRDN_TUNING_BIAS | 330 FLD_PWRDN_ENABLE_PLL); 331 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 332 &afe_power_status); 333 if (status < 0) 334 break; 335 } 336 337 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 338 0x00); 339 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 340 0x00); 341 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 342 0x00); 343 } else { 344 cx231xx_info("Invalid AV mode input\n"); 345 status = -1; 346 } 347 break; 348 default: 349 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 350 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 351 FLD_PWRDN_ENABLE_PLL)) { 352 status = afe_write_byte(dev, SUP_BLK_PWRDN, 353 FLD_PWRDN_TUNING_BIAS | 354 FLD_PWRDN_ENABLE_PLL); 355 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 356 &afe_power_status); 357 if (status < 0) 358 break; 359 } 360 361 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 362 0x40); 363 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 364 0x40); 365 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 366 0x00); 367 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 368 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 369 0x70); 370 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 371 0x70); 372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 373 0x70); 374 375 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 376 &afe_power_status); 377 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 378 FLD_PWRDN_PD_BIAS | 379 FLD_PWRDN_PD_TUNECK; 380 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 381 afe_power_status); 382 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 383 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 384 FLD_PWRDN_ENABLE_PLL)) { 385 status = afe_write_byte(dev, SUP_BLK_PWRDN, 386 FLD_PWRDN_TUNING_BIAS | 387 FLD_PWRDN_ENABLE_PLL); 388 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 389 &afe_power_status); 390 if (status < 0) 391 break; 392 } 393 394 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 395 0x00); 396 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 397 0x00); 398 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 399 0x40); 400 } else { 401 cx231xx_info("Invalid AV mode input\n"); 402 status = -1; 403 } 404 } /* switch */ 405 406 return status; 407} 408 409int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 410{ 411 u8 input_mode = 0; 412 u8 ntf_mode = 0; 413 int status = 0; 414 415 dev->video_input = video_input; 416 417 if (video_input == CX231XX_VMUX_TELEVISION) { 418 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 419 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 420 &ntf_mode); 421 } else { 422 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 423 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 424 &ntf_mode); 425 } 426 427 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 428 429 switch (input_mode) { 430 case SINGLE_ENDED: 431 dev->afe_ref_count = 0x23C; 432 break; 433 case LOW_IF: 434 dev->afe_ref_count = 0x24C; 435 break; 436 case EU_IF: 437 dev->afe_ref_count = 0x258; 438 break; 439 case US_IF: 440 dev->afe_ref_count = 0x260; 441 break; 442 default: 443 break; 444 } 445 446 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 447 448 return status; 449} 450 451/****************************************************************************** 452 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 453 ******************************************************************************/ 454static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 455{ 456 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 457 saddr, 2, data, 1); 458} 459 460static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 461{ 462 int status; 463 u32 temp = 0; 464 465 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 466 saddr, 2, &temp, 1); 467 *data = (u8) temp; 468 return status; 469} 470 471static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 472{ 473 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 474 saddr, 2, data, 4); 475} 476 477static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 478{ 479 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 480 saddr, 2, data, 4); 481} 482 483int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 484{ 485 int status = 0; 486 487 switch (INPUT(input)->type) { 488 case CX231XX_VMUX_COMPOSITE1: 489 case CX231XX_VMUX_SVIDEO: 490 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 491 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 492 /* External AV */ 493 status = cx231xx_set_power_mode(dev, 494 POLARIS_AVMODE_ENXTERNAL_AV); 495 if (status < 0) { 496 cx231xx_errdev("%s: set_power_mode : Failed to" 497 " set Power - errCode [%d]!\n", 498 __func__, status); 499 return status; 500 } 501 } 502 status = cx231xx_set_decoder_video_input(dev, 503 INPUT(input)->type, 504 INPUT(input)->vmux); 505 break; 506 case CX231XX_VMUX_TELEVISION: 507 case CX231XX_VMUX_CABLE: 508 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 509 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 510 /* Tuner */ 511 status = cx231xx_set_power_mode(dev, 512 POLARIS_AVMODE_ANALOGT_TV); 513 if (status < 0) { 514 cx231xx_errdev("%s: set_power_mode:Failed" 515 " to set Power - errCode [%d]!\n", 516 __func__, status); 517 return status; 518 } 519 } 520 status = cx231xx_set_decoder_video_input(dev, 521 CX231XX_VMUX_COMPOSITE1, 522 INPUT(input)->vmux); 523 break; 524 default: 525 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", 526 __func__, INPUT(input)->type); 527 break; 528 } 529 530 /* save the selection */ 531 dev->video_input = input; 532 533 return status; 534} 535 536int cx231xx_set_decoder_video_input(struct cx231xx *dev, 537 u8 pin_type, u8 input) 538{ 539 int status = 0; 540 u32 value = 0; 541 542 if (pin_type != dev->video_input) { 543 status = cx231xx_afe_adjust_ref_count(dev, pin_type); 544 if (status < 0) { 545 cx231xx_errdev("%s: adjust_ref_count :Failed to set" 546 "AFE input mux - errCode [%d]!\n", 547 __func__, status); 548 return status; 549 } 550 } 551 552 /* call afe block to set video inputs */ 553 status = cx231xx_afe_set_input_mux(dev, input); 554 if (status < 0) { 555 cx231xx_errdev("%s: set_input_mux :Failed to set" 556 " AFE input mux - errCode [%d]!\n", 557 __func__, status); 558 return status; 559 } 560 561 switch (pin_type) { 562 case CX231XX_VMUX_COMPOSITE1: 563 status = vid_blk_read_word(dev, AFE_CTRL, &value); 564 value |= (0 << 13) | (1 << 4); 565 value &= ~(1 << 5); 566 567 /* set [24:23] [22:15] to 0 */ 568 value &= (~(0x1ff8000)); 569 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 570 value |= 0x1000000; 571 status = vid_blk_write_word(dev, AFE_CTRL, value); 572 573 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 574 value |= (1 << 7); 575 status = vid_blk_write_word(dev, OUT_CTRL1, value); 576 577 /* Set vip 1.1 output mode */ 578 status = cx231xx_read_modify_write_i2c_dword(dev, 579 VID_BLK_I2C_ADDRESS, 580 OUT_CTRL1, 581 FLD_OUT_MODE, 582 OUT_MODE_VIP11); 583 584 /* Tell DIF object to go to baseband mode */ 585 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 586 if (status < 0) { 587 cx231xx_errdev("%s: cx231xx_dif set to By pass" 588 " mode- errCode [%d]!\n", 589 __func__, status); 590 return status; 591 } 592 593 /* Read the DFE_CTRL1 register */ 594 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 595 596 /* enable the VBI_GATE_EN */ 597 value |= FLD_VBI_GATE_EN; 598 599 /* Enable the auto-VGA enable */ 600 value |= FLD_VGA_AUTO_EN; 601 602 /* Write it back */ 603 status = vid_blk_write_word(dev, DFE_CTRL1, value); 604 605 /* Disable auto config of registers */ 606 status = cx231xx_read_modify_write_i2c_dword(dev, 607 VID_BLK_I2C_ADDRESS, 608 MODE_CTRL, FLD_ACFG_DIS, 609 cx231xx_set_field(FLD_ACFG_DIS, 1)); 610 611 /* Set CVBS input mode */ 612 status = cx231xx_read_modify_write_i2c_dword(dev, 613 VID_BLK_I2C_ADDRESS, 614 MODE_CTRL, FLD_INPUT_MODE, 615 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 616 break; 617 case CX231XX_VMUX_SVIDEO: 618 /* Disable the use of DIF */ 619 620 status = vid_blk_read_word(dev, AFE_CTRL, &value); 621 622 /* set [24:23] [22:15] to 0 */ 623 value &= (~(0x1ff8000)); 624 /* set FUNC_MODE[24:23] = 2 625 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 626 value |= 0x1000010; 627 status = vid_blk_write_word(dev, AFE_CTRL, value); 628 629 /* Tell DIF object to go to baseband mode */ 630 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 631 if (status < 0) { 632 cx231xx_errdev("%s: cx231xx_dif set to By pass" 633 " mode- errCode [%d]!\n", 634 __func__, status); 635 return status; 636 } 637 638 /* Read the DFE_CTRL1 register */ 639 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 640 641 /* enable the VBI_GATE_EN */ 642 value |= FLD_VBI_GATE_EN; 643 644 /* Enable the auto-VGA enable */ 645 value |= FLD_VGA_AUTO_EN; 646 647 /* Write it back */ 648 status = vid_blk_write_word(dev, DFE_CTRL1, value); 649 650 /* Disable auto config of registers */ 651 status = cx231xx_read_modify_write_i2c_dword(dev, 652 VID_BLK_I2C_ADDRESS, 653 MODE_CTRL, FLD_ACFG_DIS, 654 cx231xx_set_field(FLD_ACFG_DIS, 1)); 655 656 /* Set YC input mode */ 657 status = cx231xx_read_modify_write_i2c_dword(dev, 658 VID_BLK_I2C_ADDRESS, 659 MODE_CTRL, 660 FLD_INPUT_MODE, 661 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 662 663 /* Chroma to ADC2 */ 664 status = vid_blk_read_word(dev, AFE_CTRL, &value); 665 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 666 667 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 668 This sets them to use video 669 rather than audio. Only one of the two will be in use. */ 670 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 671 672 status = vid_blk_write_word(dev, AFE_CTRL, value); 673 674 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 675 break; 676 case CX231XX_VMUX_TELEVISION: 677 case CX231XX_VMUX_CABLE: 678 default: 679 switch (dev->model) { 680 case CX231XX_BOARD_CNXT_RDE_250: 681 case CX231XX_BOARD_CNXT_RDU_250: 682 /* Disable the use of DIF */ 683 684 status = vid_blk_read_word(dev, AFE_CTRL, &value); 685 value |= (0 << 13) | (1 << 4); 686 value &= ~(1 << 5); 687 688 /* set [24:23] [22:15] to 0 */ 689 value &= (~(0x1FF8000)); 690 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 691 value |= 0x1000000; 692 status = vid_blk_write_word(dev, AFE_CTRL, value); 693 694 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 695 value |= (1 << 7); 696 status = vid_blk_write_word(dev, OUT_CTRL1, value); 697 698 /* Set vip 1.1 output mode */ 699 status = cx231xx_read_modify_write_i2c_dword(dev, 700 VID_BLK_I2C_ADDRESS, 701 OUT_CTRL1, FLD_OUT_MODE, 702 OUT_MODE_VIP11); 703 704 /* Tell DIF object to go to baseband mode */ 705 status = cx231xx_dif_set_standard(dev, 706 DIF_USE_BASEBAND); 707 if (status < 0) { 708 cx231xx_errdev("%s: cx231xx_dif set to By pass" 709 " mode- errCode [%d]!\n", 710 __func__, status); 711 return status; 712 } 713 714 /* Read the DFE_CTRL1 register */ 715 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 716 717 /* enable the VBI_GATE_EN */ 718 value |= FLD_VBI_GATE_EN; 719 720 /* Enable the auto-VGA enable */ 721 value |= FLD_VGA_AUTO_EN; 722 723 /* Write it back */ 724 status = vid_blk_write_word(dev, DFE_CTRL1, value); 725 726 /* Disable auto config of registers */ 727 status = cx231xx_read_modify_write_i2c_dword(dev, 728 VID_BLK_I2C_ADDRESS, 729 MODE_CTRL, FLD_ACFG_DIS, 730 cx231xx_set_field(FLD_ACFG_DIS, 1)); 731 732 /* Set CVBS input mode */ 733 status = cx231xx_read_modify_write_i2c_dword(dev, 734 VID_BLK_I2C_ADDRESS, 735 MODE_CTRL, FLD_INPUT_MODE, 736 cx231xx_set_field(FLD_INPUT_MODE, 737 INPUT_MODE_CVBS_0)); 738 break; 739 default: 740 /* Enable the DIF for the tuner */ 741 742 /* Reinitialize the DIF */ 743 status = cx231xx_dif_set_standard(dev, dev->norm); 744 if (status < 0) { 745 cx231xx_errdev("%s: cx231xx_dif set to By pass" 746 " mode- errCode [%d]!\n", 747 __func__, status); 748 return status; 749 } 750 751 /* Make sure bypass is cleared */ 752 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 753 754 /* Clear the bypass bit */ 755 value &= ~FLD_DIF_DIF_BYPASS; 756 757 /* Enable the use of the DIF block */ 758 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 759 760 /* Read the DFE_CTRL1 register */ 761 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 762 763 /* Disable the VBI_GATE_EN */ 764 value &= ~FLD_VBI_GATE_EN; 765 766 /* Enable the auto-VGA enable, AGC, and 767 set the skip count to 2 */ 768 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 769 770 /* Write it back */ 771 status = vid_blk_write_word(dev, DFE_CTRL1, value); 772 773 /* Wait until AGC locks up */ 774 msleep(1); 775 776 /* Disable the auto-VGA enable AGC */ 777 value &= ~(FLD_VGA_AUTO_EN); 778 779 /* Write it back */ 780 status = vid_blk_write_word(dev, DFE_CTRL1, value); 781 782 /* Enable Polaris B0 AGC output */ 783 status = vid_blk_read_word(dev, PIN_CTRL, &value); 784 value |= (FLD_OEF_AGC_RF) | 785 (FLD_OEF_AGC_IFVGA) | 786 (FLD_OEF_AGC_IF); 787 status = vid_blk_write_word(dev, PIN_CTRL, value); 788 789 /* Set vip 1.1 output mode */ 790 status = cx231xx_read_modify_write_i2c_dword(dev, 791 VID_BLK_I2C_ADDRESS, 792 OUT_CTRL1, FLD_OUT_MODE, 793 OUT_MODE_VIP11); 794 795 /* Disable auto config of registers */ 796 status = cx231xx_read_modify_write_i2c_dword(dev, 797 VID_BLK_I2C_ADDRESS, 798 MODE_CTRL, FLD_ACFG_DIS, 799 cx231xx_set_field(FLD_ACFG_DIS, 1)); 800 801 /* Set CVBS input mode */ 802 status = cx231xx_read_modify_write_i2c_dword(dev, 803 VID_BLK_I2C_ADDRESS, 804 MODE_CTRL, FLD_INPUT_MODE, 805 cx231xx_set_field(FLD_INPUT_MODE, 806 INPUT_MODE_CVBS_0)); 807 808 /* Set some bits in AFE_CTRL so that channel 2 or 3 809 * is ready to receive audio */ 810 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 811 /* Clear droop comp (bit 19-20) */ 812 /* Set VGA_SEL (for audio control) (bit 7-8) */ 813 status = vid_blk_read_word(dev, AFE_CTRL, &value); 814 815 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 816 817 status = vid_blk_write_word(dev, AFE_CTRL, value); 818 break; 819 820 } 821 break; 822 } 823 824 /* Set raw VBI mode */ 825 status = cx231xx_read_modify_write_i2c_dword(dev, 826 VID_BLK_I2C_ADDRESS, 827 OUT_CTRL1, FLD_VBIHACTRAW_EN, 828 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 829 830 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 831 if (value & 0x02) { 832 value |= (1 << 19); 833 status = vid_blk_write_word(dev, OUT_CTRL1, value); 834 } 835 836 return status; 837} 838 839/* 840 * Handle any video-mode specific overrides that are different 841 * on a per video standards basis after touching the MODE_CTRL 842 * register which resets many values for autodetect 843 */ 844int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 845{ 846 int status = 0; 847 848 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", 849 (unsigned int)dev->norm); 850 851 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 852 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 853 854 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 855 cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 856 857 /* Move the close caption lines out of active video, 858 adjust the active video start point */ 859 status = cx231xx_read_modify_write_i2c_dword(dev, 860 VID_BLK_I2C_ADDRESS, 861 VERT_TIM_CTRL, 862 FLD_VBLANK_CNT, 0x18); 863 status = cx231xx_read_modify_write_i2c_dword(dev, 864 VID_BLK_I2C_ADDRESS, 865 VERT_TIM_CTRL, 866 FLD_VACTIVE_CNT, 867 0x1E6000); 868 status = cx231xx_read_modify_write_i2c_dword(dev, 869 VID_BLK_I2C_ADDRESS, 870 VERT_TIM_CTRL, 871 FLD_V656BLANK_CNT, 872 0x1E000000); 873 874 status = cx231xx_read_modify_write_i2c_dword(dev, 875 VID_BLK_I2C_ADDRESS, 876 HORIZ_TIM_CTRL, 877 FLD_HBLANK_CNT, 878 cx231xx_set_field 879 (FLD_HBLANK_CNT, 0x79)); 880 } else if (dev->norm & V4L2_STD_SECAM) { 881 cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 882 status = cx231xx_read_modify_write_i2c_dword(dev, 883 VID_BLK_I2C_ADDRESS, 884 VERT_TIM_CTRL, 885 FLD_VBLANK_CNT, 0x24); 886 /* Adjust the active video horizontal start point */ 887 status = cx231xx_read_modify_write_i2c_dword(dev, 888 VID_BLK_I2C_ADDRESS, 889 HORIZ_TIM_CTRL, 890 FLD_HBLANK_CNT, 891 cx231xx_set_field 892 (FLD_HBLANK_CNT, 0x85)); 893 } else { 894 cx231xx_info("do_mode_ctrl_overrides PAL\n"); 895 status = cx231xx_read_modify_write_i2c_dword(dev, 896 VID_BLK_I2C_ADDRESS, 897 VERT_TIM_CTRL, 898 FLD_VBLANK_CNT, 0x24); 899 /* Adjust the active video horizontal start point */ 900 status = cx231xx_read_modify_write_i2c_dword(dev, 901 VID_BLK_I2C_ADDRESS, 902 HORIZ_TIM_CTRL, 903 FLD_HBLANK_CNT, 904 cx231xx_set_field 905 (FLD_HBLANK_CNT, 0x85)); 906 } 907 908 return status; 909} 910 911int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 912{ 913 int status = 0; 914 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 915 916 switch (INPUT(input)->amux) { 917 case CX231XX_AMUX_VIDEO: 918 ainput = AUDIO_INPUT_TUNER_TV; 919 break; 920 case CX231XX_AMUX_LINE_IN: 921 status = cx231xx_i2s_blk_set_audio_input(dev, input); 922 ainput = AUDIO_INPUT_LINE; 923 break; 924 default: 925 break; 926 } 927 928 status = cx231xx_set_audio_decoder_input(dev, ainput); 929 930 return status; 931} 932 933int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 934 enum AUDIO_INPUT audio_input) 935{ 936 u32 dwval; 937 int status; 938 u8 gen_ctrl; 939 u32 value = 0; 940 941 /* Put it in soft reset */ 942 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 943 gen_ctrl |= 1; 944 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 945 946 switch (audio_input) { 947 case AUDIO_INPUT_LINE: 948 /* setup AUD_IO control from Merlin paralle output */ 949 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 950 AUD_CHAN_SRC_PARALLEL); 951 status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 952 953 /* setup input to Merlin, SRC2 connect to AC97 954 bypass upsample-by-2, slave mode, sony mode, left justify 955 adr 091c, dat 01000000 */ 956 status = vid_blk_read_word(dev, AC97_CTL, &dwval); 957 958 status = vid_blk_write_word(dev, AC97_CTL, 959 (dwval | FLD_AC97_UP2X_BYPASS)); 960 961 /* select the parallel1 and SRC3 */ 962 status = vid_blk_write_word(dev, BAND_OUT_SEL, 963 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 964 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 965 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 966 967 /* unmute all, AC97 in, independence mode 968 adr 08d0, data 0x00063073 */ 969 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 970 971 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 972 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 973 status = vid_blk_write_word(dev, PATH1_VOL_CTL, 974 (dwval | FLD_PATH1_AVC_THRESHOLD)); 975 976 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 977 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 978 status = vid_blk_write_word(dev, PATH1_SC_CTL, 979 (dwval | FLD_PATH1_SC_THRESHOLD)); 980 break; 981 982 case AUDIO_INPUT_TUNER_TV: 983 default: 984 985 /* Setup SRC sources and clocks */ 986 status = vid_blk_write_word(dev, BAND_OUT_SEL, 987 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 988 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 989 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 990 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 991 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 992 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 993 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 994 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 995 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 996 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 997 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 998 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 999 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 1000 1001 /* Setup the AUD_IO control */ 1002 status = vid_blk_write_word(dev, AUD_IO_CTRL, 1003 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1004 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1005 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1006 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1007 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 1008 1009 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1010 1011 /* setAudioStandard(_audio_standard); */ 1012 1013 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1014 switch (dev->model) { 1015 case CX231XX_BOARD_CNXT_RDE_250: 1016 case CX231XX_BOARD_CNXT_RDU_250: 1017 status = cx231xx_read_modify_write_i2c_dword(dev, 1018 VID_BLK_I2C_ADDRESS, 1019 CHIP_CTRL, 1020 FLD_SIF_EN, 1021 cx231xx_set_field(FLD_SIF_EN, 1)); 1022 break; 1023 default: 1024 break; 1025 } 1026 break; 1027 1028 case AUDIO_INPUT_TUNER_FM: 1029 /* use SIF for FM radio 1030 setupFM(); 1031 setAudioStandard(_audio_standard); 1032 */ 1033 break; 1034 1035 case AUDIO_INPUT_MUTE: 1036 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 1037 break; 1038 } 1039 1040 /* Take it out of soft reset */ 1041 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1042 gen_ctrl &= ~1; 1043 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1044 1045 return status; 1046} 1047 1048/* Set resolution of the video */ 1049int cx231xx_resolution_set(struct cx231xx *dev) 1050{ 1051 /* set horzontal scale */ 1052 int status = vid_blk_write_word(dev, HSCALE_CTRL, dev->hscale); 1053 if (status) 1054 return status; 1055 1056 /* set vertical scale */ 1057 return vid_blk_write_word(dev, VSCALE_CTRL, dev->vscale); 1058} 1059 1060/****************************************************************************** 1061 * C H I P Specific C O N T R O L functions * 1062 ******************************************************************************/ 1063int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1064{ 1065 u32 value; 1066 int status = 0; 1067 1068 status = vid_blk_read_word(dev, PIN_CTRL, &value); 1069 value |= (~dev->board.ctl_pin_status_mask); 1070 status = vid_blk_write_word(dev, PIN_CTRL, value); 1071 1072 return status; 1073} 1074 1075int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 1076 u8 analog_or_digital) 1077{ 1078 int status = 0; 1079 1080 /* first set the direction to output */ 1081 status = cx231xx_set_gpio_direction(dev, 1082 dev->board. 1083 agc_analog_digital_select_gpio, 1); 1084 1085 /* 0 - demod ; 1 - Analog mode */ 1086 status = cx231xx_set_gpio_value(dev, 1087 dev->board.agc_analog_digital_select_gpio, 1088 analog_or_digital); 1089 1090 return status; 1091} 1092 1093int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex) 1094{ 1095 u8 value[4] = { 0, 0, 0, 0 }; 1096 int status = 0; 1097 1098 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex); 1099 1100 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 1101 PWR_CTL_EN, value, 4); 1102 if (status < 0) 1103 return status; 1104 1105 if (I2CIndex == I2C_1) { 1106 if (value[0] & I2C_DEMOD_EN) { 1107 value[0] &= ~I2C_DEMOD_EN; 1108 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1109 PWR_CTL_EN, value, 4); 1110 } 1111 } else { 1112 if (!(value[0] & I2C_DEMOD_EN)) { 1113 value[0] |= I2C_DEMOD_EN; 1114 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1115 PWR_CTL_EN, value, 4); 1116 } 1117 } 1118 1119 return status; 1120 1121} 1122 1123/****************************************************************************** 1124 * D I F - B L O C K C O N T R O L functions * 1125 ******************************************************************************/ 1126int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1127 u32 function_mode, u32 standard) 1128{ 1129 int status = 0; 1130 1131 if (mode == V4L2_TUNER_RADIO) { 1132 /* C2HH */ 1133 /* lo if big signal */ 1134 status = cx231xx_reg_mask_write(dev, 1135 VID_BLK_I2C_ADDRESS, 32, 1136 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1137 /* FUNC_MODE = DIF */ 1138 status = cx231xx_reg_mask_write(dev, 1139 VID_BLK_I2C_ADDRESS, 32, 1140 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1141 /* IF_MODE */ 1142 status = cx231xx_reg_mask_write(dev, 1143 VID_BLK_I2C_ADDRESS, 32, 1144 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1145 /* no inv */ 1146 status = cx231xx_reg_mask_write(dev, 1147 VID_BLK_I2C_ADDRESS, 32, 1148 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1149 } else if (standard != DIF_USE_BASEBAND) { 1150 if (standard & V4L2_STD_MN) { 1151 /* lo if big signal */ 1152 status = cx231xx_reg_mask_write(dev, 1153 VID_BLK_I2C_ADDRESS, 32, 1154 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1155 /* FUNC_MODE = DIF */ 1156 status = cx231xx_reg_mask_write(dev, 1157 VID_BLK_I2C_ADDRESS, 32, 1158 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1159 function_mode); 1160 /* IF_MODE */ 1161 status = cx231xx_reg_mask_write(dev, 1162 VID_BLK_I2C_ADDRESS, 32, 1163 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1164 /* no inv */ 1165 status = cx231xx_reg_mask_write(dev, 1166 VID_BLK_I2C_ADDRESS, 32, 1167 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1168 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1169 status = cx231xx_reg_mask_write(dev, 1170 VID_BLK_I2C_ADDRESS, 32, 1171 AUD_IO_CTRL, 0, 31, 0x00000003); 1172 } else if ((standard == V4L2_STD_PAL_I) | 1173 (standard & V4L2_STD_SECAM)) { 1174 /* C2HH setup */ 1175 /* lo if big signal */ 1176 status = cx231xx_reg_mask_write(dev, 1177 VID_BLK_I2C_ADDRESS, 32, 1178 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1179 /* FUNC_MODE = DIF */ 1180 status = cx231xx_reg_mask_write(dev, 1181 VID_BLK_I2C_ADDRESS, 32, 1182 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1183 function_mode); 1184 /* IF_MODE */ 1185 status = cx231xx_reg_mask_write(dev, 1186 VID_BLK_I2C_ADDRESS, 32, 1187 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1188 /* no inv */ 1189 status = cx231xx_reg_mask_write(dev, 1190 VID_BLK_I2C_ADDRESS, 32, 1191 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1192 } else { 1193 /* default PAL BG */ 1194 /* C2HH setup */ 1195 /* lo if big signal */ 1196 status = cx231xx_reg_mask_write(dev, 1197 VID_BLK_I2C_ADDRESS, 32, 1198 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1199 /* FUNC_MODE = DIF */ 1200 status = cx231xx_reg_mask_write(dev, 1201 VID_BLK_I2C_ADDRESS, 32, 1202 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1203 function_mode); 1204 /* IF_MODE */ 1205 status = cx231xx_reg_mask_write(dev, 1206 VID_BLK_I2C_ADDRESS, 32, 1207 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1208 /* no inv */ 1209 status = cx231xx_reg_mask_write(dev, 1210 VID_BLK_I2C_ADDRESS, 32, 1211 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1212 } 1213 } 1214 1215 return status; 1216} 1217 1218int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 1219{ 1220 int status = 0; 1221 u32 dif_misc_ctrl_value = 0; 1222 u32 func_mode = 0; 1223 1224 cx231xx_info("%s: setStandard to %x\n", __func__, standard); 1225 1226 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 1227 if (standard != DIF_USE_BASEBAND) 1228 dev->norm = standard; 1229 1230 switch (dev->model) { 1231 case CX231XX_BOARD_CNXT_RDE_250: 1232 case CX231XX_BOARD_CNXT_RDU_250: 1233 func_mode = 0x03; 1234 break; 1235 default: 1236 func_mode = 0x01; 1237 } 1238 1239 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1240 func_mode, standard); 1241 1242 if (standard == DIF_USE_BASEBAND) { /* base band */ 1243 /* There is a different SRC_PHASE_INC value 1244 for baseband vs. DIF */ 1245 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 1246 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1247 &dif_misc_ctrl_value); 1248 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1249 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1250 dif_misc_ctrl_value); 1251 } else if (standard & V4L2_STD_PAL_D) { 1252 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1253 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1254 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1255 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1256 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1257 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1258 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1259 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1260 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1261 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1262 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1263 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1264 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1265 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1266 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1267 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1268 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1269 DIF_AGC_IF_INT_CURRENT, 0, 31, 1270 0x26001700); 1271 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1272 DIF_AGC_RF_CURRENT, 0, 31, 1273 0x00002660); 1274 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1275 DIF_VIDEO_AGC_CTRL, 0, 31, 1276 0x72500800); 1277 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1278 DIF_VID_AUD_OVERRIDE, 0, 31, 1279 0x27000100); 1280 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1281 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1282 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1283 DIF_COMP_FLT_CTRL, 0, 31, 1284 0x00000000); 1285 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1286 DIF_SRC_PHASE_INC, 0, 31, 1287 0x1befbf06); 1288 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1289 DIF_SRC_GAIN_CONTROL, 0, 31, 1290 0x000035e8); 1291 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1292 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1293 /* Save the Spec Inversion value */ 1294 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1295 dif_misc_ctrl_value |= 0x3a023F11; 1296 } else if (standard & V4L2_STD_PAL_I) { 1297 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1298 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1299 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1300 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1301 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1302 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1303 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1304 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1305 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1306 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1307 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1308 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1309 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1310 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1311 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1312 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1313 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1314 DIF_AGC_IF_INT_CURRENT, 0, 31, 1315 0x26001700); 1316 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1317 DIF_AGC_RF_CURRENT, 0, 31, 1318 0x00002660); 1319 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1320 DIF_VIDEO_AGC_CTRL, 0, 31, 1321 0x72500800); 1322 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1323 DIF_VID_AUD_OVERRIDE, 0, 31, 1324 0x27000100); 1325 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1326 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1327 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1328 DIF_COMP_FLT_CTRL, 0, 31, 1329 0x00000000); 1330 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1331 DIF_SRC_PHASE_INC, 0, 31, 1332 0x1befbf06); 1333 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1334 DIF_SRC_GAIN_CONTROL, 0, 31, 1335 0x000035e8); 1336 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1337 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1338 /* Save the Spec Inversion value */ 1339 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1340 dif_misc_ctrl_value |= 0x3a033F11; 1341 } else if (standard & V4L2_STD_PAL_M) { 1342 /* improved Low Frequency Phase Noise */ 1343 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1344 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1345 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1346 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1347 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1348 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1349 0x26001700); 1350 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1351 0x00002660); 1352 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1353 0x72500800); 1354 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1355 0x27000100); 1356 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 1357 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1358 0x009f50c1); 1359 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1360 0x1befbf06); 1361 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1362 0x000035e8); 1363 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1364 0x00000000); 1365 /* Save the Spec Inversion value */ 1366 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1367 dif_misc_ctrl_value |= 0x3A0A3F10; 1368 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1369 /* improved Low Frequency Phase Noise */ 1370 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1371 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1372 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1373 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1374 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1375 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1376 0x26001700); 1377 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1378 0x00002660); 1379 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1380 0x72500800); 1381 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1382 0x27000100); 1383 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 1384 0x012c405d); 1385 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1386 0x009f50c1); 1387 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1388 0x1befbf06); 1389 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1390 0x000035e8); 1391 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1392 0x00000000); 1393 /* Save the Spec Inversion value */ 1394 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1395 dif_misc_ctrl_value = 0x3A093F10; 1396 } else if (standard & 1397 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1398 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1399 1400 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1401 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1402 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1403 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1404 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1405 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1406 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1407 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1408 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1409 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1410 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1411 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1412 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1413 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1414 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1415 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1416 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1417 DIF_AGC_IF_INT_CURRENT, 0, 31, 1418 0x26001700); 1419 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1420 DIF_AGC_RF_CURRENT, 0, 31, 1421 0x00002660); 1422 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1423 DIF_VID_AUD_OVERRIDE, 0, 31, 1424 0x27000100); 1425 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1426 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1427 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1428 DIF_COMP_FLT_CTRL, 0, 31, 1429 0x00000000); 1430 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1431 DIF_SRC_PHASE_INC, 0, 31, 1432 0x1befbf06); 1433 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1434 DIF_SRC_GAIN_CONTROL, 0, 31, 1435 0x000035e8); 1436 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1437 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1438 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1439 DIF_VIDEO_AGC_CTRL, 0, 31, 1440 0xf4000000); 1441 1442 /* Save the Spec Inversion value */ 1443 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1444 dif_misc_ctrl_value |= 0x3a023F11; 1445 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1446 /* Is it SECAM_L1? */ 1447 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1448 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1449 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1450 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1451 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1452 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1453 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1454 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1455 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1456 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1457 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1458 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1459 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1460 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1461 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1462 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1463 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1464 DIF_AGC_IF_INT_CURRENT, 0, 31, 1465 0x26001700); 1466 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1467 DIF_AGC_RF_CURRENT, 0, 31, 1468 0x00002660); 1469 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1470 DIF_VID_AUD_OVERRIDE, 0, 31, 1471 0x27000100); 1472 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1473 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1474 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1475 DIF_COMP_FLT_CTRL, 0, 31, 1476 0x00000000); 1477 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1478 DIF_SRC_PHASE_INC, 0, 31, 1479 0x1befbf06); 1480 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1481 DIF_SRC_GAIN_CONTROL, 0, 31, 1482 0x000035e8); 1483 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1484 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1485 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1486 DIF_VIDEO_AGC_CTRL, 0, 31, 1487 0xf2560000); 1488 1489 /* Save the Spec Inversion value */ 1490 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1491 dif_misc_ctrl_value |= 0x3a023F11; 1492 1493 } else if (standard & V4L2_STD_NTSC_M) { 1494 /* V4L2_STD_NTSC_M (75 IRE Setup) Or 1495 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 1496 1497 /* For NTSC the centre frequency of video coming out of 1498 sidewinder is around 7.1MHz or 3.6MHz depending on the 1499 spectral inversion. so for a non spectrally inverted channel 1500 the pll freq word is 0x03420c49 1501 */ 1502 1503 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 1504 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 1505 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 1506 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1507 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 1508 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1509 0x26001700); 1510 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1511 0x00002660); 1512 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1513 0x04000800); 1514 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1515 0x27000100); 1516 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 1517 1518 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1519 0x009f50c1); 1520 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1521 0x1befbf06); 1522 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1523 0x000035e8); 1524 1525 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 1526 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 1527 0xC2262600); 1528 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 1529 1530 /* Save the Spec Inversion value */ 1531 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1532 dif_misc_ctrl_value |= 0x3a003F10; 1533 } else { 1534 /* default PAL BG */ 1535 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1536 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1537 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1538 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1539 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1540 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1541 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1542 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1543 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1544 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1545 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1546 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1547 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1548 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1549 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1550 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1551 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1552 DIF_AGC_IF_INT_CURRENT, 0, 31, 1553 0x26001700); 1554 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1555 DIF_AGC_RF_CURRENT, 0, 31, 1556 0x00002660); 1557 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1558 DIF_VIDEO_AGC_CTRL, 0, 31, 1559 0x72500800); 1560 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1561 DIF_VID_AUD_OVERRIDE, 0, 31, 1562 0x27000100); 1563 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1564 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 1565 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1566 DIF_COMP_FLT_CTRL, 0, 31, 1567 0x00A653A8); 1568 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1569 DIF_SRC_PHASE_INC, 0, 31, 1570 0x1befbf06); 1571 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1572 DIF_SRC_GAIN_CONTROL, 0, 31, 1573 0x000035e8); 1574 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1575 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1576 /* Save the Spec Inversion value */ 1577 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1578 dif_misc_ctrl_value |= 0x3a013F11; 1579 } 1580 1581 /* The AGC values should be the same for all standards, 1582 AUD_SRC_SEL[19] should always be disabled */ 1583 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 1584 1585 /* It is still possible to get Set Standard calls even when we 1586 are in FM mode. 1587 This is done to override the value for FM. */ 1588 if (dev->active_mode == V4L2_TUNER_RADIO) 1589 dif_misc_ctrl_value = 0x7a080000; 1590 1591 /* Write the calculated value for misc ontrol register */ 1592 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 1593 1594 return status; 1595} 1596 1597int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 1598{ 1599 int status = 0; 1600 u32 dwval; 1601 1602 /* Set the RF and IF k_agc values to 3 */ 1603 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 1604 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 1605 dwval |= 0x33000000; 1606 1607 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 1608 1609 return status; 1610} 1611 1612int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 1613{ 1614 int status = 0; 1615 u32 dwval; 1616 1617 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 1618 * SECAM L/B/D standards */ 1619 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 1620 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 1621 1622 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 1623 V4L2_STD_SECAM_D)) 1624 dwval |= 0x88000000; 1625 else 1626 dwval |= 0x44000000; 1627 1628 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 1629 1630 return status; 1631} 1632 1633/****************************************************************************** 1634 * I 2 S - B L O C K C O N T R O L functions * 1635 ******************************************************************************/ 1636int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 1637{ 1638 int status = 0; 1639 u32 value; 1640 1641 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 1642 CH_PWR_CTRL1, 1, &value, 1); 1643 /* enables clock to delta-sigma and decimation filter */ 1644 value |= 0x80; 1645 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 1646 CH_PWR_CTRL1, 1, value, 1); 1647 /* power up all channel */ 1648 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 1649 CH_PWR_CTRL2, 1, 0x00, 1); 1650 1651 return status; 1652} 1653 1654int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 1655 enum AV_MODE avmode) 1656{ 1657 int status = 0; 1658 u32 value = 0; 1659 1660 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 1661 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 1662 CH_PWR_CTRL2, 1, &value, 1); 1663 value |= 0xfe; 1664 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 1665 CH_PWR_CTRL2, 1, value, 1); 1666 } else { 1667 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 1668 CH_PWR_CTRL2, 1, 0x00, 1); 1669 } 1670 1671 return status; 1672} 1673 1674/* set i2s_blk for audio input types */ 1675int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 1676{ 1677 int status = 0; 1678 1679 switch (audio_input) { 1680 case CX231XX_AMUX_LINE_IN: 1681 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 1682 CH_PWR_CTRL2, 1, 0x00, 1); 1683 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 1684 CH_PWR_CTRL1, 1, 0x80, 1); 1685 break; 1686 case CX231XX_AMUX_VIDEO: 1687 default: 1688 break; 1689 } 1690 1691 dev->ctl_ainput = audio_input; 1692 1693 return status; 1694} 1695 1696/****************************************************************************** 1697 * P O W E R C O N T R O L functions * 1698 ******************************************************************************/ 1699int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 1700{ 1701 u8 value[4] = { 0, 0, 0, 0 }; 1702 u32 tmp = 0; 1703 int status = 0; 1704 1705 if (dev->power_mode != mode) 1706 dev->power_mode = mode; 1707 else { 1708 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n", 1709 mode); 1710 return 0; 1711 } 1712 1713 cx231xx_info(" setPowerMode::mode = %d\n", mode); 1714 1715 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 1716 4); 1717 if (status < 0) 1718 return status; 1719 1720 tmp = *((u32 *) value); 1721 1722 switch (mode) { 1723 case POLARIS_AVMODE_ENXTERNAL_AV: 1724 1725 tmp &= (~PWR_MODE_MASK); 1726 1727 tmp |= PWR_AV_EN; 1728 value[0] = (u8) tmp; 1729 value[1] = (u8) (tmp >> 8); 1730 value[2] = (u8) (tmp >> 16); 1731 value[3] = (u8) (tmp >> 24); 1732 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1733 PWR_CTL_EN, value, 4); 1734 msleep(PWR_SLEEP_INTERVAL); 1735 1736 tmp |= PWR_ISO_EN; 1737 value[0] = (u8) tmp; 1738 value[1] = (u8) (tmp >> 8); 1739 value[2] = (u8) (tmp >> 16); 1740 value[3] = (u8) (tmp >> 24); 1741 status = 1742 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 1743 value, 4); 1744 msleep(PWR_SLEEP_INTERVAL); 1745 1746 tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 1747 value[0] = (u8) tmp; 1748 value[1] = (u8) (tmp >> 8); 1749 value[2] = (u8) (tmp >> 16); 1750 value[3] = (u8) (tmp >> 24); 1751 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1752 PWR_CTL_EN, value, 4); 1753 1754 /* reset state of xceive tuner */ 1755 dev->xc_fw_load_done = 0; 1756 break; 1757 1758 case POLARIS_AVMODE_ANALOGT_TV: 1759 1760 tmp &= (~PWR_DEMOD_EN); 1761 tmp |= (I2C_DEMOD_EN); 1762 value[0] = (u8) tmp; 1763 value[1] = (u8) (tmp >> 8); 1764 value[2] = (u8) (tmp >> 16); 1765 value[3] = (u8) (tmp >> 24); 1766 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1767 PWR_CTL_EN, value, 4); 1768 msleep(PWR_SLEEP_INTERVAL); 1769 1770 if (!(tmp & PWR_TUNER_EN)) { 1771 tmp |= (PWR_TUNER_EN); 1772 value[0] = (u8) tmp; 1773 value[1] = (u8) (tmp >> 8); 1774 value[2] = (u8) (tmp >> 16); 1775 value[3] = (u8) (tmp >> 24); 1776 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1777 PWR_CTL_EN, value, 4); 1778 msleep(PWR_SLEEP_INTERVAL); 1779 } 1780 1781 if (!(tmp & PWR_AV_EN)) { 1782 tmp |= PWR_AV_EN; 1783 value[0] = (u8) tmp; 1784 value[1] = (u8) (tmp >> 8); 1785 value[2] = (u8) (tmp >> 16); 1786 value[3] = (u8) (tmp >> 24); 1787 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1788 PWR_CTL_EN, value, 4); 1789 msleep(PWR_SLEEP_INTERVAL); 1790 } 1791 if (!(tmp & PWR_ISO_EN)) { 1792 tmp |= PWR_ISO_EN; 1793 value[0] = (u8) tmp; 1794 value[1] = (u8) (tmp >> 8); 1795 value[2] = (u8) (tmp >> 16); 1796 value[3] = (u8) (tmp >> 24); 1797 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1798 PWR_CTL_EN, value, 4); 1799 msleep(PWR_SLEEP_INTERVAL); 1800 } 1801 1802 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 1803 tmp |= POLARIS_AVMODE_ANALOGT_TV; 1804 value[0] = (u8) tmp; 1805 value[1] = (u8) (tmp >> 8); 1806 value[2] = (u8) (tmp >> 16); 1807 value[3] = (u8) (tmp >> 24); 1808 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1809 PWR_CTL_EN, value, 4); 1810 msleep(PWR_SLEEP_INTERVAL); 1811 } 1812 1813 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || 1814 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { 1815 /* tuner path to channel 1 from port 3 */ 1816 cx231xx_enable_i2c_for_tuner(dev, I2C_3); 1817 1818 if (dev->cx231xx_reset_analog_tuner) 1819 dev->cx231xx_reset_analog_tuner(dev); 1820 } 1821 break; 1822 1823 case POLARIS_AVMODE_DIGITAL: 1824 if (!(tmp & PWR_TUNER_EN)) { 1825 tmp |= (PWR_TUNER_EN); 1826 value[0] = (u8) tmp; 1827 value[1] = (u8) (tmp >> 8); 1828 value[2] = (u8) (tmp >> 16); 1829 value[3] = (u8) (tmp >> 24); 1830 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1831 PWR_CTL_EN, value, 4); 1832 msleep(PWR_SLEEP_INTERVAL); 1833 } 1834 if (!(tmp & PWR_AV_EN)) { 1835 tmp |= PWR_AV_EN; 1836 value[0] = (u8) tmp; 1837 value[1] = (u8) (tmp >> 8); 1838 value[2] = (u8) (tmp >> 16); 1839 value[3] = (u8) (tmp >> 24); 1840 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1841 PWR_CTL_EN, value, 4); 1842 msleep(PWR_SLEEP_INTERVAL); 1843 } 1844 if (!(tmp & PWR_ISO_EN)) { 1845 tmp |= PWR_ISO_EN; 1846 value[0] = (u8) tmp; 1847 value[1] = (u8) (tmp >> 8); 1848 value[2] = (u8) (tmp >> 16); 1849 value[3] = (u8) (tmp >> 24); 1850 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1851 PWR_CTL_EN, value, 4); 1852 msleep(PWR_SLEEP_INTERVAL); 1853 } 1854 1855 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN; 1856 value[0] = (u8) tmp; 1857 value[1] = (u8) (tmp >> 8); 1858 value[2] = (u8) (tmp >> 16); 1859 value[3] = (u8) (tmp >> 24); 1860 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1861 PWR_CTL_EN, value, 4); 1862 msleep(PWR_SLEEP_INTERVAL); 1863 1864 if (!(tmp & PWR_DEMOD_EN)) { 1865 tmp |= PWR_DEMOD_EN; 1866 value[0] = (u8) tmp; 1867 value[1] = (u8) (tmp >> 8); 1868 value[2] = (u8) (tmp >> 16); 1869 value[3] = (u8) (tmp >> 24); 1870 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1871 PWR_CTL_EN, value, 4); 1872 msleep(PWR_SLEEP_INTERVAL); 1873 } 1874 1875 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || 1876 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { 1877 /* tuner path to channel 1 from port 3 */ 1878 cx231xx_enable_i2c_for_tuner(dev, I2C_3); 1879 1880 if (dev->cx231xx_reset_analog_tuner) 1881 dev->cx231xx_reset_analog_tuner(dev); 1882 } 1883 break; 1884 1885 default: 1886 break; 1887 } 1888 1889 msleep(PWR_SLEEP_INTERVAL); 1890 1891 /* For power saving, only enable Pwr_resetout_n 1892 when digital TV is selected. */ 1893 if (mode == POLARIS_AVMODE_DIGITAL) { 1894 tmp |= PWR_RESETOUT_EN; 1895 value[0] = (u8) tmp; 1896 value[1] = (u8) (tmp >> 8); 1897 value[2] = (u8) (tmp >> 16); 1898 value[3] = (u8) (tmp >> 24); 1899 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1900 PWR_CTL_EN, value, 4); 1901 msleep(PWR_SLEEP_INTERVAL); 1902 } 1903 1904 /* update power control for afe */ 1905 status = cx231xx_afe_update_power_control(dev, mode); 1906 1907 /* update power control for i2s_blk */ 1908 status = cx231xx_i2s_blk_update_power_control(dev, mode); 1909 1910 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 1911 4); 1912 cx231xx_info(" The data of PWR_CTL_EN register 0x74" 1913 "=0x%0x,0x%0x,0x%0x,0x%0x\n", 1914 value[0], value[1], value[2], value[3]); 1915 1916 return status; 1917} 1918 1919int cx231xx_power_suspend(struct cx231xx *dev) 1920{ 1921 u8 value[4] = { 0, 0, 0, 0 }; 1922 u32 tmp = 0; 1923 int status = 0; 1924 1925 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 1926 value, 4); 1927 if (status > 0) 1928 return status; 1929 1930 tmp = *((u32 *) value); 1931 tmp &= (~PWR_MODE_MASK); 1932 1933 value[0] = (u8) tmp; 1934 value[1] = (u8) (tmp >> 8); 1935 value[2] = (u8) (tmp >> 16); 1936 value[3] = (u8) (tmp >> 24); 1937 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 1938 value, 4); 1939 1940 return status; 1941} 1942 1943/****************************************************************************** 1944 * S T R E A M C O N T R O L functions * 1945 ******************************************************************************/ 1946int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 1947{ 1948 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 1949 u32 tmp = 0; 1950 int status = 0; 1951 1952 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); 1953 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 1954 value, 4); 1955 if (status < 0) 1956 return status; 1957 1958 tmp = *((u32 *) value); 1959 tmp |= ep_mask; 1960 value[0] = (u8) tmp; 1961 value[1] = (u8) (tmp >> 8); 1962 value[2] = (u8) (tmp >> 16); 1963 value[3] = (u8) (tmp >> 24); 1964 1965 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 1966 value, 4); 1967 1968 return status; 1969} 1970 1971int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 1972{ 1973 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 1974 u32 tmp = 0; 1975 int status = 0; 1976 1977 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); 1978 status = 1979 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 1980 if (status < 0) 1981 return status; 1982 1983 tmp = *((u32 *) value); 1984 tmp &= (~ep_mask); 1985 value[0] = (u8) tmp; 1986 value[1] = (u8) (tmp >> 8); 1987 value[2] = (u8) (tmp >> 16); 1988 value[3] = (u8) (tmp >> 24); 1989 1990 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 1991 value, 4); 1992 1993 return status; 1994} 1995 1996int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 1997{ 1998 int status = 0; 1999 2000 if (dev->udev->speed == USB_SPEED_HIGH) { 2001 switch (media_type) { 2002 case 81: /* audio */ 2003 cx231xx_info("%s: Audio enter HANC\n", __func__); 2004 status = 2005 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 2006 break; 2007 2008 case 2: /* vbi */ 2009 cx231xx_info("%s: set vanc registers\n", __func__); 2010 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 2011 break; 2012 2013 case 3: /* sliced cc */ 2014 cx231xx_info("%s: set hanc registers\n", __func__); 2015 status = 2016 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 2017 break; 2018 2019 case 0: /* video */ 2020 cx231xx_info("%s: set video registers\n", __func__); 2021 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2022 break; 2023 2024 case 4: /* ts1 */ 2025 cx231xx_info("%s: set ts1 registers\n", __func__); 2026 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2027 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2028 break; 2029 case 6: /* ts1 parallel mode */ 2030 cx231xx_info("%s: set ts1 parrallel mode registers\n", 2031 __func__); 2032 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2033 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2034 break; 2035 } 2036 } else { 2037 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2038 } 2039 2040 return status; 2041} 2042 2043int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 2044{ 2045 int rc = -1; 2046 u32 ep_mask = -1; 2047 struct pcb_config *pcb_config; 2048 2049 /* get EP for media type */ 2050 pcb_config = (struct pcb_config *)&dev->current_pcb_config; 2051 2052 if (pcb_config->config_num == 1) { 2053 switch (media_type) { 2054 case 0: /* Video */ 2055 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 2056 break; 2057 case 1: /* Audio */ 2058 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 2059 break; 2060 case 2: /* Vbi */ 2061 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 2062 break; 2063 case 3: /* Sliced_cc */ 2064 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 2065 break; 2066 case 4: /* ts1 */ 2067 case 6: /* ts1 parallel mode */ 2068 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 2069 break; 2070 case 5: /* ts2 */ 2071 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 2072 break; 2073 } 2074 2075 } else if (pcb_config->config_num > 1) { 2076 switch (media_type) { 2077 case 0: /* Video */ 2078 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 2079 break; 2080 case 1: /* Audio */ 2081 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 2082 break; 2083 case 2: /* Vbi */ 2084 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 2085 break; 2086 case 3: /* Sliced_cc */ 2087 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 2088 break; 2089 case 4: /* ts1 */ 2090 case 6: /* ts1 parallel mode */ 2091 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 2092 break; 2093 case 5: /* ts2 */ 2094 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 2095 break; 2096 } 2097 2098 } 2099 2100 if (start) { 2101 rc = cx231xx_initialize_stream_xfer(dev, media_type); 2102 2103 if (rc < 0) 2104 return rc; 2105 2106 /* enable video capture */ 2107 if (ep_mask > 0) 2108 rc = cx231xx_start_stream(dev, ep_mask); 2109 } else { 2110 /* disable video capture */ 2111 if (ep_mask > 0) 2112 rc = cx231xx_stop_stream(dev, ep_mask); 2113 } 2114 2115 if (dev->mode == CX231XX_ANALOG_MODE) 2116 ;/* do any in Analog mode */ 2117 else 2118 ;/* do any in digital mode */ 2119 2120 return rc; 2121} 2122EXPORT_SYMBOL_GPL(cx231xx_capture_start); 2123 2124/***************************************************************************** 2125* G P I O B I T control functions * 2126******************************************************************************/ 2127int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val) 2128{ 2129 int status = 0; 2130 2131 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0); 2132 2133 return status; 2134} 2135 2136int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val) 2137{ 2138 int status = 0; 2139 2140 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1); 2141 2142 return status; 2143} 2144 2145/* 2146* cx231xx_set_gpio_direction 2147* Sets the direction of the GPIO pin to input or output 2148* 2149* Parameters : 2150* pin_number : The GPIO Pin number to program the direction for 2151* from 0 to 31 2152* pin_value : The Direction of the GPIO Pin under reference. 2153* 0 = Input direction 2154* 1 = Output direction 2155*/ 2156int cx231xx_set_gpio_direction(struct cx231xx *dev, 2157 int pin_number, int pin_value) 2158{ 2159 int status = 0; 2160 u32 value = 0; 2161 2162 /* Check for valid pin_number - if 32 , bail out */ 2163 if (pin_number >= 32) 2164 return -EINVAL; 2165 2166 /* input */ 2167 if (pin_value == 0) 2168 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 2169 else 2170 value = dev->gpio_dir | (1 << pin_number); 2171 2172 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val); 2173 2174 /* cache the value for future */ 2175 dev->gpio_dir = value; 2176 2177 return status; 2178} 2179 2180/* 2181* cx231xx_set_gpio_value 2182* Sets the value of the GPIO pin to Logic high or low. The Pin under 2183* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 2184* 2185* Parameters : 2186* pin_number : The GPIO Pin number to program the direction for 2187* pin_value : The value of the GPIO Pin under reference. 2188* 0 = set it to 0 2189* 1 = set it to 1 2190*/ 2191int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 2192{ 2193 int status = 0; 2194 u32 value = 0; 2195 2196 /* Check for valid pin_number - if 0xFF , bail out */ 2197 if (pin_number >= 32) 2198 return -EINVAL; 2199 2200 /* first do a sanity check - if the Pin is not output, make it output */ 2201 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 2202 /* It was in input mode */ 2203 value = dev->gpio_dir | (1 << pin_number); 2204 dev->gpio_dir = value; 2205 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2206 (u8 *) &dev->gpio_val); 2207 value = 0; 2208 } 2209 2210 if (pin_value == 0) 2211 value = dev->gpio_val & (~(1 << pin_number)); 2212 else 2213 value = dev->gpio_val | (1 << pin_number); 2214 2215 /* store the value */ 2216 dev->gpio_val = value; 2217 2218 /* toggle bit0 of GP_IO */ 2219 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2220 2221 return status; 2222} 2223 2224/***************************************************************************** 2225* G P I O I2C related functions * 2226******************************************************************************/ 2227int cx231xx_gpio_i2c_start(struct cx231xx *dev) 2228{ 2229 int status = 0; 2230 2231 /* set SCL to output 1 ; set SDA to output 1 */ 2232 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2233 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2234 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2235 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2236 2237 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2238 if (status < 0) 2239 return -EINVAL; 2240 2241 /* set SCL to output 1; set SDA to output 0 */ 2242 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2243 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2244 2245 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2246 if (status < 0) 2247 return -EINVAL; 2248 2249 /* set SCL to output 0; set SDA to output 0 */ 2250 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2251 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2252 2253 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2254 if (status < 0) 2255 return -EINVAL; 2256 2257 return status; 2258} 2259 2260int cx231xx_gpio_i2c_end(struct cx231xx *dev) 2261{ 2262 int status = 0; 2263 2264 /* set SCL to output 0; set SDA to output 0 */ 2265 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2266 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2267 2268 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2269 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2270 2271 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2272 if (status < 0) 2273 return -EINVAL; 2274 2275 /* set SCL to output 1; set SDA to output 0 */ 2276 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2277 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2278 2279 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2280 if (status < 0) 2281 return -EINVAL; 2282 2283 /* set SCL to input ,release SCL cable control 2284 set SDA to input ,release SDA cable control */ 2285 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2286 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2287 2288 status = 2289 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2290 if (status < 0) 2291 return -EINVAL; 2292 2293 return status; 2294} 2295 2296int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 2297{ 2298 int status = 0; 2299 u8 i; 2300 2301 /* set SCL to output ; set SDA to output */ 2302 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2303 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2304 2305 for (i = 0; i < 8; i++) { 2306 if (((data << i) & 0x80) == 0) { 2307 /* set SCL to output 0; set SDA to output 0 */ 2308 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2309 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2310 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2311 (u8 *)&dev->gpio_val); 2312 2313 /* set SCL to output 1; set SDA to output 0 */ 2314 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2315 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2316 (u8 *)&dev->gpio_val); 2317 2318 /* set SCL to output 0; set SDA to output 0 */ 2319 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2320 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2321 (u8 *)&dev->gpio_val); 2322 } else { 2323 /* set SCL to output 0; set SDA to output 1 */ 2324 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2325 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2326 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2327 (u8 *)&dev->gpio_val); 2328 2329 /* set SCL to output 1; set SDA to output 1 */ 2330 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2331 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2332 (u8 *)&dev->gpio_val); 2333 2334 /* set SCL to output 0; set SDA to output 1 */ 2335 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2336 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2337 (u8 *)&dev->gpio_val); 2338 } 2339 } 2340 return status; 2341} 2342 2343int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf) 2344{ 2345 u8 value = 0; 2346 int status = 0; 2347 u32 gpio_logic_value = 0; 2348 u8 i; 2349 2350 /* read byte */ 2351 for (i = 0; i < 8; i++) { /* send write I2c addr */ 2352 2353 /* set SCL to output 0; set SDA to input */ 2354 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2355 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2356 (u8 *)&dev->gpio_val); 2357 2358 /* set SCL to output 1; set SDA to input */ 2359 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2360 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2361 (u8 *)&dev->gpio_val); 2362 2363 /* get SDA data bit */ 2364 gpio_logic_value = dev->gpio_val; 2365 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2366 (u8 *)&dev->gpio_val); 2367 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 2368 value |= (1 << (8 - i - 1)); 2369 2370 dev->gpio_val = gpio_logic_value; 2371 } 2372 2373 /* set SCL to output 0,finish the read latest SCL signal. 2374 !!!set SDA to input, never to modify SDA direction at 2375 the same times */ 2376 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2377 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2378 2379 /* store the value */ 2380 *buf = value & 0xff; 2381 2382 return status; 2383} 2384 2385int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 2386{ 2387 int status = 0; 2388 u32 gpio_logic_value = 0; 2389 int nCnt = 10; 2390 int nInit = nCnt; 2391 2392 /* clock stretch; set SCL to input; set SDA to input; 2393 get SCL value till SCL = 1 */ 2394 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2395 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2396 2397 gpio_logic_value = dev->gpio_val; 2398 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2399 2400 do { 2401 msleep(2); 2402 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2403 (u8 *)&dev->gpio_val); 2404 nCnt--; 2405 } while (((dev->gpio_val & 2406 (1 << dev->board.tuner_scl_gpio)) == 0) && 2407 (nCnt > 0)); 2408 2409 if (nCnt == 0) 2410 cx231xx_info("No ACK after %d msec -GPIO I2C failed!", 2411 nInit * 10); 2412 2413 /* 2414 * readAck 2415 * through clock stretch, slave has given a SCL signal, 2416 * so the SDA data can be directly read. 2417 */ 2418 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2419 2420 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 2421 dev->gpio_val = gpio_logic_value; 2422 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2423 status = 0; 2424 } else { 2425 dev->gpio_val = gpio_logic_value; 2426 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 2427 } 2428 2429 /* read SDA end, set the SCL to output 0, after this operation, 2430 SDA direction can be changed. */ 2431 dev->gpio_val = gpio_logic_value; 2432 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 2433 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2434 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2435 2436 return status; 2437} 2438 2439int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 2440{ 2441 int status = 0; 2442 2443 /* set SDA to ouput */ 2444 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2445 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2446 2447 /* set SCL = 0 (output); set SDA = 0 (output) */ 2448 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2449 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2450 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2451 2452 /* set SCL = 1 (output); set SDA = 0 (output) */ 2453 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2454 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2455 2456 /* set SCL = 0 (output); set SDA = 0 (output) */ 2457 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2458 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2459 2460 /* set SDA to input,and then the slave will read data from SDA. */ 2461 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2462 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2463 2464 return status; 2465} 2466 2467int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 2468{ 2469 int status = 0; 2470 2471 /* set scl to output ; set sda to input */ 2472 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2473 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2474 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2475 2476 /* set scl to output 0; set sda to input */ 2477 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2478 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2479 2480 /* set scl to output 1; set sda to input */ 2481 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2482 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2483 2484 return status; 2485} 2486 2487/***************************************************************************** 2488* G P I O I2C related functions * 2489******************************************************************************/ 2490/* cx231xx_gpio_i2c_read 2491 * Function to read data from gpio based I2C interface 2492 */ 2493int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len) 2494{ 2495 int status = 0; 2496 int i = 0; 2497 2498 /* get the lock */ 2499 mutex_lock(&dev->gpio_i2c_lock); 2500 2501 /* start */ 2502 status = cx231xx_gpio_i2c_start(dev); 2503 2504 /* write dev_addr */ 2505 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 2506 2507 /* readAck */ 2508 status = cx231xx_gpio_i2c_read_ack(dev); 2509 2510 /* read data */ 2511 for (i = 0; i < len; i++) { 2512 /* read data */ 2513 buf[i] = 0; 2514 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 2515 2516 if ((i + 1) != len) { 2517 /* only do write ack if we more length */ 2518 status = cx231xx_gpio_i2c_write_ack(dev); 2519 } 2520 } 2521 2522 /* write NAK - inform reads are complete */ 2523 status = cx231xx_gpio_i2c_write_nak(dev); 2524 2525 /* write end */ 2526 status = cx231xx_gpio_i2c_end(dev); 2527 2528 /* release the lock */ 2529 mutex_unlock(&dev->gpio_i2c_lock); 2530 2531 return status; 2532} 2533 2534/* cx231xx_gpio_i2c_write 2535 * Function to write data to gpio based I2C interface 2536 */ 2537int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len) 2538{ 2539 int status = 0; 2540 int i = 0; 2541 2542 /* get the lock */ 2543 mutex_lock(&dev->gpio_i2c_lock); 2544 2545 /* start */ 2546 status = cx231xx_gpio_i2c_start(dev); 2547 2548 /* write dev_addr */ 2549 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 2550 2551 /* read Ack */ 2552 status = cx231xx_gpio_i2c_read_ack(dev); 2553 2554 for (i = 0; i < len; i++) { 2555 /* Write data */ 2556 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]); 2557 2558 /* read Ack */ 2559 status = cx231xx_gpio_i2c_read_ack(dev); 2560 } 2561 2562 /* write End */ 2563 status = cx231xx_gpio_i2c_end(dev); 2564 2565 /* release the lock */ 2566 mutex_unlock(&dev->gpio_i2c_lock); 2567 2568 return 0; 2569} 2570