1/* 2 NXP TDA10048HN DVB OFDM demodulator driver 3 4 Copyright (C) 2009 Steven Toth <stoth@kernellabs.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20*/ 21 22#include <linux/kernel.h> 23#include <linux/init.h> 24#include <linux/module.h> 25#include <linux/string.h> 26#include <linux/slab.h> 27#include <linux/delay.h> 28#include <linux/math64.h> 29#include <asm/div64.h> 30#include "dvb_frontend.h" 31#include "dvb_math.h" 32#include "tda10048.h" 33 34#define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw" 35#define TDA10048_DEFAULT_FIRMWARE_SIZE 24878 36 37/* Register name definitions */ 38#define TDA10048_IDENTITY 0x00 39#define TDA10048_VERSION 0x01 40#define TDA10048_DSP_CODE_CPT 0x0C 41#define TDA10048_DSP_CODE_IN 0x0E 42#define TDA10048_IN_CONF1 0x10 43#define TDA10048_IN_CONF2 0x11 44#define TDA10048_IN_CONF3 0x12 45#define TDA10048_OUT_CONF1 0x14 46#define TDA10048_OUT_CONF2 0x15 47#define TDA10048_OUT_CONF3 0x16 48#define TDA10048_AUTO 0x18 49#define TDA10048_SYNC_STATUS 0x1A 50#define TDA10048_CONF_C4_1 0x1E 51#define TDA10048_CONF_C4_2 0x1F 52#define TDA10048_CODE_IN_RAM 0x20 53#define TDA10048_CHANNEL_INFO1_R 0x22 54#define TDA10048_CHANNEL_INFO2_R 0x23 55#define TDA10048_CHANNEL_INFO1 0x24 56#define TDA10048_CHANNEL_INFO2 0x25 57#define TDA10048_TIME_ERROR_R 0x26 58#define TDA10048_TIME_ERROR 0x27 59#define TDA10048_FREQ_ERROR_LSB_R 0x28 60#define TDA10048_FREQ_ERROR_MSB_R 0x29 61#define TDA10048_FREQ_ERROR_LSB 0x2A 62#define TDA10048_FREQ_ERROR_MSB 0x2B 63#define TDA10048_IT_SEL 0x30 64#define TDA10048_IT_STAT 0x32 65#define TDA10048_DSP_AD_LSB 0x3C 66#define TDA10048_DSP_AD_MSB 0x3D 67#define TDA10048_DSP_REG_LSB 0x3E 68#define TDA10048_DSP_REG_MSB 0x3F 69#define TDA10048_CONF_TRISTATE1 0x44 70#define TDA10048_CONF_TRISTATE2 0x45 71#define TDA10048_CONF_POLARITY 0x46 72#define TDA10048_GPIO_SP_DS0 0x48 73#define TDA10048_GPIO_SP_DS1 0x49 74#define TDA10048_GPIO_SP_DS2 0x4A 75#define TDA10048_GPIO_SP_DS3 0x4B 76#define TDA10048_GPIO_OUT_SEL 0x4C 77#define TDA10048_GPIO_SELECT 0x4D 78#define TDA10048_IC_MODE 0x4E 79#define TDA10048_CONF_XO 0x50 80#define TDA10048_CONF_PLL1 0x51 81#define TDA10048_CONF_PLL2 0x52 82#define TDA10048_CONF_PLL3 0x53 83#define TDA10048_CONF_ADC 0x54 84#define TDA10048_CONF_ADC_2 0x55 85#define TDA10048_CONF_C1_1 0x60 86#define TDA10048_CONF_C1_3 0x62 87#define TDA10048_AGC_CONF 0x70 88#define TDA10048_AGC_THRESHOLD_LSB 0x72 89#define TDA10048_AGC_THRESHOLD_MSB 0x73 90#define TDA10048_AGC_RENORM 0x74 91#define TDA10048_AGC_GAINS 0x76 92#define TDA10048_AGC_TUN_MIN 0x78 93#define TDA10048_AGC_TUN_MAX 0x79 94#define TDA10048_AGC_IF_MIN 0x7A 95#define TDA10048_AGC_IF_MAX 0x7B 96#define TDA10048_AGC_TUN_LEVEL 0x7E 97#define TDA10048_AGC_IF_LEVEL 0x7F 98#define TDA10048_DIG_AGC_LEVEL 0x81 99#define TDA10048_FREQ_PHY2_LSB 0x86 100#define TDA10048_FREQ_PHY2_MSB 0x87 101#define TDA10048_TIME_INVWREF_LSB 0x88 102#define TDA10048_TIME_INVWREF_MSB 0x89 103#define TDA10048_TIME_WREF_LSB 0x8A 104#define TDA10048_TIME_WREF_MID1 0x8B 105#define TDA10048_TIME_WREF_MID2 0x8C 106#define TDA10048_TIME_WREF_MSB 0x8D 107#define TDA10048_NP_OUT 0xA2 108#define TDA10048_CELL_ID_LSB 0xA4 109#define TDA10048_CELL_ID_MSB 0xA5 110#define TDA10048_EXTTPS_ODD 0xAA 111#define TDA10048_EXTTPS_EVEN 0xAB 112#define TDA10048_TPS_LENGTH 0xAC 113#define TDA10048_FREE_REG_1 0xB2 114#define TDA10048_FREE_REG_2 0xB3 115#define TDA10048_CONF_C3_1 0xC0 116#define TDA10048_CVBER_CTRL 0xC2 117#define TDA10048_CBER_NMAX_LSB 0xC4 118#define TDA10048_CBER_NMAX_MSB 0xC5 119#define TDA10048_CBER_LSB 0xC6 120#define TDA10048_CBER_MSB 0xC7 121#define TDA10048_VBER_LSB 0xC8 122#define TDA10048_VBER_MID 0xC9 123#define TDA10048_VBER_MSB 0xCA 124#define TDA10048_CVBER_LUT 0xCC 125#define TDA10048_UNCOR_CTRL 0xCD 126#define TDA10048_UNCOR_CPT_LSB 0xCE 127#define TDA10048_UNCOR_CPT_MSB 0xCF 128#define TDA10048_SOFT_IT_C3 0xD6 129#define TDA10048_CONF_TS2 0xE0 130#define TDA10048_CONF_TS1 0xE1 131 132static unsigned int debug; 133 134#define dprintk(level, fmt, arg...)\ 135 do { if (debug >= level)\ 136 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\ 137 } while (0) 138 139struct tda10048_state { 140 141 struct i2c_adapter *i2c; 142 143 /* We'll cache and update the attach config settings */ 144 struct tda10048_config config; 145 struct dvb_frontend frontend; 146 147 int fwloaded; 148 149 u32 freq_if_hz; 150 u32 xtal_hz; 151 u32 pll_mfactor; 152 u32 pll_nfactor; 153 u32 pll_pfactor; 154 u32 sample_freq; 155 156 enum fe_bandwidth bandwidth; 157}; 158 159static struct init_tab { 160 u8 reg; 161 u16 data; 162} init_tab[] = { 163 { TDA10048_CONF_PLL1, 0x08 }, 164 { TDA10048_CONF_ADC_2, 0x00 }, 165 { TDA10048_CONF_C4_1, 0x00 }, 166 { TDA10048_CONF_PLL1, 0x0f }, 167 { TDA10048_CONF_PLL2, 0x0a }, 168 { TDA10048_CONF_PLL3, 0x43 }, 169 { TDA10048_FREQ_PHY2_LSB, 0x02 }, 170 { TDA10048_FREQ_PHY2_MSB, 0x0a }, 171 { TDA10048_TIME_WREF_LSB, 0xbd }, 172 { TDA10048_TIME_WREF_MID1, 0xe4 }, 173 { TDA10048_TIME_WREF_MID2, 0xa8 }, 174 { TDA10048_TIME_WREF_MSB, 0x02 }, 175 { TDA10048_TIME_INVWREF_LSB, 0x04 }, 176 { TDA10048_TIME_INVWREF_MSB, 0x06 }, 177 { TDA10048_CONF_C4_1, 0x00 }, 178 { TDA10048_CONF_C1_1, 0xa8 }, 179 { TDA10048_AGC_CONF, 0x16 }, 180 { TDA10048_CONF_C1_3, 0x0b }, 181 { TDA10048_AGC_TUN_MIN, 0x00 }, 182 { TDA10048_AGC_TUN_MAX, 0xff }, 183 { TDA10048_AGC_IF_MIN, 0x00 }, 184 { TDA10048_AGC_IF_MAX, 0xff }, 185 { TDA10048_AGC_THRESHOLD_MSB, 0x00 }, 186 { TDA10048_AGC_THRESHOLD_LSB, 0x70 }, 187 { TDA10048_CVBER_CTRL, 0x38 }, 188 { TDA10048_AGC_GAINS, 0x12 }, 189 { TDA10048_CONF_XO, 0x00 }, 190 { TDA10048_CONF_TS1, 0x07 }, 191 { TDA10048_IC_MODE, 0x00 }, 192 { TDA10048_CONF_TS2, 0xc0 }, 193 { TDA10048_CONF_TRISTATE1, 0x21 }, 194 { TDA10048_CONF_TRISTATE2, 0x00 }, 195 { TDA10048_CONF_POLARITY, 0x00 }, 196 { TDA10048_CONF_C4_2, 0x04 }, 197 { TDA10048_CONF_ADC, 0x60 }, 198 { TDA10048_CONF_ADC_2, 0x10 }, 199 { TDA10048_CONF_ADC, 0x60 }, 200 { TDA10048_CONF_ADC_2, 0x00 }, 201 { TDA10048_CONF_C1_1, 0xa8 }, 202 { TDA10048_UNCOR_CTRL, 0x00 }, 203 { TDA10048_CONF_C4_2, 0x04 }, 204}; 205 206static struct pll_tab { 207 u32 clk_freq_khz; 208 u32 if_freq_khz; 209 u8 m, n, p; 210} pll_tab[] = { 211 { TDA10048_CLK_4000, TDA10048_IF_36130, 10, 0, 0 }, 212 { TDA10048_CLK_16000, TDA10048_IF_3300, 10, 3, 0 }, 213 { TDA10048_CLK_16000, TDA10048_IF_3500, 10, 3, 0 }, 214 { TDA10048_CLK_16000, TDA10048_IF_3800, 10, 3, 0 }, 215 { TDA10048_CLK_16000, TDA10048_IF_4000, 10, 3, 0 }, 216 { TDA10048_CLK_16000, TDA10048_IF_4300, 10, 3, 0 }, 217 { TDA10048_CLK_16000, TDA10048_IF_36130, 10, 3, 0 }, 218}; 219 220static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data) 221{ 222 struct tda10048_config *config = &state->config; 223 int ret; 224 u8 buf[] = { reg, data }; 225 struct i2c_msg msg = { 226 .addr = config->demod_address, 227 .flags = 0, .buf = buf, .len = 2 }; 228 229 dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data); 230 231 ret = i2c_transfer(state->i2c, &msg, 1); 232 233 if (ret != 1) 234 printk("%s: writereg error (ret == %i)\n", __func__, ret); 235 236 return (ret != 1) ? -1 : 0; 237} 238 239static u8 tda10048_readreg(struct tda10048_state *state, u8 reg) 240{ 241 struct tda10048_config *config = &state->config; 242 int ret; 243 u8 b0[] = { reg }; 244 u8 b1[] = { 0 }; 245 struct i2c_msg msg[] = { 246 { .addr = config->demod_address, 247 .flags = 0, .buf = b0, .len = 1 }, 248 { .addr = config->demod_address, 249 .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 250 251 dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg); 252 253 ret = i2c_transfer(state->i2c, msg, 2); 254 255 if (ret != 2) 256 printk(KERN_ERR "%s: readreg error (ret == %i)\n", 257 __func__, ret); 258 259 return b1[0]; 260} 261 262static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg, 263 const u8 *data, u16 len) 264{ 265 struct tda10048_config *config = &state->config; 266 int ret = -EREMOTEIO; 267 struct i2c_msg msg; 268 u8 *buf; 269 270 dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len); 271 272 buf = kmalloc(len + 1, GFP_KERNEL); 273 if (buf == NULL) { 274 ret = -ENOMEM; 275 goto error; 276 } 277 278 *buf = reg; 279 memcpy(buf + 1, data, len); 280 281 msg.addr = config->demod_address; 282 msg.flags = 0; 283 msg.buf = buf; 284 msg.len = len + 1; 285 286 dprintk(2, "%s(): write len = %d\n", 287 __func__, msg.len); 288 289 ret = i2c_transfer(state->i2c, &msg, 1); 290 if (ret != 1) { 291 printk(KERN_ERR "%s(): writereg error err %i\n", 292 __func__, ret); 293 ret = -EREMOTEIO; 294 } 295 296error: 297 kfree(buf); 298 299 return ret; 300} 301 302static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz, 303 u32 if_hz) 304{ 305 struct tda10048_state *state = fe->demodulator_priv; 306 u64 t; 307 308 dprintk(1, "%s()\n", __func__); 309 310 if (sample_freq_hz == 0) 311 return -EINVAL; 312 313 if (if_hz < (sample_freq_hz / 2)) { 314 /* PHY2 = (if2/fs) * 2^15 */ 315 t = if_hz; 316 t *= 10; 317 t *= 32768; 318 do_div(t, sample_freq_hz); 319 t += 5; 320 do_div(t, 10); 321 } else { 322 /* PHY2 = ((IF1-fs)/fs) * 2^15 */ 323 t = sample_freq_hz - if_hz; 324 t *= 10; 325 t *= 32768; 326 do_div(t, sample_freq_hz); 327 t += 5; 328 do_div(t, 10); 329 t = ~t + 1; 330 } 331 332 tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t); 333 tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8)); 334 335 return 0; 336} 337 338static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz, 339 u32 bw) 340{ 341 struct tda10048_state *state = fe->demodulator_priv; 342 u64 t, z; 343 u32 b = 8000000; 344 345 dprintk(1, "%s()\n", __func__); 346 347 if (sample_freq_hz == 0) 348 return -EINVAL; 349 350 if (bw == BANDWIDTH_6_MHZ) 351 b = 6000000; 352 else 353 if (bw == BANDWIDTH_7_MHZ) 354 b = 7000000; 355 356 /* WREF = (B / (7 * fs)) * 2^31 */ 357 t = b * 10; 358 /* avoid warning: this decimal constant is unsigned only in ISO C90 */ 359 /* t *= 2147483648 on 32bit platforms */ 360 t *= (2048 * 1024); 361 t *= 1024; 362 z = 7 * sample_freq_hz; 363 do_div(t, z); 364 t += 5; 365 do_div(t, 10); 366 367 tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t); 368 tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8)); 369 tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16)); 370 tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24)); 371 372 return 0; 373} 374 375static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz, 376 u32 bw) 377{ 378 struct tda10048_state *state = fe->demodulator_priv; 379 u64 t; 380 u32 b = 8000000; 381 382 dprintk(1, "%s()\n", __func__); 383 384 if (sample_freq_hz == 0) 385 return -EINVAL; 386 387 if (bw == BANDWIDTH_6_MHZ) 388 b = 6000000; 389 else 390 if (bw == BANDWIDTH_7_MHZ) 391 b = 7000000; 392 393 /* INVWREF = ((7 * fs) / B) * 2^5 */ 394 t = sample_freq_hz; 395 t *= 7; 396 t *= 32; 397 t *= 10; 398 do_div(t, b); 399 t += 5; 400 do_div(t, 10); 401 402 tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t); 403 tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8)); 404 405 return 0; 406} 407 408static int tda10048_set_bandwidth(struct dvb_frontend *fe, 409 enum fe_bandwidth bw) 410{ 411 struct tda10048_state *state = fe->demodulator_priv; 412 dprintk(1, "%s(bw=%d)\n", __func__, bw); 413 414 /* Bandwidth setting may need to be adjusted */ 415 switch (bw) { 416 case BANDWIDTH_6_MHZ: 417 case BANDWIDTH_7_MHZ: 418 case BANDWIDTH_8_MHZ: 419 tda10048_set_wref(fe, state->sample_freq, bw); 420 tda10048_set_invwref(fe, state->sample_freq, bw); 421 break; 422 default: 423 printk(KERN_ERR "%s() invalid bandwidth\n", __func__); 424 return -EINVAL; 425 } 426 427 state->bandwidth = bw; 428 429 return 0; 430} 431 432static int tda10048_set_if(struct dvb_frontend *fe, enum fe_bandwidth bw) 433{ 434 struct tda10048_state *state = fe->demodulator_priv; 435 struct tda10048_config *config = &state->config; 436 int i; 437 u32 if_freq_khz; 438 439 dprintk(1, "%s(bw = %d)\n", __func__, bw); 440 441 /* based on target bandwidth and clk we calculate pll factors */ 442 switch (bw) { 443 case BANDWIDTH_6_MHZ: 444 if_freq_khz = config->dtv6_if_freq_khz; 445 break; 446 case BANDWIDTH_7_MHZ: 447 if_freq_khz = config->dtv7_if_freq_khz; 448 break; 449 case BANDWIDTH_8_MHZ: 450 if_freq_khz = config->dtv8_if_freq_khz; 451 break; 452 default: 453 printk(KERN_ERR "%s() no default\n", __func__); 454 return -EINVAL; 455 } 456 457 for (i = 0; i < ARRAY_SIZE(pll_tab); i++) { 458 if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) && 459 (pll_tab[i].if_freq_khz == if_freq_khz)) { 460 461 state->freq_if_hz = pll_tab[i].if_freq_khz * 1000; 462 state->xtal_hz = pll_tab[i].clk_freq_khz * 1000; 463 state->pll_mfactor = pll_tab[i].m; 464 state->pll_nfactor = pll_tab[i].n; 465 state->pll_pfactor = pll_tab[i].p; 466 break; 467 } 468 } 469 if (i == ARRAY_SIZE(pll_tab)) { 470 printk(KERN_ERR "%s() Incorrect attach settings\n", 471 __func__); 472 return -EINVAL; 473 } 474 475 dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz); 476 dprintk(1, "- xtal_hz = %d\n", state->xtal_hz); 477 dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor); 478 dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor); 479 dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor); 480 481 /* Calculate the sample frequency */ 482 state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45); 483 state->sample_freq /= (state->pll_nfactor + 1); 484 state->sample_freq /= (state->pll_pfactor + 4); 485 dprintk(1, "- sample_freq = %d\n", state->sample_freq); 486 487 /* Update the I/F */ 488 tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz); 489 490 return 0; 491} 492 493static int tda10048_firmware_upload(struct dvb_frontend *fe) 494{ 495 struct tda10048_state *state = fe->demodulator_priv; 496 struct tda10048_config *config = &state->config; 497 const struct firmware *fw; 498 int ret; 499 int pos = 0; 500 int cnt; 501 u8 wlen = config->fwbulkwritelen; 502 503 if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50)) 504 wlen = TDA10048_BULKWRITE_200; 505 506 /* request the firmware, this will block and timeout */ 507 printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n", 508 __func__, 509 TDA10048_DEFAULT_FIRMWARE); 510 511 ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE, 512 state->i2c->dev.parent); 513 if (ret) { 514 printk(KERN_ERR "%s: Upload failed. (file not found?)\n", 515 __func__); 516 return -EIO; 517 } else { 518 printk(KERN_INFO "%s: firmware read %Zu bytes.\n", 519 __func__, 520 fw->size); 521 ret = 0; 522 } 523 524 if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) { 525 printk(KERN_ERR "%s: firmware incorrect size\n", __func__); 526 ret = -EIO; 527 } else { 528 printk(KERN_INFO "%s: firmware uploading\n", __func__); 529 530 /* Soft reset */ 531 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 532 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 533 & 0xfe); 534 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 535 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 536 | 0x01); 537 538 /* Put the demod into host download mode */ 539 tda10048_writereg(state, TDA10048_CONF_C4_1, 540 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9); 541 542 /* Boot the DSP */ 543 tda10048_writereg(state, TDA10048_CONF_C4_1, 544 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08); 545 546 /* Prepare for download */ 547 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0); 548 549 /* Download the firmware payload */ 550 while (pos < fw->size) { 551 552 if ((fw->size - pos) > wlen) 553 cnt = wlen; 554 else 555 cnt = fw->size - pos; 556 557 tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN, 558 &fw->data[pos], cnt); 559 560 pos += cnt; 561 } 562 563 ret = -EIO; 564 /* Wait up to 250ms for the DSP to boot */ 565 for (cnt = 0; cnt < 250 ; cnt += 10) { 566 567 msleep(10); 568 569 if (tda10048_readreg(state, TDA10048_SYNC_STATUS) 570 & 0x40) { 571 ret = 0; 572 break; 573 } 574 } 575 } 576 577 release_firmware(fw); 578 579 if (ret == 0) { 580 printk(KERN_INFO "%s: firmware uploaded\n", __func__); 581 state->fwloaded = 1; 582 } else 583 printk(KERN_ERR "%s: firmware upload failed\n", __func__); 584 585 return ret; 586} 587 588static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion) 589{ 590 struct tda10048_state *state = fe->demodulator_priv; 591 592 dprintk(1, "%s(%d)\n", __func__, inversion); 593 594 if (inversion == TDA10048_INVERSION_ON) 595 tda10048_writereg(state, TDA10048_CONF_C1_1, 596 tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20); 597 else 598 tda10048_writereg(state, TDA10048_CONF_C1_1, 599 tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf); 600 601 return 0; 602} 603 604/* Retrieve the demod settings */ 605static int tda10048_get_tps(struct tda10048_state *state, 606 struct dvb_ofdm_parameters *p) 607{ 608 u8 val; 609 610 /* Make sure the TPS regs are valid */ 611 if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01)) 612 return -EAGAIN; 613 614 val = tda10048_readreg(state, TDA10048_OUT_CONF2); 615 switch ((val & 0x60) >> 5) { 616 case 0: 617 p->constellation = QPSK; 618 break; 619 case 1: 620 p->constellation = QAM_16; 621 break; 622 case 2: 623 p->constellation = QAM_64; 624 break; 625 } 626 switch ((val & 0x18) >> 3) { 627 case 0: 628 p->hierarchy_information = HIERARCHY_NONE; 629 break; 630 case 1: 631 p->hierarchy_information = HIERARCHY_1; 632 break; 633 case 2: 634 p->hierarchy_information = HIERARCHY_2; 635 break; 636 case 3: 637 p->hierarchy_information = HIERARCHY_4; 638 break; 639 } 640 switch (val & 0x07) { 641 case 0: 642 p->code_rate_HP = FEC_1_2; 643 break; 644 case 1: 645 p->code_rate_HP = FEC_2_3; 646 break; 647 case 2: 648 p->code_rate_HP = FEC_3_4; 649 break; 650 case 3: 651 p->code_rate_HP = FEC_5_6; 652 break; 653 case 4: 654 p->code_rate_HP = FEC_7_8; 655 break; 656 } 657 658 val = tda10048_readreg(state, TDA10048_OUT_CONF3); 659 switch (val & 0x07) { 660 case 0: 661 p->code_rate_LP = FEC_1_2; 662 break; 663 case 1: 664 p->code_rate_LP = FEC_2_3; 665 break; 666 case 2: 667 p->code_rate_LP = FEC_3_4; 668 break; 669 case 3: 670 p->code_rate_LP = FEC_5_6; 671 break; 672 case 4: 673 p->code_rate_LP = FEC_7_8; 674 break; 675 } 676 677 val = tda10048_readreg(state, TDA10048_OUT_CONF1); 678 switch ((val & 0x0c) >> 2) { 679 case 0: 680 p->guard_interval = GUARD_INTERVAL_1_32; 681 break; 682 case 1: 683 p->guard_interval = GUARD_INTERVAL_1_16; 684 break; 685 case 2: 686 p->guard_interval = GUARD_INTERVAL_1_8; 687 break; 688 case 3: 689 p->guard_interval = GUARD_INTERVAL_1_4; 690 break; 691 } 692 switch (val & 0x03) { 693 case 0: 694 p->transmission_mode = TRANSMISSION_MODE_2K; 695 break; 696 case 1: 697 p->transmission_mode = TRANSMISSION_MODE_8K; 698 break; 699 } 700 701 return 0; 702} 703 704static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 705{ 706 struct tda10048_state *state = fe->demodulator_priv; 707 struct tda10048_config *config = &state->config; 708 dprintk(1, "%s(%d)\n", __func__, enable); 709 710 if (config->disable_gate_access) 711 return 0; 712 713 if (enable) 714 return tda10048_writereg(state, TDA10048_CONF_C4_1, 715 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02); 716 else 717 return tda10048_writereg(state, TDA10048_CONF_C4_1, 718 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd); 719} 720 721static int tda10048_output_mode(struct dvb_frontend *fe, int serial) 722{ 723 struct tda10048_state *state = fe->demodulator_priv; 724 dprintk(1, "%s(%d)\n", __func__, serial); 725 726 /* Ensure pins are out of tri-state */ 727 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21); 728 tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00); 729 730 if (serial) { 731 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20); 732 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0); 733 } else { 734 tda10048_writereg(state, TDA10048_IC_MODE, 0x00); 735 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01); 736 } 737 738 return 0; 739} 740 741/* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 742/* TODO: Support manual tuning with specific params */ 743static int tda10048_set_frontend(struct dvb_frontend *fe, 744 struct dvb_frontend_parameters *p) 745{ 746 struct tda10048_state *state = fe->demodulator_priv; 747 748 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency); 749 750 /* Update the I/F pll's if the bandwidth changes */ 751 if (p->u.ofdm.bandwidth != state->bandwidth) { 752 tda10048_set_if(fe, p->u.ofdm.bandwidth); 753 tda10048_set_bandwidth(fe, p->u.ofdm.bandwidth); 754 } 755 756 if (fe->ops.tuner_ops.set_params) { 757 758 if (fe->ops.i2c_gate_ctrl) 759 fe->ops.i2c_gate_ctrl(fe, 1); 760 761 fe->ops.tuner_ops.set_params(fe, p); 762 763 if (fe->ops.i2c_gate_ctrl) 764 fe->ops.i2c_gate_ctrl(fe, 0); 765 } 766 767 /* Enable demod TPS auto detection and begin acquisition */ 768 tda10048_writereg(state, TDA10048_AUTO, 0x57); 769 /* trigger cber and vber acquisition */ 770 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B); 771 772 return 0; 773} 774 775/* Establish sane defaults and load firmware. */ 776static int tda10048_init(struct dvb_frontend *fe) 777{ 778 struct tda10048_state *state = fe->demodulator_priv; 779 struct tda10048_config *config = &state->config; 780 int ret = 0, i; 781 782 dprintk(1, "%s()\n", __func__); 783 784 /* Apply register defaults */ 785 for (i = 0; i < ARRAY_SIZE(init_tab); i++) 786 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data); 787 788 if (state->fwloaded == 0) 789 ret = tda10048_firmware_upload(fe); 790 791 /* Set either serial or parallel */ 792 tda10048_output_mode(fe, config->output_mode); 793 794 /* Set inversion */ 795 tda10048_set_inversion(fe, config->inversion); 796 797 /* Establish default RF values */ 798 tda10048_set_if(fe, BANDWIDTH_8_MHZ); 799 tda10048_set_bandwidth(fe, BANDWIDTH_8_MHZ); 800 801 /* Ensure we leave the gate closed */ 802 tda10048_i2c_gate_ctrl(fe, 0); 803 804 return ret; 805} 806 807static int tda10048_read_status(struct dvb_frontend *fe, fe_status_t *status) 808{ 809 struct tda10048_state *state = fe->demodulator_priv; 810 u8 reg; 811 812 *status = 0; 813 814 reg = tda10048_readreg(state, TDA10048_SYNC_STATUS); 815 816 dprintk(1, "%s() status =0x%02x\n", __func__, reg); 817 818 if (reg & 0x02) 819 *status |= FE_HAS_CARRIER; 820 821 if (reg & 0x04) 822 *status |= FE_HAS_SIGNAL; 823 824 if (reg & 0x08) { 825 *status |= FE_HAS_LOCK; 826 *status |= FE_HAS_VITERBI; 827 *status |= FE_HAS_SYNC; 828 } 829 830 return 0; 831} 832 833static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber) 834{ 835 struct tda10048_state *state = fe->demodulator_priv; 836 static u32 cber_current; 837 u32 cber_nmax; 838 u64 cber_tmp; 839 840 dprintk(1, "%s()\n", __func__); 841 842 /* update cber on interrupt */ 843 if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) { 844 cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 | 845 tda10048_readreg(state, TDA10048_CBER_LSB); 846 cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 | 847 tda10048_readreg(state, TDA10048_CBER_NMAX_LSB); 848 cber_tmp *= 100000000; 849 cber_tmp *= 2; 850 cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1); 851 cber_current = (u32)cber_tmp; 852 /* retrigger cber acquisition */ 853 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39); 854 } 855 /* actual cber is (*ber)/1e8 */ 856 *ber = cber_current; 857 858 return 0; 859} 860 861static int tda10048_read_signal_strength(struct dvb_frontend *fe, 862 u16 *signal_strength) 863{ 864 struct tda10048_state *state = fe->demodulator_priv; 865 u8 v; 866 867 dprintk(1, "%s()\n", __func__); 868 869 *signal_strength = 65535; 870 871 v = tda10048_readreg(state, TDA10048_NP_OUT); 872 if (v > 0) 873 *signal_strength -= (v << 8) | v; 874 875 return 0; 876} 877 878/* SNR lookup table */ 879static struct snr_tab { 880 u8 val; 881 u8 data; 882} snr_tab[] = { 883 { 0, 0 }, 884 { 1, 246 }, 885 { 2, 215 }, 886 { 3, 198 }, 887 { 4, 185 }, 888 { 5, 176 }, 889 { 6, 168 }, 890 { 7, 161 }, 891 { 8, 155 }, 892 { 9, 150 }, 893 { 10, 146 }, 894 { 11, 141 }, 895 { 12, 138 }, 896 { 13, 134 }, 897 { 14, 131 }, 898 { 15, 128 }, 899 { 16, 125 }, 900 { 17, 122 }, 901 { 18, 120 }, 902 { 19, 118 }, 903 { 20, 115 }, 904 { 21, 113 }, 905 { 22, 111 }, 906 { 23, 109 }, 907 { 24, 107 }, 908 { 25, 106 }, 909 { 26, 104 }, 910 { 27, 102 }, 911 { 28, 101 }, 912 { 29, 99 }, 913 { 30, 98 }, 914 { 31, 96 }, 915 { 32, 95 }, 916 { 33, 94 }, 917 { 34, 92 }, 918 { 35, 91 }, 919 { 36, 90 }, 920 { 37, 89 }, 921 { 38, 88 }, 922 { 39, 86 }, 923 { 40, 85 }, 924 { 41, 84 }, 925 { 42, 83 }, 926 { 43, 82 }, 927 { 44, 81 }, 928 { 45, 80 }, 929 { 46, 79 }, 930 { 47, 78 }, 931 { 48, 77 }, 932 { 49, 76 }, 933 { 50, 76 }, 934 { 51, 75 }, 935 { 52, 74 }, 936 { 53, 73 }, 937 { 54, 72 }, 938 { 56, 71 }, 939 { 57, 70 }, 940 { 58, 69 }, 941 { 60, 68 }, 942 { 61, 67 }, 943 { 63, 66 }, 944 { 64, 65 }, 945 { 66, 64 }, 946 { 67, 63 }, 947 { 68, 62 }, 948 { 69, 62 }, 949 { 70, 61 }, 950 { 72, 60 }, 951 { 74, 59 }, 952 { 75, 58 }, 953 { 77, 57 }, 954 { 79, 56 }, 955 { 81, 55 }, 956 { 83, 54 }, 957 { 85, 53 }, 958 { 87, 52 }, 959 { 89, 51 }, 960 { 91, 50 }, 961 { 93, 49 }, 962 { 95, 48 }, 963 { 97, 47 }, 964 { 100, 46 }, 965 { 102, 45 }, 966 { 104, 44 }, 967 { 107, 43 }, 968 { 109, 42 }, 969 { 112, 41 }, 970 { 114, 40 }, 971 { 117, 39 }, 972 { 120, 38 }, 973 { 123, 37 }, 974 { 125, 36 }, 975 { 128, 35 }, 976 { 131, 34 }, 977 { 134, 33 }, 978 { 138, 32 }, 979 { 141, 31 }, 980 { 144, 30 }, 981 { 147, 29 }, 982 { 151, 28 }, 983 { 154, 27 }, 984 { 158, 26 }, 985 { 162, 25 }, 986 { 165, 24 }, 987 { 169, 23 }, 988 { 173, 22 }, 989 { 177, 21 }, 990 { 181, 20 }, 991 { 186, 19 }, 992 { 190, 18 }, 993 { 194, 17 }, 994 { 199, 16 }, 995 { 204, 15 }, 996 { 208, 14 }, 997 { 213, 13 }, 998 { 218, 12 }, 999 { 223, 11 }, 1000 { 229, 10 }, 1001 { 234, 9 }, 1002 { 239, 8 }, 1003 { 245, 7 }, 1004 { 251, 6 }, 1005 { 255, 5 }, 1006}; 1007 1008static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr) 1009{ 1010 struct tda10048_state *state = fe->demodulator_priv; 1011 u8 v; 1012 int i, ret = -EINVAL; 1013 1014 dprintk(1, "%s()\n", __func__); 1015 1016 v = tda10048_readreg(state, TDA10048_NP_OUT); 1017 for (i = 0; i < ARRAY_SIZE(snr_tab); i++) { 1018 if (v <= snr_tab[i].val) { 1019 *snr = snr_tab[i].data; 1020 ret = 0; 1021 break; 1022 } 1023 } 1024 1025 return ret; 1026} 1027 1028static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1029{ 1030 struct tda10048_state *state = fe->demodulator_priv; 1031 1032 dprintk(1, "%s()\n", __func__); 1033 1034 *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 | 1035 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB); 1036 /* clear the uncorrected TS packets counter when saturated */ 1037 if (*ucblocks == 0xFFFF) 1038 tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80); 1039 1040 return 0; 1041} 1042 1043static int tda10048_get_frontend(struct dvb_frontend *fe, 1044 struct dvb_frontend_parameters *p) 1045{ 1046 struct tda10048_state *state = fe->demodulator_priv; 1047 1048 dprintk(1, "%s()\n", __func__); 1049 1050 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1) 1051 & 0x20 ? INVERSION_ON : INVERSION_OFF; 1052 1053 return tda10048_get_tps(state, &p->u.ofdm); 1054} 1055 1056static int tda10048_get_tune_settings(struct dvb_frontend *fe, 1057 struct dvb_frontend_tune_settings *tune) 1058{ 1059 tune->min_delay_ms = 1000; 1060 return 0; 1061} 1062 1063static void tda10048_release(struct dvb_frontend *fe) 1064{ 1065 struct tda10048_state *state = fe->demodulator_priv; 1066 dprintk(1, "%s()\n", __func__); 1067 kfree(state); 1068} 1069 1070static void tda10048_establish_defaults(struct dvb_frontend *fe) 1071{ 1072 struct tda10048_state *state = fe->demodulator_priv; 1073 struct tda10048_config *config = &state->config; 1074 1075 /* Validate/default the config */ 1076 if (config->dtv6_if_freq_khz == 0) { 1077 config->dtv6_if_freq_khz = TDA10048_IF_4300; 1078 printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz " 1079 "is not set (defaulting to %d)\n", 1080 __func__, 1081 config->dtv6_if_freq_khz); 1082 } 1083 1084 if (config->dtv7_if_freq_khz == 0) { 1085 config->dtv7_if_freq_khz = TDA10048_IF_4300; 1086 printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz " 1087 "is not set (defaulting to %d)\n", 1088 __func__, 1089 config->dtv7_if_freq_khz); 1090 } 1091 1092 if (config->dtv8_if_freq_khz == 0) { 1093 config->dtv8_if_freq_khz = TDA10048_IF_4300; 1094 printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz " 1095 "is not set (defaulting to %d)\n", 1096 __func__, 1097 config->dtv8_if_freq_khz); 1098 } 1099 1100 if (config->clk_freq_khz == 0) { 1101 config->clk_freq_khz = TDA10048_CLK_16000; 1102 printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz " 1103 "is not set (defaulting to %d)\n", 1104 __func__, 1105 config->clk_freq_khz); 1106 } 1107} 1108 1109static struct dvb_frontend_ops tda10048_ops; 1110 1111struct dvb_frontend *tda10048_attach(const struct tda10048_config *config, 1112 struct i2c_adapter *i2c) 1113{ 1114 struct tda10048_state *state = NULL; 1115 1116 dprintk(1, "%s()\n", __func__); 1117 1118 /* allocate memory for the internal state */ 1119 state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL); 1120 if (state == NULL) 1121 goto error; 1122 1123 /* setup the state and clone the config */ 1124 memcpy(&state->config, config, sizeof(*config)); 1125 state->i2c = i2c; 1126 state->fwloaded = 0; 1127 state->bandwidth = BANDWIDTH_8_MHZ; 1128 1129 /* check if the demod is present */ 1130 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048) 1131 goto error; 1132 1133 /* create dvb_frontend */ 1134 memcpy(&state->frontend.ops, &tda10048_ops, 1135 sizeof(struct dvb_frontend_ops)); 1136 state->frontend.demodulator_priv = state; 1137 1138 /* Establish any defaults the the user didn't pass */ 1139 tda10048_establish_defaults(&state->frontend); 1140 1141 /* Set the xtal and freq defaults */ 1142 if (tda10048_set_if(&state->frontend, BANDWIDTH_8_MHZ) != 0) 1143 goto error; 1144 1145 /* Default bandwidth */ 1146 if (tda10048_set_bandwidth(&state->frontend, BANDWIDTH_8_MHZ) != 0) 1147 goto error; 1148 1149 /* Leave the gate closed */ 1150 tda10048_i2c_gate_ctrl(&state->frontend, 0); 1151 1152 return &state->frontend; 1153 1154error: 1155 kfree(state); 1156 return NULL; 1157} 1158EXPORT_SYMBOL(tda10048_attach); 1159 1160static struct dvb_frontend_ops tda10048_ops = { 1161 1162 .info = { 1163 .name = "NXP TDA10048HN DVB-T", 1164 .type = FE_OFDM, 1165 .frequency_min = 177000000, 1166 .frequency_max = 858000000, 1167 .frequency_stepsize = 166666, 1168 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1169 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1170 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1171 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | 1172 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER 1173 }, 1174 1175 .release = tda10048_release, 1176 .init = tda10048_init, 1177 .i2c_gate_ctrl = tda10048_i2c_gate_ctrl, 1178 .set_frontend = tda10048_set_frontend, 1179 .get_frontend = tda10048_get_frontend, 1180 .get_tune_settings = tda10048_get_tune_settings, 1181 .read_status = tda10048_read_status, 1182 .read_ber = tda10048_read_ber, 1183 .read_signal_strength = tda10048_read_signal_strength, 1184 .read_snr = tda10048_read_snr, 1185 .read_ucblocks = tda10048_read_ucblocks, 1186}; 1187 1188module_param(debug, int, 0644); 1189MODULE_PARM_DESC(debug, "Enable verbose debug messages"); 1190 1191MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver"); 1192MODULE_AUTHOR("Steven Toth"); 1193MODULE_LICENSE("GPL"); 1194