1/* $Id: hfc_sx.c,v 1.12.2.5 2004/02/11 13:21:33 Exp $ 2 * 3 * level driver for Cologne Chip Designs hfc-s+/sp based cards 4 * 5 * Author Werner Cornelius 6 * based on existing driver for CCD HFC PCI cards 7 * Copyright by Werner Cornelius <werner@isdn4linux.de> 8 * 9 * This software may be used and distributed according to the terms 10 * of the GNU General Public License, incorporated herein by reference. 11 * 12 */ 13 14#include <linux/init.h> 15#include "hisax.h" 16#include "hfc_sx.h" 17#include "isdnl1.h" 18#include <linux/interrupt.h> 19#include <linux/isapnp.h> 20#include <linux/slab.h> 21 22static const char *hfcsx_revision = "$Revision: 1.12.2.5 $"; 23 24/***************************************/ 25/* IRQ-table for CCDs demo board */ 26/* IRQs 6,5,10,11,12,15 are supported */ 27/***************************************/ 28 29/* Teles 16.3c Vendor Id TAG2620, Version 1.0, Vendor version 2.1 30 * 31 * Thanks to Uwe Wisniewski 32 * 33 * ISA-SLOT Signal PIN 34 * B25 IRQ3 92 IRQ_G 35 * B23 IRQ5 94 IRQ_A 36 * B4 IRQ2/9 95 IRQ_B 37 * D3 IRQ10 96 IRQ_C 38 * D4 IRQ11 97 IRQ_D 39 * D5 IRQ12 98 IRQ_E 40 * D6 IRQ15 99 IRQ_F 41 */ 42 43#undef CCD_DEMO_BOARD 44#ifdef CCD_DEMO_BOARD 45static u_char ccd_sp_irqtab[16] = { 46 0,0,0,0,0,2,1,0,0,0,3,4,5,0,0,6 47}; 48#else /* Teles 16.3c */ 49static u_char ccd_sp_irqtab[16] = { 50 0,0,0,7,0,1,0,0,0,2,3,4,5,0,0,6 51}; 52#endif 53#define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */ 54 55#define byteout(addr,val) outb(val,addr) 56#define bytein(addr) inb(addr) 57 58/******************************/ 59/* In/Out access to registers */ 60/******************************/ 61static inline void 62Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) 63{ 64 byteout(cs->hw.hfcsx.base+1, regnum); 65 byteout(cs->hw.hfcsx.base, val); 66} 67 68static inline u_char 69Read_hfc(struct IsdnCardState *cs, u_char regnum) 70{ 71 u_char ret; 72 73 byteout(cs->hw.hfcsx.base+1, regnum); 74 ret = bytein(cs->hw.hfcsx.base); 75 return(ret); 76} 77 78 79/**************************************************/ 80/* select a fifo and remember which one for reuse */ 81/**************************************************/ 82static void 83fifo_select(struct IsdnCardState *cs, u_char fifo) 84{ 85 if (fifo == cs->hw.hfcsx.last_fifo) 86 return; /* still valid */ 87 88 byteout(cs->hw.hfcsx.base+1, HFCSX_FIF_SEL); 89 byteout(cs->hw.hfcsx.base, fifo); 90 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 91 udelay(4); 92 byteout(cs->hw.hfcsx.base, fifo); 93 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 94} 95 96/******************************************/ 97/* reset the specified fifo to defaults. */ 98/* If its a send fifo init needed markers */ 99/******************************************/ 100static void 101reset_fifo(struct IsdnCardState *cs, u_char fifo) 102{ 103 fifo_select(cs, fifo); /* first select the fifo */ 104 byteout(cs->hw.hfcsx.base+1, HFCSX_CIRM); 105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ 106 udelay(1); 107 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 108} 109 110 111/*************************************************************/ 112/* write_fifo writes the skb contents to the desired fifo */ 113/* if no space is available or an error occurs 0 is returned */ 114/* the skb is not released in any way. */ 115/*************************************************************/ 116static int 117write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max) 118{ 119 unsigned short *msp; 120 int fifo_size, count, z1, z2; 121 u_char f_msk, f1, f2, *src; 122 123 if (skb->len <= 0) return(0); 124 if (fifo & 1) return(0); /* no write fifo */ 125 126 fifo_select(cs, fifo); 127 if (fifo & 4) { 128 fifo_size = D_FIFO_SIZE; /* D-channel */ 129 f_msk = MAX_D_FRAMES; 130 if (trans_max) return(0); /* only HDLC */ 131 } 132 else { 133 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ 134 f_msk = MAX_B_FRAMES; 135 } 136 137 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); 138 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); 139 140 /* Check for transparent mode */ 141 if (trans_max) { 142 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); 143 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); 144 count = z2 - z1; 145 if (count <= 0) 146 count += fifo_size; /* free bytes */ 147 if (count < skb->len+1) return(0); /* no room */ 148 count = fifo_size - count; /* bytes still not send */ 149 if (count > 2 * trans_max) return(0); /* delay to long */ 150 count = skb->len; 151 src = skb->data; 152 while (count--) 153 Write_hfc(cs, HFCSX_FIF_DWR, *src++); 154 return(1); /* success */ 155 } 156 157 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker; 158 msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES+1)); 159 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; 160 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; 161 162 count = f1 - f2; /* frame count actually buffered */ 163 if (count < 0) 164 count += (f_msk + 1); /* if wrap around */ 165 if (count > f_msk-1) { 166 if (cs->debug & L1_DEB_ISAC_FIFO) 167 debugl1(cs, "hfcsx_write_fifo %d more as %d frames",fifo,f_msk-1); 168 return(0); 169 } 170 171 *(msp + f1) = z1; /* remember marker */ 172 173 if (cs->debug & L1_DEB_ISAC_FIFO) 174 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)", 175 fifo, f1, f2, z1); 176 /* now determine free bytes in FIFO buffer */ 177 count = *(msp + f2) - z1; 178 if (count <= 0) 179 count += fifo_size; /* count now contains available bytes */ 180 181 if (cs->debug & L1_DEB_ISAC_FIFO) 182 debugl1(cs, "hfcsx_write_fifo %d count(%ld/%d)", 183 fifo, skb->len, count); 184 if (count < skb->len) { 185 if (cs->debug & L1_DEB_ISAC_FIFO) 186 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo); 187 return(0); 188 } 189 190 count = skb->len; /* get frame len */ 191 src = skb->data; /* source pointer */ 192 while (count--) 193 Write_hfc(cs, HFCSX_FIF_DWR, *src++); 194 195 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */ 196 udelay(1); 197 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 198 return(1); 199} 200 201/***************************************************************/ 202/* read_fifo reads data to an skb from the desired fifo */ 203/* if no data is available or an error occurs NULL is returned */ 204/* the skb is not released in any way. */ 205/***************************************************************/ 206static struct sk_buff * 207read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max) 208{ int fifo_size, count, z1, z2; 209 u_char f_msk, f1, f2, *dst; 210 struct sk_buff *skb; 211 212 if (!(fifo & 1)) return(NULL); /* no read fifo */ 213 fifo_select(cs, fifo); 214 if (fifo & 4) { 215 fifo_size = D_FIFO_SIZE; /* D-channel */ 216 f_msk = MAX_D_FRAMES; 217 if (trans_max) return(NULL); /* only hdlc */ 218 } 219 else { 220 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ 221 f_msk = MAX_B_FRAMES; 222 } 223 224 /* transparent mode */ 225 if (trans_max) { 226 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); 227 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); 228 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); 229 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); 230 /* now determine bytes in actual FIFO buffer */ 231 count = z1 - z2; 232 if (count <= 0) 233 count += fifo_size; /* count now contains buffered bytes */ 234 count++; 235 if (count > trans_max) 236 count = trans_max; /* limit length */ 237 if ((skb = dev_alloc_skb(count))) { 238 dst = skb_put(skb, count); 239 while (count--) 240 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); 241 return(skb); 242 } 243 else return(NULL); /* no memory */ 244 } 245 246 do { 247 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; 248 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; 249 250 if (f1 == f2) return(NULL); /* no frame available */ 251 252 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); 253 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); 254 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); 255 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); 256 257 if (cs->debug & L1_DEB_ISAC_FIFO) 258 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)", 259 fifo, f1, f2, z1, z2); 260 /* now determine bytes in actual FIFO buffer */ 261 count = z1 - z2; 262 if (count <= 0) 263 count += fifo_size; /* count now contains buffered bytes */ 264 count++; 265 266 if (cs->debug & L1_DEB_ISAC_FIFO) 267 debugl1(cs, "hfcsx_read_fifo %d count %ld)", 268 fifo, count); 269 270 if ((count > fifo_size) || (count < 4)) { 271 if (cs->debug & L1_DEB_WARN) 272 debugl1(cs, "hfcsx_read_fifo %d paket inv. len %d ", fifo , count); 273 while (count) { 274 count--; /* empty fifo */ 275 Read_hfc(cs, HFCSX_FIF_DRD); 276 } 277 skb = NULL; 278 } else 279 if ((skb = dev_alloc_skb(count - 3))) { 280 count -= 3; 281 dst = skb_put(skb, count); 282 283 while (count--) 284 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); 285 286 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */ 287 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */ 288 if (Read_hfc(cs, HFCSX_FIF_DRD)) { 289 dev_kfree_skb_irq(skb); 290 if (cs->debug & L1_DEB_ISAC_FIFO) 291 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo); 292 skb = NULL; 293 } 294 } else { 295 printk(KERN_WARNING "HFC-SX: receive out of memory\n"); 296 return(NULL); 297 } 298 299 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */ 300 udelay(1); 301 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 302 udelay(1); 303 } while (!skb); /* retry in case of crc error */ 304 return(skb); 305} 306 307/******************************************/ 308/* free hardware resources used by driver */ 309/******************************************/ 310static void 311release_io_hfcsx(struct IsdnCardState *cs) 312{ 313 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ 314 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); 315 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */ 316 msleep(30); /* Timeout 30ms */ 317 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */ 318 del_timer(&cs->hw.hfcsx.timer); 319 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */ 320 kfree(cs->hw.hfcsx.extra); 321 cs->hw.hfcsx.extra = NULL; 322} 323 324/**********************************************************/ 325/* set_fifo_size determines the size of the RAM and FIFOs */ 326/* returning 0 -> need to reset the chip again. */ 327/**********************************************************/ 328static int set_fifo_size(struct IsdnCardState *cs) 329{ 330 331 if (cs->hw.hfcsx.b_fifo_size) return(1); /* already determined */ 332 333 if ((cs->hw.hfcsx.chip >> 4) == 9) { 334 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K; 335 return(1); 336 } 337 338 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K; 339 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */ 340 return(0); 341 342} 343 344/********************************************************************************/ 345/* function called to reset the HFC SX chip. A complete software reset of chip */ 346/* and fifos is done. */ 347/********************************************************************************/ 348static void 349reset_hfcsx(struct IsdnCardState *cs) 350{ 351 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ 352 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); 353 354 printk(KERN_INFO "HFC_SX: resetting card\n"); 355 while (1) { 356 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */ 357 mdelay(30); 358 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ 359 mdelay(20); 360 if (Read_hfc(cs, HFCSX_STATUS) & 2) 361 printk(KERN_WARNING "HFC-SX init bit busy\n"); 362 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */ 363 if (!set_fifo_size(cs)) continue; 364 break; 365 } 366 367 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */ 368 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); 369 370 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */ 371 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE; 372 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */ 373 cs->hw.hfcsx.bswapped = 0; /* no exchange */ 374 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */ 375 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER; 376 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); 377 378 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC | 379 HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER; 380 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 381 382 /* Clear already pending ints */ 383 if (Read_hfc(cs, HFCSX_INT_S1)); 384 385 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */ 386 udelay(10); 387 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */ 388 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */ 389 390 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 391 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ 392 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); 393 cs->hw.hfcsx.sctrl_r = 0; 394 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); 395 396 /* Init GCI/IOM2 in master mode */ 397 /* Slots 0 and 1 are set for B-chan 1 and 2 */ 398 /* D- and monitor/CI channel are not enabled */ 399 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */ 400 /* STIO2 is used as data input, B1+B2 from IOM->ST */ 401 /* ST B-channel send disabled -> continous 1s */ 402 /* The IOM slots are always enabled */ 403 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */ 404 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); 405 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ 406 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ 407 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ 408 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ 409 410 /* Finally enable IRQ output */ 411 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE; 412 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); 413 if (Read_hfc(cs, HFCSX_INT_S2)); 414} 415 416/***************************************************/ 417/* Timer function called when kernel timer expires */ 418/***************************************************/ 419static void 420hfcsx_Timer(struct IsdnCardState *cs) 421{ 422 cs->hw.hfcsx.timer.expires = jiffies + 75; 423 /* WD RESET */ 424/* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80); 425 add_timer(&cs->hw.hfcsx.timer); 426 */ 427} 428 429/************************************************/ 430/* select a b-channel entry matching and active */ 431/************************************************/ 432static 433struct BCState * 434Sel_BCS(struct IsdnCardState *cs, int channel) 435{ 436 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) 437 return (&cs->bcs[0]); 438 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) 439 return (&cs->bcs[1]); 440 else 441 return (NULL); 442} 443 444/*******************************/ 445/* D-channel receive procedure */ 446/*******************************/ 447static 448int 449receive_dmsg(struct IsdnCardState *cs) 450{ 451 struct sk_buff *skb; 452 int count = 5; 453 454 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 455 debugl1(cs, "rec_dmsg blocked"); 456 return (1); 457 } 458 459 do { 460 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0); 461 if (skb) { 462 skb_queue_tail(&cs->rq, skb); 463 schedule_event(cs, D_RCVBUFREADY); 464 } 465 } while (--count && skb); 466 467 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 468 return (1); 469} 470 471/**********************************/ 472/* B-channel main receive routine */ 473/**********************************/ 474static void 475main_rec_hfcsx(struct BCState *bcs) 476{ 477 struct IsdnCardState *cs = bcs->cs; 478 int count = 5; 479 struct sk_buff *skb; 480 481 Begin: 482 count--; 483 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 484 debugl1(cs, "rec_data %d blocked", bcs->channel); 485 return; 486 } 487 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? 488 HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX, 489 (bcs->mode == L1_MODE_TRANS) ? 490 HFCSX_BTRANS_THRESHOLD : 0); 491 492 if (skb) { 493 skb_queue_tail(&bcs->rqueue, skb); 494 schedule_event(bcs, B_RCVBUFREADY); 495 } 496 497 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 498 if (count && skb) 499 goto Begin; 500 return; 501} 502 503/**************************/ 504/* D-channel send routine */ 505/**************************/ 506static void 507hfcsx_fill_dfifo(struct IsdnCardState *cs) 508{ 509 if (!cs->tx_skb) 510 return; 511 if (cs->tx_skb->len <= 0) 512 return; 513 514 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) { 515 dev_kfree_skb_any(cs->tx_skb); 516 cs->tx_skb = NULL; 517 } 518 return; 519} 520 521/**************************/ 522/* B-channel send routine */ 523/**************************/ 524static void 525hfcsx_fill_fifo(struct BCState *bcs) 526{ 527 struct IsdnCardState *cs = bcs->cs; 528 529 if (!bcs->tx_skb) 530 return; 531 if (bcs->tx_skb->len <= 0) 532 return; 533 534 if (write_fifo(cs, bcs->tx_skb, 535 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? 536 HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX, 537 (bcs->mode == L1_MODE_TRANS) ? 538 HFCSX_BTRANS_THRESHOLD : 0)) { 539 540 bcs->tx_cnt -= bcs->tx_skb->len; 541 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) && 542 (PACKET_NOACK != bcs->tx_skb->pkt_type)) { 543 u_long flags; 544 spin_lock_irqsave(&bcs->aclock, flags); 545 bcs->ackcnt += bcs->tx_skb->len; 546 spin_unlock_irqrestore(&bcs->aclock, flags); 547 schedule_event(bcs, B_ACKPENDING); 548 } 549 dev_kfree_skb_any(bcs->tx_skb); 550 bcs->tx_skb = NULL; 551 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); 552 } 553} 554 555/**********************************************/ 556/* D-channel l1 state call for leased NT-mode */ 557/**********************************************/ 558static void 559dch_nt_l2l1(struct PStack *st, int pr, void *arg) 560{ 561 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; 562 563 switch (pr) { 564 case (PH_DATA | REQUEST): 565 case (PH_PULL | REQUEST): 566 case (PH_PULL | INDICATION): 567 st->l1.l1hw(st, pr, arg); 568 break; 569 case (PH_ACTIVATE | REQUEST): 570 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL); 571 break; 572 case (PH_TESTLOOP | REQUEST): 573 if (1 & (long) arg) 574 debugl1(cs, "PH_TEST_LOOP B1"); 575 if (2 & (long) arg) 576 debugl1(cs, "PH_TEST_LOOP B2"); 577 if (!(3 & (long) arg)) 578 debugl1(cs, "PH_TEST_LOOP DISABLED"); 579 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg); 580 break; 581 default: 582 if (cs->debug) 583 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr); 584 break; 585 } 586} 587 588 589 590/***********************/ 591/* set/reset echo mode */ 592/***********************/ 593static int 594hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic) 595{ 596 unsigned long flags; 597 int i = *(unsigned int *) ic->parm.num; 598 599 if ((ic->arg == 98) && 600 (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) { 601 spin_lock_irqsave(&cs->lock, flags); 602 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */ 603 udelay(10); 604 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT; 605 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */ 606 udelay(10); 607 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */ 608 udelay(10); 609 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION); 610 cs->dc.hfcsx.ph_state = 1; 611 cs->hw.hfcsx.nt_mode = 1; 612 cs->hw.hfcsx.nt_timer = 0; 613 spin_unlock_irqrestore(&cs->lock, flags); 614 cs->stlist->l2.l2l1 = dch_nt_l2l1; 615 debugl1(cs, "NT mode activated"); 616 return (0); 617 } 618 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) || 619 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12)) 620 return (-EINVAL); 621 622 if (i) { 623 cs->logecho = 1; 624 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */ 625 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC; 626 /* reset Channel !!!!! */ 627 } else { 628 cs->logecho = 0; 629 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */ 630 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC; 631 } 632 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; 633 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; 634 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */ 635 cs->hw.hfcsx.ctmt &= ~2; 636 spin_lock_irqsave(&cs->lock, flags); 637 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); 638 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); 639 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); 640 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); 641 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); 642 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 643 spin_unlock_irqrestore(&cs->lock, flags); 644 return (0); 645} /* hfcsx_auxcmd */ 646 647/*****************************/ 648/* E-channel receive routine */ 649/*****************************/ 650static void 651receive_emsg(struct IsdnCardState *cs) 652{ 653 int count = 5; 654 u_char *ptr; 655 struct sk_buff *skb; 656 657 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 658 debugl1(cs, "echo_rec_data blocked"); 659 return; 660 } 661 do { 662 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0); 663 if (skb) { 664 if (cs->debug & DEB_DLOG_HEX) { 665 ptr = cs->dlog; 666 if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) { 667 *ptr++ = 'E'; 668 *ptr++ = 'C'; 669 *ptr++ = 'H'; 670 *ptr++ = 'O'; 671 *ptr++ = ':'; 672 ptr += QuickHex(ptr, skb->data, skb->len); 673 ptr--; 674 *ptr++ = '\n'; 675 *ptr = 0; 676 HiSax_putstatus(cs, NULL, cs->dlog); 677 } else 678 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len); 679 } 680 dev_kfree_skb_any(skb); 681 } 682 } while (--count && skb); 683 684 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 685 return; 686} /* receive_emsg */ 687 688 689/*********************/ 690/* Interrupt handler */ 691/*********************/ 692static irqreturn_t 693hfcsx_interrupt(int intno, void *dev_id) 694{ 695 struct IsdnCardState *cs = dev_id; 696 u_char exval; 697 struct BCState *bcs; 698 int count = 15; 699 u_long flags; 700 u_char val, stat; 701 702 if (!(cs->hw.hfcsx.int_m2 & 0x08)) 703 return IRQ_NONE; /* not initialised */ 704 705 spin_lock_irqsave(&cs->lock, flags); 706 if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) { 707 val = Read_hfc(cs, HFCSX_INT_S1); 708 if (cs->debug & L1_DEB_ISAC) 709 debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val); 710 } else { 711 spin_unlock_irqrestore(&cs->lock, flags); 712 return IRQ_NONE; 713 } 714 if (cs->debug & L1_DEB_ISAC) 715 debugl1(cs, "HFC-SX irq %x %s", val, 716 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? 717 "locked" : "unlocked"); 718 val &= cs->hw.hfcsx.int_m1; 719 if (val & 0x40) { /* state machine irq */ 720 exval = Read_hfc(cs, HFCSX_STATES) & 0xf; 721 if (cs->debug & L1_DEB_ISAC) 722 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state, 723 exval); 724 cs->dc.hfcsx.ph_state = exval; 725 schedule_event(cs, D_L1STATECHANGE); 726 val &= ~0x40; 727 } 728 if (val & 0x80) { /* timer irq */ 729 if (cs->hw.hfcsx.nt_mode) { 730 if ((--cs->hw.hfcsx.nt_timer) < 0) 731 schedule_event(cs, D_L1STATECHANGE); 732 } 733 val &= ~0x80; 734 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); 735 } 736 while (val) { 737 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 738 cs->hw.hfcsx.int_s1 |= val; 739 spin_unlock_irqrestore(&cs->lock, flags); 740 return IRQ_HANDLED; 741 } 742 if (cs->hw.hfcsx.int_s1 & 0x18) { 743 exval = val; 744 val = cs->hw.hfcsx.int_s1; 745 cs->hw.hfcsx.int_s1 = exval; 746 } 747 if (val & 0x08) { 748 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { 749 if (cs->debug) 750 debugl1(cs, "hfcsx spurious 0x08 IRQ"); 751 } else 752 main_rec_hfcsx(bcs); 753 } 754 if (val & 0x10) { 755 if (cs->logecho) 756 receive_emsg(cs); 757 else if (!(bcs = Sel_BCS(cs, 1))) { 758 if (cs->debug) 759 debugl1(cs, "hfcsx spurious 0x10 IRQ"); 760 } else 761 main_rec_hfcsx(bcs); 762 } 763 if (val & 0x01) { 764 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { 765 if (cs->debug) 766 debugl1(cs, "hfcsx spurious 0x01 IRQ"); 767 } else { 768 if (bcs->tx_skb) { 769 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 770 hfcsx_fill_fifo(bcs); 771 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 772 } else 773 debugl1(cs, "fill_data %d blocked", bcs->channel); 774 } else { 775 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) { 776 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 777 hfcsx_fill_fifo(bcs); 778 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 779 } else 780 debugl1(cs, "fill_data %d blocked", bcs->channel); 781 } else { 782 schedule_event(bcs, B_XMTBUFREADY); 783 } 784 } 785 } 786 } 787 if (val & 0x02) { 788 if (!(bcs = Sel_BCS(cs, 1))) { 789 if (cs->debug) 790 debugl1(cs, "hfcsx spurious 0x02 IRQ"); 791 } else { 792 if (bcs->tx_skb) { 793 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 794 hfcsx_fill_fifo(bcs); 795 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 796 } else 797 debugl1(cs, "fill_data %d blocked", bcs->channel); 798 } else { 799 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) { 800 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 801 hfcsx_fill_fifo(bcs); 802 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 803 } else 804 debugl1(cs, "fill_data %d blocked", bcs->channel); 805 } else { 806 schedule_event(bcs, B_XMTBUFREADY); 807 } 808 } 809 } 810 } 811 if (val & 0x20) { /* receive dframe */ 812 receive_dmsg(cs); 813 } 814 if (val & 0x04) { /* dframe transmitted */ 815 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) 816 del_timer(&cs->dbusytimer); 817 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) 818 schedule_event(cs, D_CLEARBUSY); 819 if (cs->tx_skb) { 820 if (cs->tx_skb->len) { 821 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 822 hfcsx_fill_dfifo(cs); 823 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 824 } else { 825 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); 826 } 827 goto afterXPR; 828 } else { 829 dev_kfree_skb_irq(cs->tx_skb); 830 cs->tx_cnt = 0; 831 cs->tx_skb = NULL; 832 } 833 } 834 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { 835 cs->tx_cnt = 0; 836 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 837 hfcsx_fill_dfifo(cs); 838 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 839 } else { 840 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); 841 } 842 } else 843 schedule_event(cs, D_XMTBUFREADY); 844 } 845 afterXPR: 846 if (cs->hw.hfcsx.int_s1 && count--) { 847 val = cs->hw.hfcsx.int_s1; 848 cs->hw.hfcsx.int_s1 = 0; 849 if (cs->debug & L1_DEB_ISAC) 850 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count); 851 } else 852 val = 0; 853 } 854 spin_unlock_irqrestore(&cs->lock, flags); 855 return IRQ_HANDLED; 856} 857 858/********************************************************************/ 859/* timer callback for D-chan busy resolution. Currently no function */ 860/********************************************************************/ 861static void 862hfcsx_dbusy_timer(struct IsdnCardState *cs) 863{ 864} 865 866/*************************************/ 867/* Layer 1 D-channel hardware access */ 868/*************************************/ 869static void 870HFCSX_l1hw(struct PStack *st, int pr, void *arg) 871{ 872 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; 873 struct sk_buff *skb = arg; 874 u_long flags; 875 876 switch (pr) { 877 case (PH_DATA | REQUEST): 878 if (cs->debug & DEB_DLOG_HEX) 879 LogFrame(cs, skb->data, skb->len); 880 if (cs->debug & DEB_DLOG_VERBOSE) 881 dlogframe(cs, skb, 0); 882 spin_lock_irqsave(&cs->lock, flags); 883 if (cs->tx_skb) { 884 skb_queue_tail(&cs->sq, skb); 885#ifdef L2FRAME_DEBUG /* psa */ 886 if (cs->debug & L1_DEB_LAPD) 887 Logl2Frame(cs, skb, "PH_DATA Queued", 0); 888#endif 889 } else { 890 cs->tx_skb = skb; 891 cs->tx_cnt = 0; 892#ifdef L2FRAME_DEBUG /* psa */ 893 if (cs->debug & L1_DEB_LAPD) 894 Logl2Frame(cs, skb, "PH_DATA", 0); 895#endif 896 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 897 hfcsx_fill_dfifo(cs); 898 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 899 } else 900 debugl1(cs, "hfcsx_fill_dfifo blocked"); 901 902 } 903 spin_unlock_irqrestore(&cs->lock, flags); 904 break; 905 case (PH_PULL | INDICATION): 906 spin_lock_irqsave(&cs->lock, flags); 907 if (cs->tx_skb) { 908 if (cs->debug & L1_DEB_WARN) 909 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); 910 skb_queue_tail(&cs->sq, skb); 911 spin_unlock_irqrestore(&cs->lock, flags); 912 break; 913 } 914 if (cs->debug & DEB_DLOG_HEX) 915 LogFrame(cs, skb->data, skb->len); 916 if (cs->debug & DEB_DLOG_VERBOSE) 917 dlogframe(cs, skb, 0); 918 cs->tx_skb = skb; 919 cs->tx_cnt = 0; 920#ifdef L2FRAME_DEBUG /* psa */ 921 if (cs->debug & L1_DEB_LAPD) 922 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); 923#endif 924 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 925 hfcsx_fill_dfifo(cs); 926 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 927 } else 928 debugl1(cs, "hfcsx_fill_dfifo blocked"); 929 spin_unlock_irqrestore(&cs->lock, flags); 930 break; 931 case (PH_PULL | REQUEST): 932#ifdef L2FRAME_DEBUG /* psa */ 933 if (cs->debug & L1_DEB_LAPD) 934 debugl1(cs, "-> PH_REQUEST_PULL"); 935#endif 936 if (!cs->tx_skb) { 937 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 938 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); 939 } else 940 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 941 break; 942 case (HW_RESET | REQUEST): 943 spin_lock_irqsave(&cs->lock, flags); 944 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */ 945 udelay(6); 946 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */ 947 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; 948 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 949 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); 950 spin_unlock_irqrestore(&cs->lock, flags); 951 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); 952 break; 953 case (HW_ENABLE | REQUEST): 954 spin_lock_irqsave(&cs->lock, flags); 955 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); 956 spin_unlock_irqrestore(&cs->lock, flags); 957 break; 958 case (HW_DEACTIVATE | REQUEST): 959 spin_lock_irqsave(&cs->lock, flags); 960 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER; 961 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 962 spin_unlock_irqrestore(&cs->lock, flags); 963 break; 964 case (HW_INFO3 | REQUEST): 965 spin_lock_irqsave(&cs->lock, flags); 966 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; 967 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 968 spin_unlock_irqrestore(&cs->lock, flags); 969 break; 970 case (HW_TESTLOOP | REQUEST): 971 spin_lock_irqsave(&cs->lock, flags); 972 switch ((long) arg) { 973 case (1): 974 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */ 975 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */ 976 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1; 977 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); 978 break; 979 case (2): 980 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */ 981 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */ 982 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08; 983 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); 984 break; 985 default: 986 spin_unlock_irqrestore(&cs->lock, flags); 987 if (cs->debug & L1_DEB_WARN) 988 debugl1(cs, "hfcsx_l1hw loop invalid %4lx", arg); 989 return; 990 } 991 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */ 992 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); 993 spin_unlock_irqrestore(&cs->lock, flags); 994 break; 995 default: 996 if (cs->debug & L1_DEB_WARN) 997 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr); 998 break; 999 } 1000} 1001 1002/***********************************************/ 1003/* called during init setting l1 stack pointer */ 1004/***********************************************/ 1005static void 1006setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs) 1007{ 1008 st->l1.l1hw = HFCSX_l1hw; 1009} 1010 1011/**************************************/ 1012/* send B-channel data if not blocked */ 1013/**************************************/ 1014static void 1015hfcsx_send_data(struct BCState *bcs) 1016{ 1017 struct IsdnCardState *cs = bcs->cs; 1018 1019 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 1020 hfcsx_fill_fifo(bcs); 1021 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 1022 } else 1023 debugl1(cs, "send_data %d blocked", bcs->channel); 1024} 1025 1026/***************************************************************/ 1027/* activate/deactivate hardware for selected channels and mode */ 1028/***************************************************************/ 1029static void 1030mode_hfcsx(struct BCState *bcs, int mode, int bc) 1031{ 1032 struct IsdnCardState *cs = bcs->cs; 1033 int fifo2; 1034 1035 if (cs->debug & L1_DEB_HSCX) 1036 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d", 1037 mode, bc, bcs->channel); 1038 bcs->mode = mode; 1039 bcs->channel = bc; 1040 fifo2 = bc; 1041 if (cs->chanlimit > 1) { 1042 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ 1043 cs->hw.hfcsx.sctrl_e &= ~0x80; 1044 } else { 1045 if (bc) { 1046 if (mode != L1_MODE_NULL) { 1047 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */ 1048 cs->hw.hfcsx.sctrl_e |= 0x80; 1049 } else { 1050 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ 1051 cs->hw.hfcsx.sctrl_e &= ~0x80; 1052 } 1053 fifo2 = 0; 1054 } else { 1055 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ 1056 cs->hw.hfcsx.sctrl_e &= ~0x80; 1057 } 1058 } 1059 switch (mode) { 1060 case (L1_MODE_NULL): 1061 if (bc) { 1062 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; 1063 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; 1064 } else { 1065 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA; 1066 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA; 1067 } 1068 if (fifo2) { 1069 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); 1070 } else { 1071 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); 1072 } 1073 break; 1074 case (L1_MODE_TRANS): 1075 if (bc) { 1076 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; 1077 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; 1078 } else { 1079 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; 1080 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; 1081 } 1082 if (fifo2) { 1083 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); 1084 cs->hw.hfcsx.ctmt |= 2; 1085 cs->hw.hfcsx.conn &= ~0x18; 1086 } else { 1087 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); 1088 cs->hw.hfcsx.ctmt |= 1; 1089 cs->hw.hfcsx.conn &= ~0x03; 1090 } 1091 break; 1092 case (L1_MODE_HDLC): 1093 if (bc) { 1094 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; 1095 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; 1096 } else { 1097 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; 1098 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; 1099 } 1100 if (fifo2) { 1101 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); 1102 cs->hw.hfcsx.ctmt &= ~2; 1103 cs->hw.hfcsx.conn &= ~0x18; 1104 } else { 1105 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); 1106 cs->hw.hfcsx.ctmt &= ~1; 1107 cs->hw.hfcsx.conn &= ~0x03; 1108 } 1109 break; 1110 case (L1_MODE_EXTRN): 1111 if (bc) { 1112 cs->hw.hfcsx.conn |= 0x10; 1113 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; 1114 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; 1115 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); 1116 } else { 1117 cs->hw.hfcsx.conn |= 0x02; 1118 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; 1119 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; 1120 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); 1121 } 1122 break; 1123 } 1124 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); 1125 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1126 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); 1127 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); 1128 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); 1129 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); 1130 if (mode != L1_MODE_EXTRN) { 1131 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX); 1132 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX); 1133 } 1134} 1135 1136/******************************/ 1137/* Layer2 -> Layer 1 Transfer */ 1138/******************************/ 1139static void 1140hfcsx_l2l1(struct PStack *st, int pr, void *arg) 1141{ 1142 struct BCState *bcs = st->l1.bcs; 1143 struct sk_buff *skb = arg; 1144 u_long flags; 1145 1146 switch (pr) { 1147 case (PH_DATA | REQUEST): 1148 spin_lock_irqsave(&bcs->cs->lock, flags); 1149 if (bcs->tx_skb) { 1150 skb_queue_tail(&bcs->squeue, skb); 1151 } else { 1152 bcs->tx_skb = skb; 1153// test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); 1154 bcs->cs->BC_Send_Data(bcs); 1155 } 1156 spin_unlock_irqrestore(&bcs->cs->lock, flags); 1157 break; 1158 case (PH_PULL | INDICATION): 1159 spin_lock_irqsave(&bcs->cs->lock, flags); 1160 if (bcs->tx_skb) { 1161 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n"); 1162 } else { 1163// test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); 1164 bcs->tx_skb = skb; 1165 bcs->cs->BC_Send_Data(bcs); 1166 } 1167 spin_unlock_irqrestore(&bcs->cs->lock, flags); 1168 break; 1169 case (PH_PULL | REQUEST): 1170 if (!bcs->tx_skb) { 1171 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 1172 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); 1173 } else 1174 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 1175 break; 1176 case (PH_ACTIVATE | REQUEST): 1177 spin_lock_irqsave(&bcs->cs->lock, flags); 1178 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag); 1179 mode_hfcsx(bcs, st->l1.mode, st->l1.bc); 1180 spin_unlock_irqrestore(&bcs->cs->lock, flags); 1181 l1_msg_b(st, pr, arg); 1182 break; 1183 case (PH_DEACTIVATE | REQUEST): 1184 l1_msg_b(st, pr, arg); 1185 break; 1186 case (PH_DEACTIVATE | CONFIRM): 1187 spin_lock_irqsave(&bcs->cs->lock, flags); 1188 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag); 1189 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); 1190 mode_hfcsx(bcs, 0, st->l1.bc); 1191 spin_unlock_irqrestore(&bcs->cs->lock, flags); 1192 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL); 1193 break; 1194 } 1195} 1196 1197/******************************************/ 1198/* deactivate B-channel access and queues */ 1199/******************************************/ 1200static void 1201close_hfcsx(struct BCState *bcs) 1202{ 1203 mode_hfcsx(bcs, 0, bcs->channel); 1204 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) { 1205 skb_queue_purge(&bcs->rqueue); 1206 skb_queue_purge(&bcs->squeue); 1207 if (bcs->tx_skb) { 1208 dev_kfree_skb_any(bcs->tx_skb); 1209 bcs->tx_skb = NULL; 1210 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); 1211 } 1212 } 1213} 1214 1215/*************************************/ 1216/* init B-channel queues and control */ 1217/*************************************/ 1218static int 1219open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs) 1220{ 1221 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) { 1222 skb_queue_head_init(&bcs->rqueue); 1223 skb_queue_head_init(&bcs->squeue); 1224 } 1225 bcs->tx_skb = NULL; 1226 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); 1227 bcs->event = 0; 1228 bcs->tx_cnt = 0; 1229 return (0); 1230} 1231 1232/*********************************/ 1233/* inits the stack for B-channel */ 1234/*********************************/ 1235static int 1236setstack_2b(struct PStack *st, struct BCState *bcs) 1237{ 1238 bcs->channel = st->l1.bc; 1239 if (open_hfcsxstate(st->l1.hardware, bcs)) 1240 return (-1); 1241 st->l1.bcs = bcs; 1242 st->l2.l2l1 = hfcsx_l2l1; 1243 setstack_manager(st); 1244 bcs->st = st; 1245 setstack_l1_B(st); 1246 return (0); 1247} 1248 1249/***************************/ 1250/* handle L1 state changes */ 1251/***************************/ 1252static void 1253hfcsx_bh(struct work_struct *work) 1254{ 1255 struct IsdnCardState *cs = 1256 container_of(work, struct IsdnCardState, tqueue); 1257 u_long flags; 1258 1259 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { 1260 if (!cs->hw.hfcsx.nt_mode) 1261 switch (cs->dc.hfcsx.ph_state) { 1262 case (0): 1263 l1_msg(cs, HW_RESET | INDICATION, NULL); 1264 break; 1265 case (3): 1266 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); 1267 break; 1268 case (8): 1269 l1_msg(cs, HW_RSYNC | INDICATION, NULL); 1270 break; 1271 case (6): 1272 l1_msg(cs, HW_INFO2 | INDICATION, NULL); 1273 break; 1274 case (7): 1275 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); 1276 break; 1277 default: 1278 break; 1279 } else { 1280 switch (cs->dc.hfcsx.ph_state) { 1281 case (2): 1282 spin_lock_irqsave(&cs->lock, flags); 1283 if (cs->hw.hfcsx.nt_timer < 0) { 1284 cs->hw.hfcsx.nt_timer = 0; 1285 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; 1286 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1287 /* Clear already pending ints */ 1288 if (Read_hfc(cs, HFCSX_INT_S1)); 1289 1290 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE); 1291 udelay(10); 1292 Write_hfc(cs, HFCSX_STATES, 4); 1293 cs->dc.hfcsx.ph_state = 4; 1294 } else { 1295 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER; 1296 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1297 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER; 1298 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125; 1299 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); 1300 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); 1301 cs->hw.hfcsx.nt_timer = NT_T1_COUNT; 1302 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */ 1303 } 1304 spin_unlock_irqrestore(&cs->lock, flags); 1305 break; 1306 case (1): 1307 case (3): 1308 case (4): 1309 spin_lock_irqsave(&cs->lock, flags); 1310 cs->hw.hfcsx.nt_timer = 0; 1311 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; 1312 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1313 spin_unlock_irqrestore(&cs->lock, flags); 1314 break; 1315 default: 1316 break; 1317 } 1318 } 1319 } 1320 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) 1321 DChannel_proc_rcv(cs); 1322 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) 1323 DChannel_proc_xmt(cs); 1324} 1325 1326 1327/********************************/ 1328/* called for card init message */ 1329/********************************/ 1330static void inithfcsx(struct IsdnCardState *cs) 1331{ 1332 cs->setstack_d = setstack_hfcsx; 1333 cs->BC_Send_Data = &hfcsx_send_data; 1334 cs->bcs[0].BC_SetStack = setstack_2b; 1335 cs->bcs[1].BC_SetStack = setstack_2b; 1336 cs->bcs[0].BC_Close = close_hfcsx; 1337 cs->bcs[1].BC_Close = close_hfcsx; 1338 mode_hfcsx(cs->bcs, 0, 0); 1339 mode_hfcsx(cs->bcs + 1, 0, 1); 1340} 1341 1342 1343 1344/*******************************************/ 1345/* handle card messages from control layer */ 1346/*******************************************/ 1347static int 1348hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg) 1349{ 1350 u_long flags; 1351 1352 if (cs->debug & L1_DEB_ISAC) 1353 debugl1(cs, "HFCSX: card_msg %x", mt); 1354 switch (mt) { 1355 case CARD_RESET: 1356 spin_lock_irqsave(&cs->lock, flags); 1357 reset_hfcsx(cs); 1358 spin_unlock_irqrestore(&cs->lock, flags); 1359 return (0); 1360 case CARD_RELEASE: 1361 release_io_hfcsx(cs); 1362 return (0); 1363 case CARD_INIT: 1364 spin_lock_irqsave(&cs->lock, flags); 1365 inithfcsx(cs); 1366 spin_unlock_irqrestore(&cs->lock, flags); 1367 msleep(80); /* Timeout 80ms */ 1368 /* now switch timer interrupt off */ 1369 spin_lock_irqsave(&cs->lock, flags); 1370 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; 1371 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1372 /* reinit mode reg */ 1373 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 1374 spin_unlock_irqrestore(&cs->lock, flags); 1375 return (0); 1376 case CARD_TEST: 1377 return (0); 1378 } 1379 return (0); 1380} 1381 1382#ifdef __ISAPNP__ 1383static struct isapnp_device_id hfc_ids[] __devinitdata = { 1384 { ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620), 1385 ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620), 1386 (unsigned long) "Teles 16.3c2" }, 1387 { 0, } 1388}; 1389 1390static struct isapnp_device_id *ipid __devinitdata = &hfc_ids[0]; 1391static struct pnp_card *pnp_c __devinitdata = NULL; 1392#endif 1393 1394int __devinit 1395setup_hfcsx(struct IsdnCard *card) 1396{ 1397 struct IsdnCardState *cs = card->cs; 1398 char tmp[64]; 1399 1400 strcpy(tmp, hfcsx_revision); 1401 printk(KERN_INFO "HiSax: HFC-SX driver Rev. %s\n", HiSax_getrev(tmp)); 1402#ifdef __ISAPNP__ 1403 if (!card->para[1] && isapnp_present()) { 1404 struct pnp_dev *pnp_d; 1405 while(ipid->card_vendor) { 1406 if ((pnp_c = pnp_find_card(ipid->card_vendor, 1407 ipid->card_device, pnp_c))) { 1408 pnp_d = NULL; 1409 if ((pnp_d = pnp_find_dev(pnp_c, 1410 ipid->vendor, ipid->function, pnp_d))) { 1411 int err; 1412 1413 printk(KERN_INFO "HiSax: %s detected\n", 1414 (char *)ipid->driver_data); 1415 pnp_disable_dev(pnp_d); 1416 err = pnp_activate_dev(pnp_d); 1417 if (err<0) { 1418 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n", 1419 __func__, err); 1420 return(0); 1421 } 1422 card->para[1] = pnp_port_start(pnp_d, 0); 1423 card->para[0] = pnp_irq(pnp_d, 0); 1424 if (!card->para[0] || !card->para[1]) { 1425 printk(KERN_ERR "HFC PnP:some resources are missing %ld/%lx\n", 1426 card->para[0], card->para[1]); 1427 pnp_disable_dev(pnp_d); 1428 return(0); 1429 } 1430 break; 1431 } else { 1432 printk(KERN_ERR "HFC PnP: PnP error card found, no device\n"); 1433 } 1434 } 1435 ipid++; 1436 pnp_c = NULL; 1437 } 1438 if (!ipid->card_vendor) { 1439 printk(KERN_INFO "HFC PnP: no ISAPnP card found\n"); 1440 return(0); 1441 } 1442 } 1443#endif 1444 cs->hw.hfcsx.base = card->para[1] & 0xfffe; 1445 cs->irq = card->para[0]; 1446 cs->hw.hfcsx.int_s1 = 0; 1447 cs->dc.hfcsx.ph_state = 0; 1448 cs->hw.hfcsx.fifo = 255; 1449 if ((cs->typ == ISDN_CTYPE_HFC_SX) || 1450 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) { 1451 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) { 1452 printk(KERN_WARNING 1453 "HiSax: HFC-SX io-base %#lx already in use\n", 1454 cs->hw.hfcsx.base); 1455 return(0); 1456 } 1457 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); 1458 byteout(cs->hw.hfcsx.base + 1, 1459 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54); 1460 udelay(10); 1461 cs->hw.hfcsx.chip = Read_hfc(cs,HFCSX_CHIP_ID); 1462 switch (cs->hw.hfcsx.chip >> 4) { 1463 case 1: 1464 tmp[0] ='+'; 1465 break; 1466 case 9: 1467 tmp[0] ='P'; 1468 break; 1469 default: 1470 printk(KERN_WARNING 1471 "HFC-SX: invalid chip id 0x%x\n", 1472 cs->hw.hfcsx.chip >> 4); 1473 release_region(cs->hw.hfcsx.base, 2); 1474 return(0); 1475 } 1476 if (!ccd_sp_irqtab[cs->irq & 0xF]) { 1477 printk(KERN_WARNING 1478 "HFC_SX: invalid irq %d specified\n",cs->irq & 0xF); 1479 release_region(cs->hw.hfcsx.base, 2); 1480 return(0); 1481 } 1482 if (!(cs->hw.hfcsx.extra = (void *) 1483 kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) { 1484 release_region(cs->hw.hfcsx.base, 2); 1485 printk(KERN_WARNING "HFC-SX: unable to allocate memory\n"); 1486 return(0); 1487 } 1488 printk(KERN_INFO "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n", 1489 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ); 1490 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */ 1491 cs->hw.hfcsx.int_m1 = 0; 1492 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1493 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); 1494 } else 1495 return (0); /* no valid card type */ 1496 1497 cs->dbusytimer.function = (void *) hfcsx_dbusy_timer; 1498 cs->dbusytimer.data = (long) cs; 1499 init_timer(&cs->dbusytimer); 1500 INIT_WORK(&cs->tqueue, hfcsx_bh); 1501 cs->readisac = NULL; 1502 cs->writeisac = NULL; 1503 cs->readisacfifo = NULL; 1504 cs->writeisacfifo = NULL; 1505 cs->BC_Read_Reg = NULL; 1506 cs->BC_Write_Reg = NULL; 1507 cs->irq_func = &hfcsx_interrupt; 1508 1509 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer; 1510 cs->hw.hfcsx.timer.data = (long) cs; 1511 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */ 1512 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */ 1513 init_timer(&cs->hw.hfcsx.timer); 1514 1515 reset_hfcsx(cs); 1516 cs->cardmsg = &hfcsx_card_msg; 1517 cs->auxcmd = &hfcsx_auxcmd; 1518 return (1); 1519} 1520