1/* 2 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#include <linux/pci.h> 34#include <linux/io.h> 35#include <linux/delay.h> 36#include <linux/vmalloc.h> 37#include <linux/aer.h> 38 39#include "qib.h" 40 41/* 42 * This file contains PCIe utility routines that are common to the 43 * various QLogic InfiniPath adapters 44 */ 45 46/* 47 * Code to adjust PCIe capabilities. 48 * To minimize the change footprint, we call it 49 * from qib_pcie_params, which every chip-specific 50 * file calls, even though this violates some 51 * expectations of harmlessness. 52 */ 53static int qib_tune_pcie_caps(struct qib_devdata *); 54static int qib_tune_pcie_coalesce(struct qib_devdata *); 55 56/* 57 * Do all the common PCIe setup and initialization. 58 * devdata is not yet allocated, and is not allocated until after this 59 * routine returns success. Therefore qib_dev_err() can't be used for error 60 * printing. 61 */ 62int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 63{ 64 int ret; 65 66 ret = pci_enable_device(pdev); 67 if (ret) { 68 /* 69 * This can happen (in theory) iff: 70 * We did a chip reset, and then failed to reprogram the 71 * BAR, or the chip reset due to an internal error. We then 72 * unloaded the driver and reloaded it. 73 * 74 * Both reset cases set the BAR back to initial state. For 75 * the latter case, the AER sticky error bit at offset 0x718 76 * should be set, but the Linux kernel doesn't yet know 77 * about that, it appears. If the original BAR was retained 78 * in the kernel data structures, this may be OK. 79 */ 80 qib_early_err(&pdev->dev, "pci enable failed: error %d\n", 81 -ret); 82 goto done; 83 } 84 85 ret = pci_request_regions(pdev, QIB_DRV_NAME); 86 if (ret) { 87 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); 88 goto bail; 89 } 90 91 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 92 if (ret) { 93 /* 94 * If the 64 bit setup fails, try 32 bit. Some systems 95 * do not setup 64 bit maps on systems with 2GB or less 96 * memory installed. 97 */ 98 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 99 if (ret) { 100 qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret); 101 goto bail; 102 } 103 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 104 } else 105 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 106 if (ret) 107 qib_early_err(&pdev->dev, 108 "Unable to set DMA consistent mask: %d\n", ret); 109 110 pci_set_master(pdev); 111 ret = pci_enable_pcie_error_reporting(pdev); 112 if (ret) 113 qib_early_err(&pdev->dev, 114 "Unable to enable pcie error reporting: %d\n", 115 ret); 116 goto done; 117 118bail: 119 pci_disable_device(pdev); 120 pci_release_regions(pdev); 121done: 122 return ret; 123} 124 125/* 126 * Do remaining PCIe setup, once dd is allocated, and save away 127 * fields required to re-initialize after a chip reset, or for 128 * various other purposes 129 */ 130int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev, 131 const struct pci_device_id *ent) 132{ 133 unsigned long len; 134 resource_size_t addr; 135 136 dd->pcidev = pdev; 137 pci_set_drvdata(pdev, dd); 138 139 addr = pci_resource_start(pdev, 0); 140 len = pci_resource_len(pdev, 0); 141 142#if defined(__powerpc__) 143 /* There isn't a generic way to specify writethrough mappings */ 144 dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU); 145#else 146 dd->kregbase = ioremap_nocache(addr, len); 147#endif 148 149 if (!dd->kregbase) 150 return -ENOMEM; 151 152 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len); 153 dd->physaddr = addr; /* used for io_remap, etc. */ 154 155 /* 156 * Save BARs to rewrite after device reset. Save all 64 bits of 157 * BAR, just in case. 158 */ 159 dd->pcibar0 = addr; 160 dd->pcibar1 = addr >> 32; 161 dd->deviceid = ent->device; /* save for later use */ 162 dd->vendorid = ent->vendor; 163 164 return 0; 165} 166 167/* 168 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior 169 * to releasing the dd memory. 170 * void because none of the core pcie cleanup returns are void 171 */ 172void qib_pcie_ddcleanup(struct qib_devdata *dd) 173{ 174 u64 __iomem *base = (void __iomem *) dd->kregbase; 175 176 dd->kregbase = NULL; 177 iounmap(base); 178 if (dd->piobase) 179 iounmap(dd->piobase); 180 if (dd->userbase) 181 iounmap(dd->userbase); 182 if (dd->piovl15base) 183 iounmap(dd->piovl15base); 184 185 pci_disable_device(dd->pcidev); 186 pci_release_regions(dd->pcidev); 187 188 pci_set_drvdata(dd->pcidev, NULL); 189} 190 191static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt, 192 struct msix_entry *msix_entry) 193{ 194 int ret; 195 u32 tabsize = 0; 196 u16 msix_flags; 197 198 pci_read_config_word(dd->pcidev, pos + PCI_MSIX_FLAGS, &msix_flags); 199 tabsize = 1 + (msix_flags & PCI_MSIX_FLAGS_QSIZE); 200 if (tabsize > *msixcnt) 201 tabsize = *msixcnt; 202 ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize); 203 if (ret > 0) { 204 tabsize = ret; 205 ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize); 206 } 207 if (ret) { 208 qib_dev_err(dd, "pci_enable_msix %d vectors failed: %d, " 209 "falling back to INTx\n", tabsize, ret); 210 tabsize = 0; 211 } 212 *msixcnt = tabsize; 213 214 if (ret) 215 qib_enable_intx(dd->pcidev); 216 217} 218 219/** 220 * We save the msi lo and hi values, so we can restore them after 221 * chip reset (the kernel PCI infrastructure doesn't yet handle that 222 * correctly. 223 */ 224static int qib_msi_setup(struct qib_devdata *dd, int pos) 225{ 226 struct pci_dev *pdev = dd->pcidev; 227 u16 control; 228 int ret; 229 230 ret = pci_enable_msi(pdev); 231 if (ret) 232 qib_dev_err(dd, "pci_enable_msi failed: %d, " 233 "interrupts may not work\n", ret); 234 /* continue even if it fails, we may still be OK... */ 235 236 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, 237 &dd->msi_lo); 238 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, 239 &dd->msi_hi); 240 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 241 /* now save the data (vector) info */ 242 pci_read_config_word(pdev, pos + ((control & PCI_MSI_FLAGS_64BIT) 243 ? 12 : 8), 244 &dd->msi_data); 245 return ret; 246} 247 248int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent, 249 struct msix_entry *entry) 250{ 251 u16 linkstat, speed; 252 int pos = 0, pose, ret = 1; 253 254 pose = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP); 255 if (!pose) { 256 qib_dev_err(dd, "Can't find PCI Express capability!\n"); 257 /* set up something... */ 258 dd->lbus_width = 1; 259 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 260 goto bail; 261 } 262 263 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSIX); 264 if (nent && *nent && pos) { 265 qib_msix_setup(dd, pos, nent, entry); 266 ret = 0; /* did it, either MSIx or INTx */ 267 } else { 268 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI); 269 if (pos) 270 ret = qib_msi_setup(dd, pos); 271 else 272 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n"); 273 } 274 if (!pos) 275 qib_enable_intx(dd->pcidev); 276 277 pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat); 278 /* 279 * speed is bits 0-3, linkwidth is bits 4-8 280 * no defines for them in headers 281 */ 282 speed = linkstat & 0xf; 283 linkstat >>= 4; 284 linkstat &= 0x1f; 285 dd->lbus_width = linkstat; 286 287 switch (speed) { 288 case 1: 289 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 290 break; 291 case 2: 292 dd->lbus_speed = 5000; /* Gen1, 5GHz */ 293 break; 294 default: /* not defined, assume gen1 */ 295 dd->lbus_speed = 2500; 296 break; 297 } 298 299 /* 300 * Check against expected pcie width and complain if "wrong" 301 * on first initialization, not afterwards (i.e., reset). 302 */ 303 if (minw && linkstat < minw) 304 qib_dev_err(dd, 305 "PCIe width %u (x%u HCA), performance reduced\n", 306 linkstat, minw); 307 308 qib_tune_pcie_caps(dd); 309 310 qib_tune_pcie_coalesce(dd); 311 312bail: 313 /* fill in string, even on errors */ 314 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 315 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width); 316 return ret; 317} 318 319/* 320 * Setup pcie interrupt stuff again after a reset. I'd like to just call 321 * pci_enable_msi() again for msi, but when I do that, 322 * the MSI enable bit doesn't get set in the command word, and 323 * we switch to to a different interrupt vector, which is confusing, 324 * so I instead just do it all inline. Perhaps somehow can tie this 325 * into the PCIe hotplug support at some point 326 */ 327int qib_reinit_intr(struct qib_devdata *dd) 328{ 329 int pos; 330 u16 control; 331 int ret = 0; 332 333 /* If we aren't using MSI, don't restore it */ 334 if (!dd->msi_lo) 335 goto bail; 336 337 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI); 338 if (!pos) { 339 qib_dev_err(dd, "Can't find MSI capability, " 340 "can't restore MSI settings\n"); 341 ret = 0; 342 /* nothing special for MSIx, just MSI */ 343 goto bail; 344 } 345 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, 346 dd->msi_lo); 347 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, 348 dd->msi_hi); 349 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); 350 if (!(control & PCI_MSI_FLAGS_ENABLE)) { 351 control |= PCI_MSI_FLAGS_ENABLE; 352 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, 353 control); 354 } 355 /* now rewrite the data (vector) info */ 356 pci_write_config_word(dd->pcidev, pos + 357 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), 358 dd->msi_data); 359 ret = 1; 360bail: 361 if (!ret && (dd->flags & QIB_HAS_INTX)) { 362 qib_enable_intx(dd->pcidev); 363 ret = 1; 364 } 365 366 /* and now set the pci master bit again */ 367 pci_set_master(dd->pcidev); 368 369 return ret; 370} 371 372/* 373 * Disable msi interrupt if enabled, and clear msi_lo. 374 * This is used primarily for the fallback to INTx, but 375 * is also used in reinit after reset, and during cleanup. 376 */ 377void qib_nomsi(struct qib_devdata *dd) 378{ 379 dd->msi_lo = 0; 380 pci_disable_msi(dd->pcidev); 381} 382 383/* 384 * Same as qib_nosmi, but for MSIx. 385 */ 386void qib_nomsix(struct qib_devdata *dd) 387{ 388 pci_disable_msix(dd->pcidev); 389} 390 391/* 392 * Similar to pci_intx(pdev, 1), except that we make sure 393 * msi(x) is off. 394 */ 395void qib_enable_intx(struct pci_dev *pdev) 396{ 397 u16 cw, new; 398 int pos; 399 400 /* first, turn on INTx */ 401 pci_read_config_word(pdev, PCI_COMMAND, &cw); 402 new = cw & ~PCI_COMMAND_INTX_DISABLE; 403 if (new != cw) 404 pci_write_config_word(pdev, PCI_COMMAND, new); 405 406 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 407 if (pos) { 408 /* then turn off MSI */ 409 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw); 410 new = cw & ~PCI_MSI_FLAGS_ENABLE; 411 if (new != cw) 412 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new); 413 } 414 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 415 if (pos) { 416 /* then turn off MSIx */ 417 pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw); 418 new = cw & ~PCI_MSIX_FLAGS_ENABLE; 419 if (new != cw) 420 pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new); 421 } 422} 423 424/* 425 * These two routines are helper routines for the device reset code 426 * to move all the pcie code out of the chip-specific driver code. 427 */ 428void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline) 429{ 430 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd); 431 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); 432 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); 433} 434 435void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline) 436{ 437 int r; 438 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 439 dd->pcibar0); 440 if (r) 441 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r); 442 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 443 dd->pcibar1); 444 if (r) 445 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r); 446 /* now re-enable memory access, and restore cosmetic settings */ 447 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd); 448 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); 449 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); 450 r = pci_enable_device(dd->pcidev); 451 if (r) 452 qib_dev_err(dd, "pci_enable_device failed after " 453 "reset: %d\n", r); 454} 455 456/* code to adjust PCIe capabilities. */ 457 458static int fld2val(int wd, int mask) 459{ 460 int lsbmask; 461 462 if (!mask) 463 return 0; 464 wd &= mask; 465 lsbmask = mask ^ (mask & (mask - 1)); 466 wd /= lsbmask; 467 return wd; 468} 469 470static int val2fld(int wd, int mask) 471{ 472 int lsbmask; 473 474 if (!mask) 475 return 0; 476 lsbmask = mask ^ (mask & (mask - 1)); 477 wd *= lsbmask; 478 return wd; 479} 480 481static int qib_pcie_coalesce; 482module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO); 483MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets"); 484 485/* 486 * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300 487 * chipsets. This is known to be unsafe for some revisions of some 488 * of these chipsets, with some BIOS settings, and enabling it on those 489 * systems may result in the system crashing, and/or data corruption. 490 */ 491static int qib_tune_pcie_coalesce(struct qib_devdata *dd) 492{ 493 int r; 494 struct pci_dev *parent; 495 int ppos; 496 u16 devid; 497 u32 mask, bits, val; 498 499 if (!qib_pcie_coalesce) 500 return 0; 501 502 /* Find out supported and configured values for parent (root) */ 503 parent = dd->pcidev->bus->self; 504 if (parent->bus->parent) { 505 qib_devinfo(dd->pcidev, "Parent not root\n"); 506 return 1; 507 } 508 ppos = pci_find_capability(parent, PCI_CAP_ID_EXP); 509 if (!ppos) 510 return 1; 511 if (parent->vendor != 0x8086) 512 return 1; 513 514 /* 515 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1 516 * - bit 11: COALESCE_FORCE: need to set to 0 517 * - bit 10: COALESCE_EN: need to set to 1 518 * (but limitations on some on some chipsets) 519 * 520 * On the Intel 5000, 5100, and 7300 chipsets, there is 521 * also: - bit 25:24: COALESCE_MODE, need to set to 0 522 */ 523 devid = parent->device; 524 if (devid >= 0x25e2 && devid <= 0x25fa) { 525 u8 rev; 526 527 /* 5000 P/V/X/Z */ 528 pci_read_config_byte(parent, PCI_REVISION_ID, &rev); 529 if (rev <= 0xb2) 530 bits = 1U << 10; 531 else 532 bits = 7U << 10; 533 mask = (3U << 24) | (7U << 10); 534 } else if (devid >= 0x65e2 && devid <= 0x65fa) { 535 /* 5100 */ 536 bits = 1U << 10; 537 mask = (3U << 24) | (7U << 10); 538 } else if (devid >= 0x4021 && devid <= 0x402e) { 539 /* 5400 */ 540 bits = 7U << 10; 541 mask = 7U << 10; 542 } else if (devid >= 0x3604 && devid <= 0x360a) { 543 /* 7300 */ 544 bits = 7U << 10; 545 mask = (3U << 24) | (7U << 10); 546 } else { 547 /* not one of the chipsets that we know about */ 548 return 1; 549 } 550 pci_read_config_dword(parent, 0x48, &val); 551 val &= ~mask; 552 val |= bits; 553 r = pci_write_config_dword(parent, 0x48, val); 554 return 0; 555} 556 557/* 558 * BIOS may not set PCIe bus-utilization parameters for best performance. 559 * Check and optionally adjust them to maximize our throughput. 560 */ 561static int qib_pcie_caps; 562module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO); 563MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (4lsb), ReadReq (D4..7)"); 564 565static int qib_tune_pcie_caps(struct qib_devdata *dd) 566{ 567 int ret = 1; /* Assume the worst */ 568 struct pci_dev *parent; 569 int ppos, epos; 570 u16 pcaps, pctl, ecaps, ectl; 571 int rc_sup, ep_sup; 572 int rc_cur, ep_cur; 573 574 /* Find out supported and configured values for parent (root) */ 575 parent = dd->pcidev->bus->self; 576 if (parent->bus->parent) { 577 qib_devinfo(dd->pcidev, "Parent not root\n"); 578 goto bail; 579 } 580 ppos = pci_find_capability(parent, PCI_CAP_ID_EXP); 581 if (ppos) { 582 pci_read_config_word(parent, ppos + PCI_EXP_DEVCAP, &pcaps); 583 pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl); 584 } else 585 goto bail; 586 /* Find out supported and configured values for endpoint (us) */ 587 epos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP); 588 if (epos) { 589 pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCAP, &ecaps); 590 pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, &ectl); 591 } else 592 goto bail; 593 ret = 0; 594 /* Find max payload supported by root, endpoint */ 595 rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD); 596 ep_sup = fld2val(ecaps, PCI_EXP_DEVCAP_PAYLOAD); 597 if (rc_sup > ep_sup) 598 rc_sup = ep_sup; 599 600 rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_PAYLOAD); 601 ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_PAYLOAD); 602 603 /* If Supported greater than limit in module param, limit it */ 604 if (rc_sup > (qib_pcie_caps & 7)) 605 rc_sup = qib_pcie_caps & 7; 606 /* If less than (allowed, supported), bump root payload */ 607 if (rc_sup > rc_cur) { 608 rc_cur = rc_sup; 609 pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) | 610 val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD); 611 pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl); 612 } 613 /* If less than (allowed, supported), bump endpoint payload */ 614 if (rc_sup > ep_cur) { 615 ep_cur = rc_sup; 616 ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) | 617 val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD); 618 pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl); 619 } 620 621 /* 622 * Now the Read Request size. 623 * No field for max supported, but PCIe spec limits it to 4096, 624 * which is code '5' (log2(4096) - 7) 625 */ 626 rc_sup = 5; 627 if (rc_sup > ((qib_pcie_caps >> 4) & 7)) 628 rc_sup = (qib_pcie_caps >> 4) & 7; 629 rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_READRQ); 630 ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_READRQ); 631 632 if (rc_sup > rc_cur) { 633 rc_cur = rc_sup; 634 pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) | 635 val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ); 636 pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl); 637 } 638 if (rc_sup > ep_cur) { 639 ep_cur = rc_sup; 640 ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) | 641 val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ); 642 pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl); 643 } 644bail: 645 return ret; 646} 647/* End of PCIe capability tuning */ 648 649/* 650 * From here through qib_pci_err_handler definition is invoked via 651 * PCI error infrastructure, registered via pci 652 */ 653static pci_ers_result_t 654qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 655{ 656 struct qib_devdata *dd = pci_get_drvdata(pdev); 657 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 658 659 switch (state) { 660 case pci_channel_io_normal: 661 qib_devinfo(pdev, "State Normal, ignoring\n"); 662 break; 663 664 case pci_channel_io_frozen: 665 qib_devinfo(pdev, "State Frozen, requesting reset\n"); 666 pci_disable_device(pdev); 667 ret = PCI_ERS_RESULT_NEED_RESET; 668 break; 669 670 case pci_channel_io_perm_failure: 671 qib_devinfo(pdev, "State Permanent Failure, disabling\n"); 672 if (dd) { 673 /* no more register accesses! */ 674 dd->flags &= ~QIB_PRESENT; 675 qib_disable_after_error(dd); 676 } 677 /* else early, or other problem */ 678 ret = PCI_ERS_RESULT_DISCONNECT; 679 break; 680 681 default: /* shouldn't happen */ 682 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n", 683 state); 684 break; 685 } 686 return ret; 687} 688 689static pci_ers_result_t 690qib_pci_mmio_enabled(struct pci_dev *pdev) 691{ 692 u64 words = 0U; 693 struct qib_devdata *dd = pci_get_drvdata(pdev); 694 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 695 696 if (dd && dd->pport) { 697 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV); 698 if (words == ~0ULL) 699 ret = PCI_ERS_RESULT_NEED_RESET; 700 } 701 qib_devinfo(pdev, "QIB mmio_enabled function called, " 702 "read wordscntr %Lx, returning %d\n", words, ret); 703 return ret; 704} 705 706static pci_ers_result_t 707qib_pci_slot_reset(struct pci_dev *pdev) 708{ 709 qib_devinfo(pdev, "QIB link_reset function called, ignored\n"); 710 return PCI_ERS_RESULT_CAN_RECOVER; 711} 712 713static pci_ers_result_t 714qib_pci_link_reset(struct pci_dev *pdev) 715{ 716 qib_devinfo(pdev, "QIB link_reset function called, ignored\n"); 717 return PCI_ERS_RESULT_CAN_RECOVER; 718} 719 720static void 721qib_pci_resume(struct pci_dev *pdev) 722{ 723 struct qib_devdata *dd = pci_get_drvdata(pdev); 724 qib_devinfo(pdev, "QIB resume function called\n"); 725 pci_cleanup_aer_uncorrect_error_status(pdev); 726 /* 727 * Running jobs will fail, since it's asynchronous 728 * unlike sysfs-requested reset. Better than 729 * doing nothing. 730 */ 731 qib_init(dd, 1); /* same as re-init after reset */ 732} 733 734struct pci_error_handlers qib_pci_err_handler = { 735 .error_detected = qib_pci_error_detected, 736 .mmio_enabled = qib_pci_mmio_enabled, 737 .link_reset = qib_pci_link_reset, 738 .slot_reset = qib_pci_slot_reset, 739 .resume = qib_pci_resume, 740}; 741