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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/infiniband/hw/mthca/
1/*
2 * Copyright (c) 2004 Topspin Communications.  All rights reserved.
3 * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses.  You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 *     Redistribution and use in source and binary forms, with or
13 *     without modification, are permitted provided that the following
14 *     conditions are met:
15 *
16 *      - Redistributions of source code must retain the above
17 *        copyright notice, this list of conditions and the following
18 *        disclaimer.
19 *
20 *      - Redistributions in binary form must reproduce the above
21 *        copyright notice, this list of conditions and the following
22 *        disclaimer in the documentation and/or other materials
23 *        provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef MTHCA_PROVIDER_H
36#define MTHCA_PROVIDER_H
37
38#include <rdma/ib_verbs.h>
39#include <rdma/ib_pack.h>
40
41#define MTHCA_MPT_FLAG_ATOMIC        (1 << 14)
42#define MTHCA_MPT_FLAG_REMOTE_WRITE  (1 << 13)
43#define MTHCA_MPT_FLAG_REMOTE_READ   (1 << 12)
44#define MTHCA_MPT_FLAG_LOCAL_WRITE   (1 << 11)
45#define MTHCA_MPT_FLAG_LOCAL_READ    (1 << 10)
46
47struct mthca_buf_list {
48	void *buf;
49	DEFINE_DMA_UNMAP_ADDR(mapping);
50};
51
52union mthca_buf {
53	struct mthca_buf_list direct;
54	struct mthca_buf_list *page_list;
55};
56
57struct mthca_uar {
58	unsigned long pfn;
59	int           index;
60};
61
62struct mthca_user_db_table;
63
64struct mthca_ucontext {
65	struct ib_ucontext          ibucontext;
66	struct mthca_uar            uar;
67	struct mthca_user_db_table *db_tab;
68	int			    reg_mr_warned;
69};
70
71struct mthca_mtt;
72
73struct mthca_mr {
74	struct ib_mr      ibmr;
75	struct ib_umem   *umem;
76	struct mthca_mtt *mtt;
77};
78
79struct mthca_fmr {
80	struct ib_fmr      ibmr;
81	struct ib_fmr_attr attr;
82	struct mthca_mtt  *mtt;
83	int                maps;
84	union {
85		struct {
86			struct mthca_mpt_entry __iomem *mpt;
87			u64 __iomem *mtts;
88		} tavor;
89		struct {
90			struct mthca_mpt_entry *mpt;
91			__be64 *mtts;
92			dma_addr_t dma_handle;
93		} arbel;
94	} mem;
95};
96
97struct mthca_pd {
98	struct ib_pd    ibpd;
99	u32             pd_num;
100	atomic_t        sqp_count;
101	struct mthca_mr ntmr;
102	int             privileged;
103};
104
105struct mthca_eq {
106	struct mthca_dev      *dev;
107	int                    eqn;
108	u32                    eqn_mask;
109	u32                    cons_index;
110	u16                    msi_x_vector;
111	u16                    msi_x_entry;
112	int                    have_irq;
113	int                    nent;
114	struct mthca_buf_list *page_list;
115	struct mthca_mr        mr;
116	char		       irq_name[IB_DEVICE_NAME_MAX];
117};
118
119struct mthca_av;
120
121enum mthca_ah_type {
122	MTHCA_AH_ON_HCA,
123	MTHCA_AH_PCI_POOL,
124	MTHCA_AH_KMALLOC
125};
126
127struct mthca_ah {
128	struct ib_ah       ibah;
129	enum mthca_ah_type type;
130	u32                key;
131	struct mthca_av   *av;
132	dma_addr_t         avdma;
133};
134
135/*
136 * Quick description of our CQ/QP locking scheme:
137 *
138 * We have one global lock that protects dev->cq/qp_table.  Each
139 * struct mthca_cq/qp also has its own lock.  An individual qp lock
140 * may be taken inside of an individual cq lock.  Both cqs attached to
141 * a qp may be locked, with the cq with the lower cqn locked first.
142 * No other nesting should be done.
143 *
144 * Each struct mthca_cq/qp also has an ref count, protected by the
145 * corresponding table lock.  The pointer from the cq/qp_table to the
146 * struct counts as one reference.  This reference also is good for
147 * access through the consumer API, so modifying the CQ/QP etc doesn't
148 * need to take another reference.  Access to a QP because of a
149 * completion being polled does not need a reference either.
150 *
151 * Finally, each struct mthca_cq/qp has a wait_queue_head_t for the
152 * destroy function to sleep on.
153 *
154 * This means that access from the consumer API requires nothing but
155 * taking the struct's lock.
156 *
157 * Access because of a completion event should go as follows:
158 * - lock cq/qp_table and look up struct
159 * - increment ref count in struct
160 * - drop cq/qp_table lock
161 * - lock struct, do your thing, and unlock struct
162 * - decrement ref count; if zero, wake up waiters
163 *
164 * To destroy a CQ/QP, we can do the following:
165 * - lock cq/qp_table
166 * - remove pointer and decrement ref count
167 * - unlock cq/qp_table lock
168 * - wait_event until ref count is zero
169 *
170 * It is the consumer's responsibilty to make sure that no QP
171 * operations (WQE posting or state modification) are pending when a
172 * QP is destroyed.  Also, the consumer must make sure that calls to
173 * qp_modify are serialized.  Similarly, the consumer is responsible
174 * for ensuring that no CQ resize operations are pending when a CQ
175 * is destroyed.
176 *
177 * Possible optimizations (wait for profile data to see if/where we
178 * have locks bouncing between CPUs):
179 * - split cq/qp table lock into n separate (cache-aligned) locks,
180 *   indexed (say) by the page in the table
181 * - split QP struct lock into three (one for common info, one for the
182 *   send queue and one for the receive queue)
183 */
184
185struct mthca_cq_buf {
186	union mthca_buf		queue;
187	struct mthca_mr		mr;
188	int			is_direct;
189};
190
191struct mthca_cq_resize {
192	struct mthca_cq_buf	buf;
193	int			cqe;
194	enum {
195		CQ_RESIZE_ALLOC,
196		CQ_RESIZE_READY,
197		CQ_RESIZE_SWAPPED
198	}			state;
199};
200
201struct mthca_cq {
202	struct ib_cq		ibcq;
203	spinlock_t		lock;
204	int			refcount;
205	int			cqn;
206	u32			cons_index;
207	struct mthca_cq_buf	buf;
208	struct mthca_cq_resize *resize_buf;
209	int			is_kernel;
210
211	/* Next fields are Arbel only */
212	int			set_ci_db_index;
213	__be32		       *set_ci_db;
214	int			arm_db_index;
215	__be32		       *arm_db;
216	int			arm_sn;
217
218	wait_queue_head_t	wait;
219	struct mutex		mutex;
220};
221
222struct mthca_srq {
223	struct ib_srq		ibsrq;
224	spinlock_t		lock;
225	int			refcount;
226	int			srqn;
227	int			max;
228	int			max_gs;
229	int			wqe_shift;
230	int			first_free;
231	int			last_free;
232	u16			counter;  /* Arbel only */
233	int			db_index; /* Arbel only */
234	__be32		       *db;       /* Arbel only */
235	void		       *last;
236
237	int			is_direct;
238	u64		       *wrid;
239	union mthca_buf		queue;
240	struct mthca_mr		mr;
241
242	wait_queue_head_t	wait;
243	struct mutex		mutex;
244};
245
246struct mthca_wq {
247	spinlock_t lock;
248	int        max;
249	unsigned   next_ind;
250	unsigned   last_comp;
251	unsigned   head;
252	unsigned   tail;
253	void      *last;
254	int        max_gs;
255	int        wqe_shift;
256
257	int        db_index;	/* Arbel only */
258	__be32    *db;
259};
260
261struct mthca_qp {
262	struct ib_qp           ibqp;
263	int                    refcount;
264	u32                    qpn;
265	int                    is_direct;
266	u8                     port; /* for SQP and memfree use only */
267	u8                     alt_port; /* for memfree use only */
268	u8                     transport;
269	u8                     state;
270	u8                     atomic_rd_en;
271	u8                     resp_depth;
272
273	struct mthca_mr        mr;
274
275	struct mthca_wq        rq;
276	struct mthca_wq        sq;
277	enum ib_sig_type       sq_policy;
278	int                    send_wqe_offset;
279	int                    max_inline_data;
280
281	u64                   *wrid;
282	union mthca_buf	       queue;
283
284	wait_queue_head_t      wait;
285	struct mutex	       mutex;
286};
287
288struct mthca_sqp {
289	struct mthca_qp qp;
290	int             pkey_index;
291	u32             qkey;
292	u32             send_psn;
293	struct ib_ud_header ud_header;
294	int             header_buf_size;
295	void           *header_buf;
296	dma_addr_t      header_dma;
297};
298
299static inline struct mthca_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
300{
301	return container_of(ibucontext, struct mthca_ucontext, ibucontext);
302}
303
304static inline struct mthca_fmr *to_mfmr(struct ib_fmr *ibmr)
305{
306	return container_of(ibmr, struct mthca_fmr, ibmr);
307}
308
309static inline struct mthca_mr *to_mmr(struct ib_mr *ibmr)
310{
311	return container_of(ibmr, struct mthca_mr, ibmr);
312}
313
314static inline struct mthca_pd *to_mpd(struct ib_pd *ibpd)
315{
316	return container_of(ibpd, struct mthca_pd, ibpd);
317}
318
319static inline struct mthca_ah *to_mah(struct ib_ah *ibah)
320{
321	return container_of(ibah, struct mthca_ah, ibah);
322}
323
324static inline struct mthca_cq *to_mcq(struct ib_cq *ibcq)
325{
326	return container_of(ibcq, struct mthca_cq, ibcq);
327}
328
329static inline struct mthca_srq *to_msrq(struct ib_srq *ibsrq)
330{
331	return container_of(ibsrq, struct mthca_srq, ibsrq);
332}
333
334static inline struct mthca_qp *to_mqp(struct ib_qp *ibqp)
335{
336	return container_of(ibqp, struct mthca_qp, ibqp);
337}
338
339static inline struct mthca_sqp *to_msqp(struct mthca_qp *qp)
340{
341	return container_of(qp, struct mthca_sqp, qp);
342}
343
344#endif /* MTHCA_PROVIDER_H */
345