1/* 2 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com> 3 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be> 4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org> 6 * 7 * Inspired by an earlier effort from David S. Miller <davem@redhat.com> 8 */ 9 10#include <linux/module.h> 11#include <linux/types.h> 12#include <linux/kernel.h> 13#include <linux/interrupt.h> 14#include <linux/pci.h> 15#include <linux/delay.h> 16#include <linux/ide.h> 17#include <linux/init.h> 18 19#include <asm/io.h> 20 21#define DRV_NAME "ns87415" 22 23#ifdef CONFIG_SUPERIO 24/* SUPERIO 87560 is a PoS chip that NatSem denies exists. 25 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations 26 * which use the integrated NS87514 cell for CD-ROM support. 27 * i.e we have to support for CD-ROM installs. 28 * See drivers/parisc/superio.c for more gory details. 29 */ 30#include <asm/superio.h> 31 32#define SUPERIO_IDE_MAX_RETRIES 25 33 34/* Because of a defect in Super I/O, all reads of the PCI DMA status 35 * registers, IDE status register and the IDE select register need to be 36 * retried 37 */ 38static u8 superio_ide_inb (unsigned long port) 39{ 40 u8 tmp; 41 int retries = SUPERIO_IDE_MAX_RETRIES; 42 43 /* printk(" [ reading port 0x%x with retry ] ", port); */ 44 45 do { 46 tmp = inb(port); 47 if (tmp == 0) 48 udelay(50); 49 } while (tmp == 0 && retries-- > 0); 50 51 return tmp; 52} 53 54static u8 superio_read_status(ide_hwif_t *hwif) 55{ 56 return superio_ide_inb(hwif->io_ports.status_addr); 57} 58 59static u8 superio_dma_sff_read_status(ide_hwif_t *hwif) 60{ 61 return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS); 62} 63 64static void superio_tf_read(ide_drive_t *drive, struct ide_taskfile *tf, 65 u8 valid) 66{ 67 struct ide_io_ports *io_ports = &drive->hwif->io_ports; 68 69 if (valid & IDE_VALID_ERROR) 70 tf->error = inb(io_ports->feature_addr); 71 if (valid & IDE_VALID_NSECT) 72 tf->nsect = inb(io_ports->nsect_addr); 73 if (valid & IDE_VALID_LBAL) 74 tf->lbal = inb(io_ports->lbal_addr); 75 if (valid & IDE_VALID_LBAM) 76 tf->lbam = inb(io_ports->lbam_addr); 77 if (valid & IDE_VALID_LBAH) 78 tf->lbah = inb(io_ports->lbah_addr); 79 if (valid & IDE_VALID_DEVICE) 80 tf->device = superio_ide_inb(io_ports->device_addr); 81} 82 83static void ns87415_dev_select(ide_drive_t *drive); 84 85static const struct ide_tp_ops superio_tp_ops = { 86 .exec_command = ide_exec_command, 87 .read_status = superio_read_status, 88 .read_altstatus = ide_read_altstatus, 89 .write_devctl = ide_write_devctl, 90 91 .dev_select = ns87415_dev_select, 92 .tf_load = ide_tf_load, 93 .tf_read = superio_tf_read, 94 95 .input_data = ide_input_data, 96 .output_data = ide_output_data, 97}; 98 99static void __devinit superio_init_iops(struct hwif_s *hwif) 100{ 101 struct pci_dev *pdev = to_pci_dev(hwif->dev); 102 u32 dma_stat; 103 u8 port = hwif->channel, tmp; 104 105 dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa); 106 107 /* Clear error/interrupt, enable dma */ 108 tmp = superio_ide_inb(dma_stat); 109 outb(tmp | 0x66, dma_stat); 110} 111#else 112#define superio_dma_sff_read_status ide_dma_sff_read_status 113#endif 114 115static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 }; 116 117/* 118 * This routine either enables/disables (according to IDE_DFLAG_PRESENT) 119 * the IRQ associated with the port, 120 * and selects either PIO or DMA handshaking for the next I/O operation. 121 */ 122static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma) 123{ 124 ide_hwif_t *hwif = drive->hwif; 125 struct pci_dev *dev = to_pci_dev(hwif->dev); 126 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data; 127 unsigned long flags; 128 129 local_irq_save(flags); 130 new = *old; 131 132 /* Adjust IRQ enable bit */ 133 bit = 1 << (8 + hwif->channel); 134 135 if (drive->dev_flags & IDE_DFLAG_PRESENT) 136 new &= ~bit; 137 else 138 new |= bit; 139 140 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */ 141 bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1)); 142 other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1)); 143 new = use_dma ? ((new & ~other) | bit) : (new & ~bit); 144 145 if (new != *old) { 146 unsigned char stat; 147 148 /* 149 * Don't change DMA engine settings while Write Buffers 150 * are busy. 151 */ 152 (void) pci_read_config_byte(dev, 0x43, &stat); 153 while (stat & 0x03) { 154 udelay(1); 155 (void) pci_read_config_byte(dev, 0x43, &stat); 156 } 157 158 *old = new; 159 (void) pci_write_config_dword(dev, 0x40, new); 160 161 /* 162 * And let things settle... 163 */ 164 udelay(10); 165 } 166 167 local_irq_restore(flags); 168} 169 170static void ns87415_dev_select(ide_drive_t *drive) 171{ 172 ns87415_prepare_drive(drive, 173 !!(drive->dev_flags & IDE_DFLAG_USING_DMA)); 174 175 outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr); 176} 177 178static void ns87415_dma_start(ide_drive_t *drive) 179{ 180 ns87415_prepare_drive(drive, 1); 181 ide_dma_start(drive); 182} 183 184static int ns87415_dma_end(ide_drive_t *drive) 185{ 186 ide_hwif_t *hwif = drive->hwif; 187 u8 dma_stat = 0, dma_cmd = 0; 188 189 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); 190 /* get DMA command mode */ 191 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 192 /* stop DMA */ 193 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); 194 /* from ERRATA: clear the INTR & ERROR bits */ 195 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); 196 outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD); 197 198 ns87415_prepare_drive(drive, 0); 199 200 /* verify good DMA status */ 201 return (dma_stat & 7) != 4; 202} 203 204static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) 205{ 206 struct pci_dev *dev = to_pci_dev(hwif->dev); 207 unsigned int ctrl, using_inta; 208 u8 progif; 209#ifdef __sparc_v9__ 210 int timeout; 211 u8 stat; 212#endif 213 214 /* 215 * We cannot probe for IRQ: both ports share common IRQ on INTA. 216 * Also, leave IRQ masked during drive probing, to prevent infinite 217 * interrupts from a potentially floating INTA.. 218 * 219 * IRQs get unmasked in dev_select() when drive is first used. 220 */ 221 (void) pci_read_config_dword(dev, 0x40, &ctrl); 222 (void) pci_read_config_byte(dev, 0x09, &progif); 223 /* is irq in "native" mode? */ 224 using_inta = progif & (1 << (hwif->channel << 1)); 225 if (!using_inta) 226 using_inta = ctrl & (1 << (4 + hwif->channel)); 227 if (hwif->mate) { 228 hwif->select_data = hwif->mate->select_data; 229 } else { 230 hwif->select_data = (unsigned long) 231 &ns87415_control[ns87415_count++]; 232 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */ 233 if (using_inta) 234 ctrl &= ~(1 << 6); /* unmask INTA */ 235 *((unsigned int *)hwif->select_data) = ctrl; 236 (void) pci_write_config_dword(dev, 0x40, ctrl); 237 238 /* 239 * Set prefetch size to 512 bytes for both ports, 240 * but don't turn on/off prefetching here. 241 */ 242 pci_write_config_byte(dev, 0x55, 0xee); 243 244#ifdef __sparc_v9__ 245 timeout = 10000; 246 outb(12, hwif->io_ports.ctl_addr); 247 udelay(10); 248 outb(8, hwif->io_ports.ctl_addr); 249 do { 250 udelay(50); 251 stat = hwif->tp_ops->read_status(hwif); 252 if (stat == 0xff) 253 break; 254 } while ((stat & ATA_BUSY) && --timeout); 255#endif 256 } 257 258 if (!using_inta) 259 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel); 260 261 if (!hwif->dma_base) 262 return; 263 264 outb(0x60, hwif->dma_base + ATA_DMA_STATUS); 265} 266 267static const struct ide_tp_ops ns87415_tp_ops = { 268 .exec_command = ide_exec_command, 269 .read_status = ide_read_status, 270 .read_altstatus = ide_read_altstatus, 271 .write_devctl = ide_write_devctl, 272 273 .dev_select = ns87415_dev_select, 274 .tf_load = ide_tf_load, 275 .tf_read = ide_tf_read, 276 277 .input_data = ide_input_data, 278 .output_data = ide_output_data, 279}; 280 281static const struct ide_dma_ops ns87415_dma_ops = { 282 .dma_host_set = ide_dma_host_set, 283 .dma_setup = ide_dma_setup, 284 .dma_start = ns87415_dma_start, 285 .dma_end = ns87415_dma_end, 286 .dma_test_irq = ide_dma_test_irq, 287 .dma_lost_irq = ide_dma_lost_irq, 288 .dma_timer_expiry = ide_dma_sff_timer_expiry, 289 .dma_sff_read_status = superio_dma_sff_read_status, 290}; 291 292static const struct ide_port_info ns87415_chipset __devinitdata = { 293 .name = DRV_NAME, 294 .init_hwif = init_hwif_ns87415, 295 .tp_ops = &ns87415_tp_ops, 296 .dma_ops = &ns87415_dma_ops, 297 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | 298 IDE_HFLAG_NO_ATAPI_DMA, 299}; 300 301static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) 302{ 303 struct ide_port_info d = ns87415_chipset; 304 305#ifdef CONFIG_SUPERIO 306 if (PCI_SLOT(dev->devfn) == 0xE) { 307 /* Built-in - assume it's under superio. */ 308 d.init_iops = superio_init_iops; 309 d.tp_ops = &superio_tp_ops; 310 } 311#endif 312 return ide_pci_init_one(dev, &d, NULL); 313} 314 315static const struct pci_device_id ns87415_pci_tbl[] = { 316 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 }, 317 { 0, }, 318}; 319MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); 320 321static struct pci_driver ns87415_pci_driver = { 322 .name = "NS87415_IDE", 323 .id_table = ns87415_pci_tbl, 324 .probe = ns87415_init_one, 325 .remove = ide_pci_remove, 326 .suspend = ide_pci_suspend, 327 .resume = ide_pci_resume, 328}; 329 330static int __init ns87415_ide_init(void) 331{ 332 return ide_pci_register_driver(&ns87415_pci_driver); 333} 334 335static void __exit ns87415_ide_exit(void) 336{ 337 pci_unregister_driver(&ns87415_pci_driver); 338} 339 340module_init(ns87415_ide_init); 341module_exit(ns87415_ide_exit); 342 343MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick"); 344MODULE_DESCRIPTION("PCI driver module for NS87415 IDE"); 345MODULE_LICENSE("GPL"); 346