1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26#include <drm/drmP.h> 27#include <drm/drm_crtc_helper.h> 28#include <drm/radeon_drm.h> 29#include <drm/drm_fixed.h> 30#include "radeon.h" 31#include "atom.h" 32 33static void radeon_overscan_setup(struct drm_crtc *crtc, 34 struct drm_display_mode *mode) 35{ 36 struct drm_device *dev = crtc->dev; 37 struct radeon_device *rdev = dev->dev_private; 38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 39 40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 43} 44 45static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 46 struct drm_display_mode *mode) 47{ 48 struct drm_device *dev = crtc->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 51 int xres = mode->hdisplay; 52 int yres = mode->vdisplay; 53 bool hscale = true, vscale = true; 54 int hsync_wid; 55 int vsync_wid; 56 int hsync_start; 57 int blank_width; 58 u32 scale, inc, crtc_more_cntl; 59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 63 64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 65 (RADEON_VERT_STRETCH_RESERVED | 66 RADEON_VERT_AUTO_RATIO_INC); 67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 68 (RADEON_HORZ_FP_LOOP_STRETCH | 69 RADEON_HORZ_AUTO_RATIO_INC); 70 71 crtc_more_cntl = 0; 72 if ((rdev->family == CHIP_RS100) || 73 (rdev->family == CHIP_RS200)) { 74 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 75 } 76 77 78 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 79 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 80 81 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 82 if (!hsync_wid) 83 hsync_wid = 1; 84 hsync_start = mode->crtc_hsync_start - 8; 85 86 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 87 | ((hsync_wid & 0x3f) << 16) 88 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 89 ? RADEON_CRTC_H_SYNC_POL 90 : 0)); 91 92 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 93 | ((mode->crtc_vdisplay - 1) << 16)); 94 95 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 96 if (!vsync_wid) 97 vsync_wid = 1; 98 99 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 100 | ((vsync_wid & 0x1f) << 16) 101 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 102 ? RADEON_CRTC_V_SYNC_POL 103 : 0)); 104 105 fp_horz_vert_active = 0; 106 107 if (native_mode->hdisplay == 0 || 108 native_mode->vdisplay == 0) { 109 hscale = false; 110 vscale = false; 111 } else { 112 if (xres > native_mode->hdisplay) 113 xres = native_mode->hdisplay; 114 if (yres > native_mode->vdisplay) 115 yres = native_mode->vdisplay; 116 117 if (xres == native_mode->hdisplay) 118 hscale = false; 119 if (yres == native_mode->vdisplay) 120 vscale = false; 121 } 122 123 switch (radeon_crtc->rmx_type) { 124 case RMX_FULL: 125 case RMX_ASPECT: 126 if (!hscale) 127 fp_horz_stretch |= ((xres/8-1) << 16); 128 else { 129 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 130 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 131 / native_mode->hdisplay + 1; 132 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 133 RADEON_HORZ_STRETCH_BLEND | 134 RADEON_HORZ_STRETCH_ENABLE | 135 ((native_mode->hdisplay/8-1) << 16)); 136 } 137 138 if (!vscale) 139 fp_vert_stretch |= ((yres-1) << 12); 140 else { 141 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 142 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 143 / native_mode->vdisplay + 1; 144 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 145 RADEON_VERT_STRETCH_ENABLE | 146 RADEON_VERT_STRETCH_BLEND | 147 ((native_mode->vdisplay-1) << 12)); 148 } 149 break; 150 case RMX_CENTER: 151 fp_horz_stretch |= ((xres/8-1) << 16); 152 fp_vert_stretch |= ((yres-1) << 12); 153 154 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 155 RADEON_CRTC_AUTO_VERT_CENTER_EN); 156 157 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 158 if (blank_width > 110) 159 blank_width = 110; 160 161 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 162 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 163 164 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 165 if (!hsync_wid) 166 hsync_wid = 1; 167 168 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 169 | ((hsync_wid & 0x3f) << 16) 170 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 171 ? RADEON_CRTC_H_SYNC_POL 172 : 0)); 173 174 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 175 | ((mode->crtc_vdisplay - 1) << 16)); 176 177 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 178 if (!vsync_wid) 179 vsync_wid = 1; 180 181 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 182 | ((vsync_wid & 0x1f) << 16) 183 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 184 ? RADEON_CRTC_V_SYNC_POL 185 : 0))); 186 187 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 188 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 189 break; 190 case RMX_OFF: 191 default: 192 fp_horz_stretch |= ((xres/8-1) << 16); 193 fp_vert_stretch |= ((yres-1) << 12); 194 break; 195 } 196 197 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 198 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 199 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 200 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 201 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 202 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 203 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 204 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 205} 206 207void radeon_restore_common_regs(struct drm_device *dev) 208{ 209 /* don't need this yet */ 210} 211 212static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 213{ 214 struct radeon_device *rdev = dev->dev_private; 215 int i = 0; 216 217 for (i = 0; 218 (i < 10000 && 219 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 220 i++); 221} 222 223static void radeon_pll_write_update(struct drm_device *dev) 224{ 225 struct radeon_device *rdev = dev->dev_private; 226 227 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 228 229 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 230 RADEON_PPLL_ATOMIC_UPDATE_W, 231 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 232} 233 234static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 235{ 236 struct radeon_device *rdev = dev->dev_private; 237 int i = 0; 238 239 240 for (i = 0; 241 (i < 10000 && 242 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 243 i++); 244} 245 246static void radeon_pll2_write_update(struct drm_device *dev) 247{ 248 struct radeon_device *rdev = dev->dev_private; 249 250 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 251 252 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 253 RADEON_P2PLL_ATOMIC_UPDATE_W, 254 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 255} 256 257static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 258 uint16_t fb_div) 259{ 260 unsigned int vcoFreq; 261 262 if (!ref_div) 263 return 1; 264 265 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 266 267 /* 268 * This is horribly crude: the VCO frequency range is divided into 269 * 3 parts, each part having a fixed PLL gain value. 270 */ 271 if (vcoFreq >= 30000) 272 /* 273 * [300..max] MHz : 7 274 */ 275 return 7; 276 else if (vcoFreq >= 18000) 277 /* 278 * [180..300) MHz : 4 279 */ 280 return 4; 281 else 282 /* 283 * [0..180) MHz : 1 284 */ 285 return 1; 286} 287 288void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 289{ 290 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 291 struct drm_device *dev = crtc->dev; 292 struct radeon_device *rdev = dev->dev_private; 293 uint32_t mask; 294 295 if (radeon_crtc->crtc_id) 296 mask = (RADEON_CRTC2_DISP_DIS | 297 RADEON_CRTC2_VSYNC_DIS | 298 RADEON_CRTC2_HSYNC_DIS | 299 RADEON_CRTC2_DISP_REQ_EN_B); 300 else 301 mask = (RADEON_CRTC_DISPLAY_DIS | 302 RADEON_CRTC_VSYNC_DIS | 303 RADEON_CRTC_HSYNC_DIS); 304 305 switch (mode) { 306 case DRM_MODE_DPMS_ON: 307 radeon_crtc->enabled = true; 308 /* adjust pm to dpms changes BEFORE enabling crtcs */ 309 radeon_pm_compute_clocks(rdev); 310 if (radeon_crtc->crtc_id) 311 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 312 else { 313 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 314 RADEON_CRTC_DISP_REQ_EN_B)); 315 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); 316 } 317 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 318 radeon_crtc_load_lut(crtc); 319 break; 320 case DRM_MODE_DPMS_STANDBY: 321 case DRM_MODE_DPMS_SUSPEND: 322 case DRM_MODE_DPMS_OFF: 323 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 324 if (radeon_crtc->crtc_id) 325 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 326 else { 327 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 328 RADEON_CRTC_DISP_REQ_EN_B)); 329 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); 330 } 331 radeon_crtc->enabled = false; 332 /* adjust pm to dpms changes AFTER disabling crtcs */ 333 radeon_pm_compute_clocks(rdev); 334 break; 335 } 336} 337 338int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 339 struct drm_framebuffer *old_fb) 340{ 341 struct drm_device *dev = crtc->dev; 342 struct radeon_device *rdev = dev->dev_private; 343 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 344 struct radeon_framebuffer *radeon_fb; 345 struct drm_gem_object *obj; 346 struct radeon_bo *rbo; 347 uint64_t base; 348 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 349 uint32_t crtc_pitch, pitch_pixels; 350 uint32_t tiling_flags; 351 int format; 352 uint32_t gen_cntl_reg, gen_cntl_val; 353 int r; 354 355 DRM_DEBUG_KMS("\n"); 356 /* no fb bound */ 357 if (!crtc->fb) { 358 DRM_DEBUG_KMS("No FB bound\n"); 359 return 0; 360 } 361 362 radeon_fb = to_radeon_framebuffer(crtc->fb); 363 364 switch (crtc->fb->bits_per_pixel) { 365 case 8: 366 format = 2; 367 break; 368 case 15: /* 555 */ 369 format = 3; 370 break; 371 case 16: /* 565 */ 372 format = 4; 373 break; 374 case 24: /* RGB */ 375 format = 5; 376 break; 377 case 32: /* xRGB */ 378 format = 6; 379 break; 380 default: 381 return false; 382 } 383 384 /* Pin framebuffer & get tilling informations */ 385 obj = radeon_fb->obj; 386 rbo = obj->driver_private; 387 r = radeon_bo_reserve(rbo, false); 388 if (unlikely(r != 0)) 389 return r; 390 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base); 391 if (unlikely(r != 0)) { 392 radeon_bo_unreserve(rbo); 393 return -EINVAL; 394 } 395 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 396 radeon_bo_unreserve(rbo); 397 if (tiling_flags & RADEON_TILING_MICRO) 398 DRM_ERROR("trying to scanout microtiled buffer\n"); 399 400 /* if scanout was in GTT this really wouldn't work */ 401 /* crtc offset is from display base addr not FB location */ 402 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 403 404 base -= radeon_crtc->legacy_display_base_addr; 405 406 crtc_offset_cntl = 0; 407 408 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); 409 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) + 410 ((crtc->fb->bits_per_pixel * 8) - 1)) / 411 (crtc->fb->bits_per_pixel * 8)); 412 crtc_pitch |= crtc_pitch << 16; 413 414 415 if (tiling_flags & RADEON_TILING_MACRO) { 416 if (ASIC_IS_R300(rdev)) 417 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 418 R300_CRTC_MICRO_TILE_BUFFER_DIS | 419 R300_CRTC_MACRO_TILE_EN); 420 else 421 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 422 } else { 423 if (ASIC_IS_R300(rdev)) 424 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 425 R300_CRTC_MICRO_TILE_BUFFER_DIS | 426 R300_CRTC_MACRO_TILE_EN); 427 else 428 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 429 } 430 431 if (tiling_flags & RADEON_TILING_MACRO) { 432 if (ASIC_IS_R300(rdev)) { 433 crtc_tile_x0_y0 = x | (y << 16); 434 base &= ~0x7ff; 435 } else { 436 int byteshift = crtc->fb->bits_per_pixel >> 4; 437 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 438 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 439 crtc_offset_cntl |= (y % 16); 440 } 441 } else { 442 int offset = y * pitch_pixels + x; 443 switch (crtc->fb->bits_per_pixel) { 444 case 8: 445 offset *= 1; 446 break; 447 case 15: 448 case 16: 449 offset *= 2; 450 break; 451 case 24: 452 offset *= 3; 453 break; 454 case 32: 455 offset *= 4; 456 break; 457 default: 458 return false; 459 } 460 base += offset; 461 } 462 463 base &= ~7; 464 465 if (radeon_crtc->crtc_id == 1) 466 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 467 else 468 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 469 470 gen_cntl_val = RREG32(gen_cntl_reg); 471 gen_cntl_val &= ~(0xf << 8); 472 gen_cntl_val |= (format << 8); 473 WREG32(gen_cntl_reg, gen_cntl_val); 474 475 crtc_offset = (u32)base; 476 477 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 478 479 if (ASIC_IS_R300(rdev)) { 480 if (radeon_crtc->crtc_id) 481 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 482 else 483 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 484 } 485 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 486 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 487 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 488 489 if (old_fb && old_fb != crtc->fb) { 490 radeon_fb = to_radeon_framebuffer(old_fb); 491 rbo = radeon_fb->obj->driver_private; 492 r = radeon_bo_reserve(rbo, false); 493 if (unlikely(r != 0)) 494 return r; 495 radeon_bo_unpin(rbo); 496 radeon_bo_unreserve(rbo); 497 } 498 499 /* Bytes per pixel may have changed */ 500 radeon_bandwidth_update(rdev); 501 502 return 0; 503} 504 505static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 506{ 507 struct drm_device *dev = crtc->dev; 508 struct radeon_device *rdev = dev->dev_private; 509 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 510 struct drm_encoder *encoder; 511 int format; 512 int hsync_start; 513 int hsync_wid; 514 int vsync_wid; 515 uint32_t crtc_h_total_disp; 516 uint32_t crtc_h_sync_strt_wid; 517 uint32_t crtc_v_total_disp; 518 uint32_t crtc_v_sync_strt_wid; 519 bool is_tv = false; 520 521 DRM_DEBUG_KMS("\n"); 522 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 523 if (encoder->crtc == crtc) { 524 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 525 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 526 is_tv = true; 527 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 528 break; 529 } 530 } 531 } 532 533 switch (crtc->fb->bits_per_pixel) { 534 case 8: 535 format = 2; 536 break; 537 case 15: /* 555 */ 538 format = 3; 539 break; 540 case 16: /* 565 */ 541 format = 4; 542 break; 543 case 24: /* RGB */ 544 format = 5; 545 break; 546 case 32: /* xRGB */ 547 format = 6; 548 break; 549 default: 550 return false; 551 } 552 553 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 554 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 555 556 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 557 if (!hsync_wid) 558 hsync_wid = 1; 559 hsync_start = mode->crtc_hsync_start - 8; 560 561 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 562 | ((hsync_wid & 0x3f) << 16) 563 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 564 ? RADEON_CRTC_H_SYNC_POL 565 : 0)); 566 567 /* This works for double scan mode. */ 568 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 569 | ((mode->crtc_vdisplay - 1) << 16)); 570 571 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 572 if (!vsync_wid) 573 vsync_wid = 1; 574 575 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 576 | ((vsync_wid & 0x1f) << 16) 577 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 578 ? RADEON_CRTC_V_SYNC_POL 579 : 0)); 580 581 if (radeon_crtc->crtc_id) { 582 uint32_t crtc2_gen_cntl; 583 uint32_t disp2_merge_cntl; 584 585 /* if TV DAC is enabled for another crtc and keep it enabled */ 586 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 587 crtc2_gen_cntl |= ((format << 8) 588 | RADEON_CRTC2_VSYNC_DIS 589 | RADEON_CRTC2_HSYNC_DIS 590 | RADEON_CRTC2_DISP_DIS 591 | RADEON_CRTC2_DISP_REQ_EN_B 592 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 593 ? RADEON_CRTC2_DBL_SCAN_EN 594 : 0) 595 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 596 ? RADEON_CRTC2_CSYNC_EN 597 : 0) 598 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 599 ? RADEON_CRTC2_INTERLACE_EN 600 : 0)); 601 602 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 603 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 604 crtc2_gen_cntl |= RADEON_CRTC2_EN; 605 606 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 607 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 608 609 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 610 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 611 612 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 613 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 614 } else { 615 uint32_t crtc_gen_cntl; 616 uint32_t crtc_ext_cntl; 617 uint32_t disp_merge_cntl; 618 619 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 620 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 621 | (format << 8) 622 | RADEON_CRTC_DISP_REQ_EN_B 623 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 624 ? RADEON_CRTC_DBL_SCAN_EN 625 : 0) 626 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 627 ? RADEON_CRTC_CSYNC_EN 628 : 0) 629 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 630 ? RADEON_CRTC_INTERLACE_EN 631 : 0)); 632 633 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 634 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 635 crtc_gen_cntl |= RADEON_CRTC_EN; 636 637 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 638 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 639 RADEON_CRTC_VSYNC_DIS | 640 RADEON_CRTC_HSYNC_DIS | 641 RADEON_CRTC_DISPLAY_DIS); 642 643 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 644 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 645 646 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 647 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 648 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 649 } 650 651 if (is_tv) 652 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 653 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 654 &crtc_v_sync_strt_wid); 655 656 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 657 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 658 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 659 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 660 661 return true; 662} 663 664static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 665{ 666 struct drm_device *dev = crtc->dev; 667 struct radeon_device *rdev = dev->dev_private; 668 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 669 struct drm_encoder *encoder; 670 uint32_t feedback_div = 0; 671 uint32_t frac_fb_div = 0; 672 uint32_t reference_div = 0; 673 uint32_t post_divider = 0; 674 uint32_t freq = 0; 675 uint8_t pll_gain; 676 bool use_bios_divs = false; 677 /* PLL registers */ 678 uint32_t pll_ref_div = 0; 679 uint32_t pll_fb_post_div = 0; 680 uint32_t htotal_cntl = 0; 681 bool is_tv = false; 682 struct radeon_pll *pll; 683 684 struct { 685 int divider; 686 int bitvalue; 687 } *post_div, post_divs[] = { 688 /* From RAGE 128 VR/RAGE 128 GL Register 689 * Reference Manual (Technical Reference 690 * Manual P/N RRG-G04100-C Rev. 0.04), page 691 * 3-17 (PLL_DIV_[3:0]). 692 */ 693 { 1, 0 }, /* VCLK_SRC */ 694 { 2, 1 }, /* VCLK_SRC/2 */ 695 { 4, 2 }, /* VCLK_SRC/4 */ 696 { 8, 3 }, /* VCLK_SRC/8 */ 697 { 3, 4 }, /* VCLK_SRC/3 */ 698 { 16, 5 }, /* VCLK_SRC/16 */ 699 { 6, 6 }, /* VCLK_SRC/6 */ 700 { 12, 7 }, /* VCLK_SRC/12 */ 701 { 0, 0 } 702 }; 703 704 if (radeon_crtc->crtc_id) 705 pll = &rdev->clock.p2pll; 706 else 707 pll = &rdev->clock.p1pll; 708 709 pll->flags = RADEON_PLL_LEGACY; 710 if (radeon_new_pll == 1) 711 pll->algo = PLL_ALGO_NEW; 712 else 713 pll->algo = PLL_ALGO_LEGACY; 714 715 if (mode->clock > 200000) /* range limits??? */ 716 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 717 else 718 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 719 720 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 721 if (encoder->crtc == crtc) { 722 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 723 724 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 725 is_tv = true; 726 break; 727 } 728 729 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 730 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 731 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 732 if (!rdev->is_atom_bios) { 733 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 734 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 735 if (lvds) { 736 if (lvds->use_bios_dividers) { 737 pll_ref_div = lvds->panel_ref_divider; 738 pll_fb_post_div = (lvds->panel_fb_divider | 739 (lvds->panel_post_divider << 16)); 740 htotal_cntl = 0; 741 use_bios_divs = true; 742 } 743 } 744 } 745 pll->flags |= RADEON_PLL_USE_REF_DIV; 746 } 747 } 748 } 749 750 DRM_DEBUG_KMS("\n"); 751 752 if (!use_bios_divs) { 753 radeon_compute_pll(pll, mode->clock, 754 &freq, &feedback_div, &frac_fb_div, 755 &reference_div, &post_divider); 756 757 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 758 if (post_div->divider == post_divider) 759 break; 760 } 761 762 if (!post_div->divider) 763 post_div = &post_divs[0]; 764 765 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 766 (unsigned)freq, 767 feedback_div, 768 reference_div, 769 post_divider); 770 771 pll_ref_div = reference_div; 772 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 773 774 htotal_cntl = mode->htotal & 0x7; 775 776 } 777 778 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 779 pll_ref_div & 0x3ff, 780 pll_fb_post_div & 0x7ff); 781 782 if (radeon_crtc->crtc_id) { 783 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 784 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 785 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 786 787 if (is_tv) { 788 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 789 &pll_ref_div, &pll_fb_post_div, 790 &pixclks_cntl); 791 } 792 793 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 794 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 795 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 796 797 WREG32_PLL_P(RADEON_P2PLL_CNTL, 798 RADEON_P2PLL_RESET 799 | RADEON_P2PLL_ATOMIC_UPDATE_EN 800 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 801 ~(RADEON_P2PLL_RESET 802 | RADEON_P2PLL_ATOMIC_UPDATE_EN 803 | RADEON_P2PLL_PVG_MASK)); 804 805 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 806 pll_ref_div, 807 ~RADEON_P2PLL_REF_DIV_MASK); 808 809 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 810 pll_fb_post_div, 811 ~RADEON_P2PLL_FB0_DIV_MASK); 812 813 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 814 pll_fb_post_div, 815 ~RADEON_P2PLL_POST0_DIV_MASK); 816 817 radeon_pll2_write_update(dev); 818 radeon_pll2_wait_for_read_update_complete(dev); 819 820 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 821 822 WREG32_PLL_P(RADEON_P2PLL_CNTL, 823 0, 824 ~(RADEON_P2PLL_RESET 825 | RADEON_P2PLL_SLEEP 826 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 827 828 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 829 (unsigned)pll_ref_div, 830 (unsigned)pll_fb_post_div, 831 (unsigned)htotal_cntl, 832 RREG32_PLL(RADEON_P2PLL_CNTL)); 833 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 834 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 835 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 836 (unsigned)((pll_fb_post_div & 837 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 838 839 mdelay(50); /* Let the clock to lock */ 840 841 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 842 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 843 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 844 845 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 846 } else { 847 uint32_t pixclks_cntl; 848 849 850 if (is_tv) { 851 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 852 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 853 &pll_fb_post_div, &pixclks_cntl); 854 } 855 856 if (rdev->flags & RADEON_IS_MOBILITY) { 857 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 858 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 859 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 860 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 861 RADEON_PLL_DIV_SEL, 862 ~(RADEON_PLL_DIV_SEL)); 863 r100_pll_errata_after_index(rdev); 864 return; 865 } 866 } 867 868 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 869 RADEON_VCLK_SRC_SEL_CPUCLK, 870 ~(RADEON_VCLK_SRC_SEL_MASK)); 871 WREG32_PLL_P(RADEON_PPLL_CNTL, 872 RADEON_PPLL_RESET 873 | RADEON_PPLL_ATOMIC_UPDATE_EN 874 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 875 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 876 ~(RADEON_PPLL_RESET 877 | RADEON_PPLL_ATOMIC_UPDATE_EN 878 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 879 | RADEON_PPLL_PVG_MASK)); 880 881 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 882 RADEON_PLL_DIV_SEL, 883 ~(RADEON_PLL_DIV_SEL)); 884 r100_pll_errata_after_index(rdev); 885 886 if (ASIC_IS_R300(rdev) || 887 (rdev->family == CHIP_RS300) || 888 (rdev->family == CHIP_RS400) || 889 (rdev->family == CHIP_RS480)) { 890 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 891 /* When restoring console mode, use saved PPLL_REF_DIV 892 * setting. 893 */ 894 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 895 pll_ref_div, 896 0); 897 } else { 898 /* R300 uses ref_div_acc field as real ref divider */ 899 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 900 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 901 ~R300_PPLL_REF_DIV_ACC_MASK); 902 } 903 } else 904 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 905 pll_ref_div, 906 ~RADEON_PPLL_REF_DIV_MASK); 907 908 WREG32_PLL_P(RADEON_PPLL_DIV_3, 909 pll_fb_post_div, 910 ~RADEON_PPLL_FB3_DIV_MASK); 911 912 WREG32_PLL_P(RADEON_PPLL_DIV_3, 913 pll_fb_post_div, 914 ~RADEON_PPLL_POST3_DIV_MASK); 915 916 radeon_pll_write_update(dev); 917 radeon_pll_wait_for_read_update_complete(dev); 918 919 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 920 921 WREG32_PLL_P(RADEON_PPLL_CNTL, 922 0, 923 ~(RADEON_PPLL_RESET 924 | RADEON_PPLL_SLEEP 925 | RADEON_PPLL_ATOMIC_UPDATE_EN 926 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 927 928 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 929 pll_ref_div, 930 pll_fb_post_div, 931 (unsigned)htotal_cntl, 932 RREG32_PLL(RADEON_PPLL_CNTL)); 933 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 934 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 935 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 936 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 937 938 mdelay(50); /* Let the clock to lock */ 939 940 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 941 RADEON_VCLK_SRC_SEL_PPLLCLK, 942 ~(RADEON_VCLK_SRC_SEL_MASK)); 943 944 if (is_tv) 945 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 946 } 947} 948 949static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 950 struct drm_display_mode *mode, 951 struct drm_display_mode *adjusted_mode) 952{ 953 struct drm_device *dev = crtc->dev; 954 struct radeon_device *rdev = dev->dev_private; 955 956 /* adjust pm to upcoming mode change */ 957 radeon_pm_compute_clocks(rdev); 958 959 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 960 return false; 961 return true; 962} 963 964static int radeon_crtc_mode_set(struct drm_crtc *crtc, 965 struct drm_display_mode *mode, 966 struct drm_display_mode *adjusted_mode, 967 int x, int y, struct drm_framebuffer *old_fb) 968{ 969 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 970 971 /* TODO TV */ 972 radeon_crtc_set_base(crtc, x, y, old_fb); 973 radeon_set_crtc_timing(crtc, adjusted_mode); 974 radeon_set_pll(crtc, adjusted_mode); 975 radeon_overscan_setup(crtc, adjusted_mode); 976 if (radeon_crtc->crtc_id == 0) { 977 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 978 } else { 979 if (radeon_crtc->rmx_type != RMX_OFF) { 980 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 981 } 982 } 983 return 0; 984} 985 986static void radeon_crtc_prepare(struct drm_crtc *crtc) 987{ 988 struct drm_device *dev = crtc->dev; 989 struct drm_crtc *crtci; 990 991 /* 992 * The hardware wedges sometimes if you reconfigure one CRTC 993 * whilst another is running (see fdo bug #24611). 994 */ 995 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 996 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 997} 998 999static void radeon_crtc_commit(struct drm_crtc *crtc) 1000{ 1001 struct drm_device *dev = crtc->dev; 1002 struct drm_crtc *crtci; 1003 1004 /* 1005 * Reenable the CRTCs that should be running. 1006 */ 1007 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1008 if (crtci->enabled) 1009 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1010 } 1011} 1012 1013static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1014 .dpms = radeon_crtc_dpms, 1015 .mode_fixup = radeon_crtc_mode_fixup, 1016 .mode_set = radeon_crtc_mode_set, 1017 .mode_set_base = radeon_crtc_set_base, 1018 .prepare = radeon_crtc_prepare, 1019 .commit = radeon_crtc_commit, 1020 .load_lut = radeon_crtc_load_lut, 1021}; 1022 1023 1024void radeon_legacy_init_crtc(struct drm_device *dev, 1025 struct radeon_crtc *radeon_crtc) 1026{ 1027 if (radeon_crtc->crtc_id == 1) 1028 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1029 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1030} 1031