1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26#include "drmP.h" 27#include "radeon_drm.h" 28#include "radeon.h" 29 30#define CURSOR_WIDTH 64 31#define CURSOR_HEIGHT 64 32 33static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) 34{ 35 struct radeon_device *rdev = crtc->dev->dev_private; 36 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 37 uint32_t cur_lock; 38 39 if (ASIC_IS_DCE4(rdev)) { 40 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); 41 if (lock) 42 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; 43 else 44 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; 45 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 46 } else if (ASIC_IS_AVIVO(rdev)) { 47 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); 48 if (lock) 49 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; 50 else 51 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; 52 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 53 } else { 54 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); 55 if (lock) 56 cur_lock |= RADEON_CUR_LOCK; 57 else 58 cur_lock &= ~RADEON_CUR_LOCK; 59 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); 60 } 61} 62 63static void radeon_hide_cursor(struct drm_crtc *crtc) 64{ 65 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 66 struct radeon_device *rdev = crtc->dev->dev_private; 67 68 if (ASIC_IS_DCE4(rdev)) { 69 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 70 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); 71 } else if (ASIC_IS_AVIVO(rdev)) { 72 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 73 WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 74 } else { 75 switch (radeon_crtc->crtc_id) { 76 case 0: 77 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); 78 break; 79 case 1: 80 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); 81 break; 82 default: 83 return; 84 } 85 WREG32_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN); 86 } 87} 88 89static void radeon_show_cursor(struct drm_crtc *crtc) 90{ 91 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 92 struct radeon_device *rdev = crtc->dev->dev_private; 93 94 if (ASIC_IS_DCE4(rdev)) { 95 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 96 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | 97 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); 98 } else if (ASIC_IS_AVIVO(rdev)) { 99 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 100 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | 101 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 102 } else { 103 switch (radeon_crtc->crtc_id) { 104 case 0: 105 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); 106 break; 107 case 1: 108 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); 109 break; 110 default: 111 return; 112 } 113 114 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | 115 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), 116 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); 117 } 118} 119 120static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, 121 uint32_t gpu_addr) 122{ 123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 124 struct radeon_device *rdev = crtc->dev->dev_private; 125 126 if (ASIC_IS_DCE4(rdev)) { 127 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); 128 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); 129 } else if (ASIC_IS_AVIVO(rdev)) { 130 if (rdev->family >= CHIP_RV770) { 131 if (radeon_crtc->crtc_id) 132 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); 133 else 134 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); 135 } 136 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); 137 } else { 138 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; 139 /* offset is from DISP(2)_BASE_ADDRESS */ 140 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); 141 } 142} 143 144int radeon_crtc_cursor_set(struct drm_crtc *crtc, 145 struct drm_file *file_priv, 146 uint32_t handle, 147 uint32_t width, 148 uint32_t height) 149{ 150 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 151 struct drm_gem_object *obj; 152 uint64_t gpu_addr; 153 int ret; 154 155 if (!handle) { 156 /* turn off cursor */ 157 radeon_hide_cursor(crtc); 158 obj = NULL; 159 goto unpin; 160 } 161 162 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { 163 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 164 return -EINVAL; 165 } 166 167 radeon_crtc->cursor_width = width; 168 radeon_crtc->cursor_height = height; 169 170 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 171 if (!obj) { 172 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); 173 return -ENOENT; 174 } 175 176 ret = radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 177 if (ret) 178 goto fail; 179 180 radeon_lock_cursor(crtc, true); 181 radeon_set_cursor(crtc, obj, gpu_addr); 182 radeon_show_cursor(crtc); 183 radeon_lock_cursor(crtc, false); 184 185unpin: 186 if (radeon_crtc->cursor_bo) { 187 radeon_gem_object_unpin(radeon_crtc->cursor_bo); 188 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); 189 } 190 191 radeon_crtc->cursor_bo = obj; 192 return 0; 193fail: 194 drm_gem_object_unreference_unlocked(obj); 195 196 return ret; 197} 198 199int radeon_crtc_cursor_move(struct drm_crtc *crtc, 200 int x, int y) 201{ 202 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 203 struct radeon_device *rdev = crtc->dev->dev_private; 204 int xorigin = 0, yorigin = 0; 205 int w = radeon_crtc->cursor_width; 206 207 if (x < 0) 208 xorigin = -x + 1; 209 if (y < 0) 210 yorigin = -y + 1; 211 if (xorigin >= CURSOR_WIDTH) 212 xorigin = CURSOR_WIDTH - 1; 213 if (yorigin >= CURSOR_HEIGHT) 214 yorigin = CURSOR_HEIGHT - 1; 215 216 if (ASIC_IS_AVIVO(rdev)) { 217 int i = 0; 218 struct drm_crtc *crtc_p; 219 220 /* avivo cursor are offset into the total surface */ 221 x += crtc->x; 222 y += crtc->y; 223 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 224 225 /* avivo cursor image can't end on 128 pixel boundry or 226 * go past the end of the frame if both crtcs are enabled 227 */ 228 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { 229 if (crtc_p->enabled) 230 i++; 231 } 232 if (i > 1) { 233 int cursor_end, frame_end; 234 235 cursor_end = x - xorigin + w; 236 frame_end = crtc->x + crtc->mode.crtc_hdisplay; 237 if (cursor_end >= frame_end) { 238 w = w - (cursor_end - frame_end); 239 if (!(frame_end & 0x7f)) 240 w--; 241 } else { 242 if (!(cursor_end & 0x7f)) 243 w--; 244 } 245 if (w <= 0) 246 w = 1; 247 } 248 } 249 250 radeon_lock_cursor(crtc, true); 251 if (ASIC_IS_DCE4(rdev)) { 252 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, 253 ((xorigin ? 0 : x) << 16) | 254 (yorigin ? 0 : y)); 255 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 256 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 257 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 258 } else if (ASIC_IS_AVIVO(rdev)) { 259 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, 260 ((xorigin ? 0 : x) << 16) | 261 (yorigin ? 0 : y)); 262 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 263 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 264 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 265 } else { 266 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 267 y *= 2; 268 269 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, 270 (RADEON_CUR_LOCK 271 | (xorigin << 16) 272 | yorigin)); 273 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, 274 (RADEON_CUR_LOCK 275 | ((xorigin ? 0 : x) << 16) 276 | (yorigin ? 0 : y))); 277 /* offset is from DISP(2)_BASE_ADDRESS */ 278 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + 279 (yorigin * 256))); 280 } 281 radeon_lock_cursor(crtc, false); 282 283 return 0; 284} 285