1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef __RADEON_ASIC_H__ 29#define __RADEON_ASIC_H__ 30 31/* 32 * common functions 33 */ 34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45/* 46 * r100,rv100,rs100,rv200,rs200 47 */ 48struct r100_mc_save { 49 u32 GENMO_WT; 50 u32 CRTC_EXT_CNTL; 51 u32 CRTC_GEN_CNTL; 52 u32 CRTC2_GEN_CNTL; 53 u32 CUR_OFFSET; 54 u32 CUR2_OFFSET; 55}; 56int r100_init(struct radeon_device *rdev); 57void r100_fini(struct radeon_device *rdev); 58int r100_suspend(struct radeon_device *rdev); 59int r100_resume(struct radeon_device *rdev); 60uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 61void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 62void r100_vga_set_state(struct radeon_device *rdev, bool state); 63bool r100_gpu_is_lockup(struct radeon_device *rdev); 64int r100_asic_reset(struct radeon_device *rdev); 65u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 66void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 67int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 68void r100_cp_commit(struct radeon_device *rdev); 69void r100_ring_start(struct radeon_device *rdev); 70int r100_irq_set(struct radeon_device *rdev); 71int r100_irq_process(struct radeon_device *rdev); 72void r100_fence_ring_emit(struct radeon_device *rdev, 73 struct radeon_fence *fence); 74int r100_cs_parse(struct radeon_cs_parser *p); 75void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 76uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 77int r100_copy_blit(struct radeon_device *rdev, 78 uint64_t src_offset, 79 uint64_t dst_offset, 80 unsigned num_pages, 81 struct radeon_fence *fence); 82int r100_set_surface_reg(struct radeon_device *rdev, int reg, 83 uint32_t tiling_flags, uint32_t pitch, 84 uint32_t offset, uint32_t obj_size); 85void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 86void r100_bandwidth_update(struct radeon_device *rdev); 87void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 88int r100_ring_test(struct radeon_device *rdev); 89void r100_hpd_init(struct radeon_device *rdev); 90void r100_hpd_fini(struct radeon_device *rdev); 91bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 92void r100_hpd_set_polarity(struct radeon_device *rdev, 93 enum radeon_hpd_id hpd); 94int r100_debugfs_rbbm_init(struct radeon_device *rdev); 95int r100_debugfs_cp_init(struct radeon_device *rdev); 96void r100_cp_disable(struct radeon_device *rdev); 97int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 98void r100_cp_fini(struct radeon_device *rdev); 99int r100_pci_gart_init(struct radeon_device *rdev); 100void r100_pci_gart_fini(struct radeon_device *rdev); 101int r100_pci_gart_enable(struct radeon_device *rdev); 102void r100_pci_gart_disable(struct radeon_device *rdev); 103int r100_debugfs_mc_info_init(struct radeon_device *rdev); 104int r100_gui_wait_for_idle(struct radeon_device *rdev); 105void r100_ib_fini(struct radeon_device *rdev); 106int r100_ib_init(struct radeon_device *rdev); 107void r100_irq_disable(struct radeon_device *rdev); 108void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 109void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 110void r100_vram_init_sizes(struct radeon_device *rdev); 111void r100_wb_disable(struct radeon_device *rdev); 112void r100_wb_fini(struct radeon_device *rdev); 113int r100_wb_init(struct radeon_device *rdev); 114int r100_cp_reset(struct radeon_device *rdev); 115void r100_vga_render_disable(struct radeon_device *rdev); 116void r100_restore_sanity(struct radeon_device *rdev); 117int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 118 struct radeon_cs_packet *pkt, 119 struct radeon_bo *robj); 120int r100_cs_parse_packet0(struct radeon_cs_parser *p, 121 struct radeon_cs_packet *pkt, 122 const unsigned *auth, unsigned n, 123 radeon_packet0_check_t check); 124int r100_cs_packet_parse(struct radeon_cs_parser *p, 125 struct radeon_cs_packet *pkt, 126 unsigned idx); 127void r100_enable_bm(struct radeon_device *rdev); 128void r100_set_common_regs(struct radeon_device *rdev); 129void r100_bm_disable(struct radeon_device *rdev); 130extern bool r100_gui_idle(struct radeon_device *rdev); 131extern void r100_pm_misc(struct radeon_device *rdev); 132extern void r100_pm_prepare(struct radeon_device *rdev); 133extern void r100_pm_finish(struct radeon_device *rdev); 134extern void r100_pm_init_profile(struct radeon_device *rdev); 135extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 136 137/* 138 * r200,rv250,rs300,rv280 139 */ 140extern int r200_copy_dma(struct radeon_device *rdev, 141 uint64_t src_offset, 142 uint64_t dst_offset, 143 unsigned num_pages, 144 struct radeon_fence *fence); 145 146/* 147 * r300,r350,rv350,rv380 148 */ 149extern int r300_init(struct radeon_device *rdev); 150extern void r300_fini(struct radeon_device *rdev); 151extern int r300_suspend(struct radeon_device *rdev); 152extern int r300_resume(struct radeon_device *rdev); 153extern bool r300_gpu_is_lockup(struct radeon_device *rdev); 154extern int r300_asic_reset(struct radeon_device *rdev); 155extern void r300_ring_start(struct radeon_device *rdev); 156extern void r300_fence_ring_emit(struct radeon_device *rdev, 157 struct radeon_fence *fence); 158extern int r300_cs_parse(struct radeon_cs_parser *p); 159extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 160extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 161extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 162extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 163extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 164extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 165 166/* 167 * r420,r423,rv410 168 */ 169extern int r420_init(struct radeon_device *rdev); 170extern void r420_fini(struct radeon_device *rdev); 171extern int r420_suspend(struct radeon_device *rdev); 172extern int r420_resume(struct radeon_device *rdev); 173extern void r420_pm_init_profile(struct radeon_device *rdev); 174 175/* 176 * rs400,rs480 177 */ 178extern int rs400_init(struct radeon_device *rdev); 179extern void rs400_fini(struct radeon_device *rdev); 180extern int rs400_suspend(struct radeon_device *rdev); 181extern int rs400_resume(struct radeon_device *rdev); 182void rs400_gart_tlb_flush(struct radeon_device *rdev); 183int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 184uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 185void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 186 187/* 188 * rs600. 189 */ 190extern int rs600_asic_reset(struct radeon_device *rdev); 191extern int rs600_init(struct radeon_device *rdev); 192extern void rs600_fini(struct radeon_device *rdev); 193extern int rs600_suspend(struct radeon_device *rdev); 194extern int rs600_resume(struct radeon_device *rdev); 195int rs600_irq_set(struct radeon_device *rdev); 196int rs600_irq_process(struct radeon_device *rdev); 197u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 198void rs600_gart_tlb_flush(struct radeon_device *rdev); 199int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 200uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 201void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 202void rs600_bandwidth_update(struct radeon_device *rdev); 203void rs600_hpd_init(struct radeon_device *rdev); 204void rs600_hpd_fini(struct radeon_device *rdev); 205bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 206void rs600_hpd_set_polarity(struct radeon_device *rdev, 207 enum radeon_hpd_id hpd); 208extern void rs600_pm_misc(struct radeon_device *rdev); 209extern void rs600_pm_prepare(struct radeon_device *rdev); 210extern void rs600_pm_finish(struct radeon_device *rdev); 211 212/* 213 * rs690,rs740 214 */ 215int rs690_init(struct radeon_device *rdev); 216void rs690_fini(struct radeon_device *rdev); 217int rs690_resume(struct radeon_device *rdev); 218int rs690_suspend(struct radeon_device *rdev); 219uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 220void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 221void rs690_bandwidth_update(struct radeon_device *rdev); 222 223/* 224 * rv515 225 */ 226int rv515_init(struct radeon_device *rdev); 227void rv515_fini(struct radeon_device *rdev); 228uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 229void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 230void rv515_ring_start(struct radeon_device *rdev); 231uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 232void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 233void rv515_bandwidth_update(struct radeon_device *rdev); 234int rv515_resume(struct radeon_device *rdev); 235int rv515_suspend(struct radeon_device *rdev); 236 237/* 238 * r520,rv530,rv560,rv570,r580 239 */ 240int r520_init(struct radeon_device *rdev); 241int r520_resume(struct radeon_device *rdev); 242 243/* 244 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 245 */ 246int r600_init(struct radeon_device *rdev); 247void r600_fini(struct radeon_device *rdev); 248int r600_suspend(struct radeon_device *rdev); 249int r600_resume(struct radeon_device *rdev); 250void r600_vga_set_state(struct radeon_device *rdev, bool state); 251int r600_wb_init(struct radeon_device *rdev); 252void r600_wb_fini(struct radeon_device *rdev); 253void r600_cp_commit(struct radeon_device *rdev); 254void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 255uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 256void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 257int r600_cs_parse(struct radeon_cs_parser *p); 258void r600_fence_ring_emit(struct radeon_device *rdev, 259 struct radeon_fence *fence); 260int r600_copy_dma(struct radeon_device *rdev, 261 uint64_t src_offset, 262 uint64_t dst_offset, 263 unsigned num_pages, 264 struct radeon_fence *fence); 265int r600_irq_process(struct radeon_device *rdev); 266int r600_irq_set(struct radeon_device *rdev); 267bool r600_gpu_is_lockup(struct radeon_device *rdev); 268int r600_asic_reset(struct radeon_device *rdev); 269int r600_set_surface_reg(struct radeon_device *rdev, int reg, 270 uint32_t tiling_flags, uint32_t pitch, 271 uint32_t offset, uint32_t obj_size); 272void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 273void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 274int r600_ring_test(struct radeon_device *rdev); 275int r600_copy_blit(struct radeon_device *rdev, 276 uint64_t src_offset, uint64_t dst_offset, 277 unsigned num_pages, struct radeon_fence *fence); 278void r600_hpd_init(struct radeon_device *rdev); 279void r600_hpd_fini(struct radeon_device *rdev); 280bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 281void r600_hpd_set_polarity(struct radeon_device *rdev, 282 enum radeon_hpd_id hpd); 283extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 284extern bool r600_gui_idle(struct radeon_device *rdev); 285extern void r600_pm_misc(struct radeon_device *rdev); 286extern void r600_pm_init_profile(struct radeon_device *rdev); 287extern void rs780_pm_init_profile(struct radeon_device *rdev); 288extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 289 290/* 291 * rv770,rv730,rv710,rv740 292 */ 293int rv770_init(struct radeon_device *rdev); 294void rv770_fini(struct radeon_device *rdev); 295int rv770_suspend(struct radeon_device *rdev); 296int rv770_resume(struct radeon_device *rdev); 297extern void rv770_pm_misc(struct radeon_device *rdev); 298 299/* 300 * evergreen 301 */ 302void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 303int evergreen_init(struct radeon_device *rdev); 304void evergreen_fini(struct radeon_device *rdev); 305int evergreen_suspend(struct radeon_device *rdev); 306int evergreen_resume(struct radeon_device *rdev); 307bool evergreen_gpu_is_lockup(struct radeon_device *rdev); 308int evergreen_asic_reset(struct radeon_device *rdev); 309void evergreen_bandwidth_update(struct radeon_device *rdev); 310void evergreen_hpd_init(struct radeon_device *rdev); 311void evergreen_hpd_fini(struct radeon_device *rdev); 312bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 313void evergreen_hpd_set_polarity(struct radeon_device *rdev, 314 enum radeon_hpd_id hpd); 315u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 316int evergreen_irq_set(struct radeon_device *rdev); 317int evergreen_irq_process(struct radeon_device *rdev); 318extern int evergreen_cs_parse(struct radeon_cs_parser *p); 319extern void evergreen_pm_misc(struct radeon_device *rdev); 320extern void evergreen_pm_prepare(struct radeon_device *rdev); 321extern void evergreen_pm_finish(struct radeon_device *rdev); 322 323#endif 324