1/* 2 * Copyright 2009 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25#include "drmP.h" 26 27#include "nouveau_drv.h" 28#include "nouveau_i2c.h" 29#include "nouveau_connector.h" 30#include "nouveau_encoder.h" 31 32static int 33auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size) 34{ 35 struct drm_device *dev = encoder->dev; 36 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 37 struct nouveau_i2c_chan *auxch; 38 int ret; 39 40 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); 41 if (!auxch) 42 return -ENODEV; 43 44 ret = nouveau_dp_auxch(auxch, 9, address, buf, size); 45 if (ret) 46 return ret; 47 48 return 0; 49} 50 51static int 52auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size) 53{ 54 struct drm_device *dev = encoder->dev; 55 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 56 struct nouveau_i2c_chan *auxch; 57 int ret; 58 59 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); 60 if (!auxch) 61 return -ENODEV; 62 63 ret = nouveau_dp_auxch(auxch, 8, address, buf, size); 64 return ret; 65} 66 67static int 68nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd) 69{ 70 struct drm_device *dev = encoder->dev; 71 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 72 uint32_t tmp; 73 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); 74 75 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 76 tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED | 77 NV50_SOR_DP_CTRL_LANE_MASK); 78 tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16; 79 if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN) 80 tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED; 81 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp); 82 83 return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1); 84} 85 86static int 87nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd) 88{ 89 struct drm_device *dev = encoder->dev; 90 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 91 uint32_t tmp; 92 int reg = 0x614300 + (nv_encoder->or * 0x800); 93 94 tmp = nv_rd32(dev, reg); 95 tmp &= 0xfff3ffff; 96 if (cmd == DP_LINK_BW_2_7) 97 tmp |= 0x00040000; 98 nv_wr32(dev, reg, tmp); 99 100 return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1); 101} 102 103static int 104nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern) 105{ 106 struct drm_device *dev = encoder->dev; 107 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 108 uint32_t tmp; 109 uint8_t cmd; 110 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); 111 int ret; 112 113 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 114 tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN; 115 tmp |= (pattern << 24); 116 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp); 117 118 ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1); 119 if (ret) 120 return ret; 121 cmd &= ~DP_TRAINING_PATTERN_MASK; 122 cmd |= (pattern & DP_TRAINING_PATTERN_MASK); 123 return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1); 124} 125 126static int 127nouveau_dp_max_voltage_swing(struct drm_encoder *encoder) 128{ 129 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 130 struct drm_device *dev = encoder->dev; 131 struct bit_displayport_encoder_table_entry *dpse; 132 struct bit_displayport_encoder_table *dpe; 133 int i, dpe_headerlen, max_vs = 0; 134 135 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); 136 if (!dpe) 137 return false; 138 dpse = (void *)((char *)dpe + dpe_headerlen); 139 140 for (i = 0; i < dpe_headerlen; i++, dpse++) { 141 if (dpse->vs_level > max_vs) 142 max_vs = dpse->vs_level; 143 } 144 145 return max_vs; 146} 147 148static int 149nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs) 150{ 151 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 152 struct drm_device *dev = encoder->dev; 153 struct bit_displayport_encoder_table_entry *dpse; 154 struct bit_displayport_encoder_table *dpe; 155 int i, dpe_headerlen, max_pre = 0; 156 157 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); 158 if (!dpe) 159 return false; 160 dpse = (void *)((char *)dpe + dpe_headerlen); 161 162 for (i = 0; i < dpe_headerlen; i++, dpse++) { 163 if (dpse->vs_level != vs) 164 continue; 165 166 if (dpse->pre_level > max_pre) 167 max_pre = dpse->pre_level; 168 } 169 170 return max_pre; 171} 172 173static bool 174nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config) 175{ 176 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 177 struct drm_device *dev = encoder->dev; 178 struct bit_displayport_encoder_table_entry *dpse; 179 struct bit_displayport_encoder_table *dpe; 180 int ret, i, dpe_headerlen, vs = 0, pre = 0; 181 uint8_t request[2]; 182 183 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); 184 if (!dpe) 185 return false; 186 dpse = (void *)((char *)dpe + dpe_headerlen); 187 188 ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2); 189 if (ret) 190 return false; 191 192 NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]); 193 194 /* Keep all lanes at the same level.. */ 195 for (i = 0; i < nv_encoder->dp.link_nr; i++) { 196 int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf; 197 int lane_vs = lane_req & 3; 198 int lane_pre = (lane_req >> 2) & 3; 199 200 if (lane_vs > vs) 201 vs = lane_vs; 202 if (lane_pre > pre) 203 pre = lane_pre; 204 } 205 206 if (vs >= nouveau_dp_max_voltage_swing(encoder)) { 207 vs = nouveau_dp_max_voltage_swing(encoder); 208 vs |= 4; 209 } 210 211 if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) { 212 pre = nouveau_dp_max_pre_emphasis(encoder, vs & 3); 213 pre |= 4; 214 } 215 216 /* Update the configuration for all lanes.. */ 217 for (i = 0; i < nv_encoder->dp.link_nr; i++) 218 config[i] = (pre << 3) | vs; 219 220 return true; 221} 222 223static bool 224nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config) 225{ 226 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 227 struct drm_device *dev = encoder->dev; 228 struct bit_displayport_encoder_table_entry *dpse; 229 struct bit_displayport_encoder_table *dpe; 230 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); 231 int dpe_headerlen, ret, i; 232 233 NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n", 234 config[0], config[1], config[2], config[3]); 235 236 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); 237 if (!dpe) 238 return false; 239 dpse = (void *)((char *)dpe + dpe_headerlen); 240 241 for (i = 0; i < dpe->record_nr; i++, dpse++) { 242 if (dpse->vs_level == (config[0] & 3) && 243 dpse->pre_level == ((config[0] >> 3) & 3)) 244 break; 245 } 246 BUG_ON(i == dpe->record_nr); 247 248 for (i = 0; i < nv_encoder->dp.link_nr; i++) { 249 const int shift[4] = { 16, 8, 0, 24 }; 250 uint32_t mask = 0xff << shift[i]; 251 uint32_t reg0, reg1, reg2; 252 253 reg0 = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask; 254 reg0 |= (dpse->reg0 << shift[i]); 255 reg1 = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask; 256 reg1 |= (dpse->reg1 << shift[i]); 257 reg2 = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff; 258 reg2 |= (dpse->reg2 << 8); 259 nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0); 260 nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1); 261 nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2); 262 } 263 264 ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4); 265 if (ret) 266 return false; 267 268 return true; 269} 270 271bool 272nouveau_dp_link_train(struct drm_encoder *encoder) 273{ 274 struct drm_device *dev = encoder->dev; 275 struct drm_nouveau_private *dev_priv = dev->dev_private; 276 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 277 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 278 struct nouveau_connector *nv_connector; 279 struct bit_displayport_encoder_table *dpe; 280 int dpe_headerlen; 281 uint8_t config[4], status[3]; 282 bool cr_done, cr_max_vs, eq_done; 283 int ret = 0, i, tries, voltage; 284 285 NV_DEBUG_KMS(dev, "link training!!\n"); 286 287 nv_connector = nouveau_encoder_connector_get(nv_encoder); 288 if (!nv_connector) 289 return false; 290 291 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); 292 if (!dpe) { 293 NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or); 294 return false; 295 } 296 297 /* disable hotplug detect, this flips around on some panels during 298 * link training. 299 */ 300 pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false); 301 302 if (dpe->script0) { 303 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or); 304 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0), 305 nv_encoder->dcb); 306 } 307 308train: 309 cr_done = eq_done = false; 310 311 /* set link configuration */ 312 NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n", 313 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr); 314 315 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw); 316 if (ret) 317 return false; 318 319 config[0] = nv_encoder->dp.link_nr; 320 if (nv_encoder->dp.dpcd_version >= 0x11) 321 config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 322 323 ret = nouveau_dp_lane_count_set(encoder, config[0]); 324 if (ret) 325 return false; 326 327 /* clock recovery */ 328 NV_DEBUG_KMS(dev, "\tbegin cr\n"); 329 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1); 330 if (ret) 331 goto stop; 332 333 tries = 0; 334 voltage = -1; 335 memset(config, 0x00, sizeof(config)); 336 for (;;) { 337 if (!nouveau_dp_link_train_commit(encoder, config)) 338 break; 339 340 udelay(100); 341 342 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2); 343 if (ret) 344 break; 345 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n", 346 status[0], status[1]); 347 348 cr_done = true; 349 cr_max_vs = false; 350 for (i = 0; i < nv_encoder->dp.link_nr; i++) { 351 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf; 352 353 if (!(lane & DP_LANE_CR_DONE)) { 354 cr_done = false; 355 if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED) 356 cr_max_vs = true; 357 break; 358 } 359 } 360 361 if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) { 362 voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 363 tries = 0; 364 } 365 366 if (cr_done || cr_max_vs || (++tries == 5)) 367 break; 368 369 if (!nouveau_dp_link_train_adjust(encoder, config)) 370 break; 371 } 372 373 if (!cr_done) 374 goto stop; 375 376 /* channel equalisation */ 377 NV_DEBUG_KMS(dev, "\tbegin eq\n"); 378 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2); 379 if (ret) 380 goto stop; 381 382 for (tries = 0; tries <= 5; tries++) { 383 udelay(400); 384 385 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3); 386 if (ret) 387 break; 388 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n", 389 status[0], status[1]); 390 391 eq_done = true; 392 if (!(status[2] & DP_INTERLANE_ALIGN_DONE)) 393 eq_done = false; 394 395 for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) { 396 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf; 397 398 if (!(lane & DP_LANE_CR_DONE)) { 399 cr_done = false; 400 break; 401 } 402 403 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) || 404 !(lane & DP_LANE_SYMBOL_LOCKED)) { 405 eq_done = false; 406 break; 407 } 408 } 409 410 if (eq_done || !cr_done) 411 break; 412 413 if (!nouveau_dp_link_train_adjust(encoder, config) || 414 !nouveau_dp_link_train_commit(encoder, config)) 415 break; 416 } 417 418stop: 419 /* end link training */ 420 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE); 421 if (ret) 422 return false; 423 424 /* retry at a lower setting, if possible */ 425 if (!ret && !(eq_done && cr_done)) { 426 NV_DEBUG_KMS(dev, "\twe failed\n"); 427 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) { 428 NV_DEBUG_KMS(dev, "retry link training at low rate\n"); 429 nv_encoder->dp.link_bw = DP_LINK_BW_1_62; 430 goto train; 431 } 432 } 433 434 if (dpe->script1) { 435 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or); 436 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1), 437 nv_encoder->dcb); 438 } 439 440 /* re-enable hotplug detect */ 441 pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true); 442 443 return eq_done; 444} 445 446bool 447nouveau_dp_detect(struct drm_encoder *encoder) 448{ 449 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 450 struct drm_device *dev = encoder->dev; 451 uint8_t dpcd[4]; 452 int ret; 453 454 ret = auxch_rd(encoder, 0x0000, dpcd, 4); 455 if (ret) 456 return false; 457 458 NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n" 459 "display: link_bw %d, link_nr %d version 0x%02x\n", 460 nv_encoder->dcb->dpconf.link_bw, 461 nv_encoder->dcb->dpconf.link_nr, 462 dpcd[1], dpcd[2] & 0x0f, dpcd[0]); 463 464 nv_encoder->dp.dpcd_version = dpcd[0]; 465 466 nv_encoder->dp.link_bw = dpcd[1]; 467 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 && 468 !nv_encoder->dcb->dpconf.link_bw) 469 nv_encoder->dp.link_bw = DP_LINK_BW_1_62; 470 471 nv_encoder->dp.link_nr = dpcd[2] & 0xf; 472 if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr) 473 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr; 474 475 return true; 476} 477 478int 479nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 480 uint8_t *data, int data_nr) 481{ 482 struct drm_device *dev = auxch->dev; 483 uint32_t tmp, ctrl, stat = 0, data32[4] = {}; 484 int ret = 0, i, index = auxch->rd; 485 486 NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr); 487 488 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); 489 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000); 490 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); 491 if (!(tmp & 0x01000000)) { 492 NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp); 493 ret = -EIO; 494 goto out; 495 } 496 497 for (i = 0; i < 3; i++) { 498 tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd)); 499 if (tmp & NV50_AUXCH_STAT_STATE_READY) 500 break; 501 udelay(100); 502 } 503 504 if (i == 3) { 505 ret = -EBUSY; 506 goto out; 507 } 508 509 if (!(cmd & 1)) { 510 memcpy(data32, data, data_nr); 511 for (i = 0; i < 4; i++) { 512 NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]); 513 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]); 514 } 515 } 516 517 nv_wr32(dev, NV50_AUXCH_ADDR(index), addr); 518 ctrl = nv_rd32(dev, NV50_AUXCH_CTRL(index)); 519 ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN); 520 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT); 521 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT); 522 523 for (i = 0; i < 16; i++) { 524 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000); 525 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl); 526 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000); 527 if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) { 528 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n", 529 nv_rd32(dev, NV50_AUXCH_CTRL(index))); 530 ret = -EBUSY; 531 goto out; 532 } 533 534 udelay(400); 535 536 stat = nv_rd32(dev, NV50_AUXCH_STAT(index)); 537 if ((stat & NV50_AUXCH_STAT_REPLY_AUX) != 538 NV50_AUXCH_STAT_REPLY_AUX_DEFER) 539 break; 540 } 541 542 if (i == 16) { 543 NV_ERROR(dev, "auxch DEFER too many times, bailing\n"); 544 ret = -EREMOTEIO; 545 goto out; 546 } 547 548 if (cmd & 1) { 549 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) { 550 ret = -EREMOTEIO; 551 goto out; 552 } 553 554 for (i = 0; i < 4; i++) { 555 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i)); 556 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]); 557 } 558 memcpy(data, data32, data_nr); 559 } 560 561out: 562 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); 563 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000); 564 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); 565 if (tmp & 0x01000000) { 566 NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp); 567 ret = -EIO; 568 } 569 570 udelay(400); 571 572 return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY); 573} 574 575static int 576nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 577{ 578 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap; 579 struct drm_device *dev = auxch->dev; 580 struct i2c_msg *msg = msgs; 581 int ret, mcnt = num; 582 583 while (mcnt--) { 584 u8 remaining = msg->len; 585 u8 *ptr = msg->buf; 586 587 while (remaining) { 588 u8 cnt = (remaining > 16) ? 16 : remaining; 589 u8 cmd; 590 591 if (msg->flags & I2C_M_RD) 592 cmd = AUX_I2C_READ; 593 else 594 cmd = AUX_I2C_WRITE; 595 596 if (mcnt || remaining > 16) 597 cmd |= AUX_I2C_MOT; 598 599 ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt); 600 if (ret < 0) 601 return ret; 602 603 switch (ret & NV50_AUXCH_STAT_REPLY_I2C) { 604 case NV50_AUXCH_STAT_REPLY_I2C_ACK: 605 break; 606 case NV50_AUXCH_STAT_REPLY_I2C_NACK: 607 return -EREMOTEIO; 608 case NV50_AUXCH_STAT_REPLY_I2C_DEFER: 609 udelay(100); 610 continue; 611 default: 612 NV_ERROR(dev, "bad auxch reply: 0x%08x\n", ret); 613 return -EREMOTEIO; 614 } 615 616 ptr += cnt; 617 remaining -= cnt; 618 } 619 620 msg++; 621 } 622 623 return num; 624} 625 626static u32 627nouveau_dp_i2c_func(struct i2c_adapter *adap) 628{ 629 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 630} 631 632const struct i2c_algorithm nouveau_dp_i2c_algo = { 633 .master_xfer = nouveau_dp_i2c_xfer, 634 .functionality = nouveau_dp_i2c_func 635}; 636