1/* i830_drv.h -- Private header for the I830 driver -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com> 28 * Jeff Hartmann <jhartmann@valinux.com> 29 * 30 */ 31 32#ifndef _I830_DRV_H_ 33#define _I830_DRV_H_ 34 35/* General customization: 36 */ 37 38#define DRIVER_AUTHOR "VA Linux Systems Inc." 39 40#define DRIVER_NAME "i830" 41#define DRIVER_DESC "Intel 830M" 42#define DRIVER_DATE "20021108" 43 44/* Interface history: 45 * 46 * 1.1: Original. 47 * 1.2: ? 48 * 1.3: New irq emit/wait ioctls. 49 * New pageflip ioctl. 50 * New getparam ioctl. 51 * State for texunits 3&4 in sarea. 52 * New (alternative) layout for texture state. 53 */ 54#define DRIVER_MAJOR 1 55#define DRIVER_MINOR 3 56#define DRIVER_PATCHLEVEL 2 57 58/* Driver will work either way: IRQ's save cpu time when waiting for 59 * the card, but are subject to subtle interactions between bios, 60 * hardware and the driver. 61 */ 62#define USE_IRQS 0 63 64typedef struct drm_i830_buf_priv { 65 u32 *in_use; 66 int my_use_idx; 67 int currently_mapped; 68 void __user *virtual; 69 void *kernel_virtual; 70 drm_local_map_t map; 71} drm_i830_buf_priv_t; 72 73typedef struct _drm_i830_ring_buffer { 74 int tail_mask; 75 unsigned long Start; 76 unsigned long End; 77 unsigned long Size; 78 u8 *virtual_start; 79 int head; 80 int tail; 81 int space; 82 drm_local_map_t map; 83} drm_i830_ring_buffer_t; 84 85typedef struct drm_i830_private { 86 struct drm_local_map *sarea_map; 87 struct drm_local_map *mmio_map; 88 89 drm_i830_sarea_t *sarea_priv; 90 drm_i830_ring_buffer_t ring; 91 92 void *hw_status_page; 93 unsigned long counter; 94 95 dma_addr_t dma_status_page; 96 97 struct drm_buf *mmap_buffer; 98 99 u32 front_di1, back_di1, zi1; 100 101 int back_offset; 102 int depth_offset; 103 int front_offset; 104 int w, h; 105 int pitch; 106 int back_pitch; 107 int depth_pitch; 108 unsigned int cpp; 109 110 int do_boxes; 111 int dma_used; 112 113 int current_page; 114 int page_flipping; 115 116 wait_queue_head_t irq_queue; 117 atomic_t irq_received; 118 atomic_t irq_emitted; 119 120 int use_mi_batchbuffer_start; 121 122} drm_i830_private_t; 123 124long i830_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 125extern struct drm_ioctl_desc i830_ioctls[]; 126extern int i830_max_ioctl; 127 128/* i830_irq.c */ 129extern int i830_irq_emit(struct drm_device *dev, void *data, 130 struct drm_file *file_priv); 131extern int i830_irq_wait(struct drm_device *dev, void *data, 132 struct drm_file *file_priv); 133 134extern irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS); 135extern void i830_driver_irq_preinstall(struct drm_device *dev); 136extern void i830_driver_irq_postinstall(struct drm_device *dev); 137extern void i830_driver_irq_uninstall(struct drm_device *dev); 138extern int i830_driver_load(struct drm_device *, unsigned long flags); 139extern void i830_driver_preclose(struct drm_device *dev, 140 struct drm_file *file_priv); 141extern void i830_driver_lastclose(struct drm_device *dev); 142extern void i830_driver_reclaim_buffers_locked(struct drm_device *dev, 143 struct drm_file *file_priv); 144extern int i830_driver_dma_quiescent(struct drm_device *dev); 145extern int i830_driver_device_is_agp(struct drm_device *dev); 146 147#define I830_READ(reg) DRM_READ32(dev_priv->mmio_map, reg) 148#define I830_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio_map, reg, val) 149#define I830_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg) 150#define I830_WRITE16(reg, val) DRM_WRITE16(dev_priv->mmio_map, reg, val) 151 152#define I830_VERBOSE 0 153 154#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 155 volatile char *virt; 156 157#define BEGIN_LP_RING(n) do { \ 158 if (I830_VERBOSE) \ 159 printk("BEGIN_LP_RING(%d)\n", (n)); \ 160 if (dev_priv->ring.space < n*4) \ 161 i830_wait_ring(dev, n*4, __func__); \ 162 outcount = 0; \ 163 outring = dev_priv->ring.tail; \ 164 ringmask = dev_priv->ring.tail_mask; \ 165 virt = dev_priv->ring.virtual_start; \ 166} while (0) 167 168#define OUT_RING(n) do { \ 169 if (I830_VERBOSE) \ 170 printk(" OUT_RING %x\n", (int)(n)); \ 171 *(volatile unsigned int *)(virt + outring) = n; \ 172 outcount++; \ 173 outring += 4; \ 174 outring &= ringmask; \ 175} while (0) 176 177#define ADVANCE_LP_RING() do { \ 178 if (I830_VERBOSE) \ 179 printk("ADVANCE_LP_RING %x\n", outring); \ 180 dev_priv->ring.tail = outring; \ 181 dev_priv->ring.space -= outcount * 4; \ 182 I830_WRITE(LP_RING + RING_TAIL, outring); \ 183} while (0) 184 185extern int i830_wait_ring(struct drm_device *dev, int n, const char *caller); 186 187#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 188#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 189#define CMD_REPORT_HEAD (7<<23) 190#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 191#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 192 193#define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16)) 194#define LOAD_TEXTURE_MAP0 (1<<11) 195 196#define INST_PARSER_CLIENT 0x00000000 197#define INST_OP_FLUSH 0x02000000 198#define INST_FLUSH_MAP_CACHE 0x00000001 199 200#define BB1_START_ADDR_MASK (~0x7) 201#define BB1_PROTECTED (1<<0) 202#define BB1_UNPROTECTED (0<<0) 203#define BB2_END_ADDR_MASK (~0x7) 204 205#define I830REG_HWSTAM 0x02098 206#define I830REG_INT_IDENTITY_R 0x020a4 207#define I830REG_INT_MASK_R 0x020a8 208#define I830REG_INT_ENABLE_R 0x020a0 209 210#define I830_IRQ_RESERVED ((1<<13)|(3<<2)) 211 212#define LP_RING 0x2030 213#define HP_RING 0x2040 214#define RING_TAIL 0x00 215#define TAIL_ADDR 0x001FFFF8 216#define RING_HEAD 0x04 217#define HEAD_WRAP_COUNT 0xFFE00000 218#define HEAD_WRAP_ONE 0x00200000 219#define HEAD_ADDR 0x001FFFFC 220#define RING_START 0x08 221#define START_ADDR 0x0xFFFFF000 222#define RING_LEN 0x0C 223#define RING_NR_PAGES 0x001FF000 224#define RING_REPORT_MASK 0x00000006 225#define RING_REPORT_64K 0x00000002 226#define RING_REPORT_128K 0x00000004 227#define RING_NO_REPORT 0x00000000 228#define RING_VALID_MASK 0x00000001 229#define RING_VALID 0x00000001 230#define RING_INVALID 0x00000000 231 232#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 233#define SC_UPDATE_SCISSOR (0x1<<1) 234#define SC_ENABLE_MASK (0x1<<0) 235#define SC_ENABLE (0x1<<0) 236 237#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 238#define SCI_YMIN_MASK (0xffff<<16) 239#define SCI_XMIN_MASK (0xffff<<0) 240#define SCI_YMAX_MASK (0xffff<<16) 241#define SCI_XMAX_MASK (0xffff<<0) 242 243#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 244#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 245#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 246#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 247#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 248#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 249#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 250#define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24)) 251 252#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 253 254#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 255#define ASYNC_FLIP (1<<22) 256 257#define CMD_3D (0x3<<29) 258#define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D|(0x1d<<24)|(0x88<<16)) 259#define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16)) 260 261#define BR00_BITBLT_CLIENT 0x40000000 262#define BR00_OP_COLOR_BLT 0x10000000 263#define BR00_OP_SRC_COPY_BLT 0x10C00000 264#define BR13_SOLID_PATTERN 0x80000000 265 266#define BUF_3D_ID_COLOR_BACK (0x3<<24) 267#define BUF_3D_ID_DEPTH (0x7<<24) 268#define BUF_3D_USE_FENCE (1<<23) 269#define BUF_3D_PITCH(x) (((x)/4)<<2) 270 271#define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255) 272#define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8)) 273#define MAP_PALETTE_BOTH (1<<11) 274 275#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4) 276#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) 277#define XY_COLOR_BLT_WRITE_RGB (1<<20) 278 279#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 280#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 281#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 282 283#define MI_BATCH_BUFFER ((0x30<<23)|1) 284#define MI_BATCH_BUFFER_START (0x31<<23) 285#define MI_BATCH_BUFFER_END (0xA<<23) 286#define MI_BATCH_NON_SECURE (1) 287 288#define MI_WAIT_FOR_EVENT ((0x3<<23)) 289#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 290#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 291 292#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 293 294#endif 295