1/* 2 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel 3 * module (C) 2006 Tim Small 4 * 5 * This file may be distributed under the terms of the GNU General 6 * Public License. 7 * 8 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux 9 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and 10 * others. 11 * 12 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>. 13 * 14 * Written with reference to 82443BX Host Bridge Datasheet: 15 * http://www.intel.com/design/chipsets/440/documentation.htm 16 * references to this document given in []. 17 * 18 * This module doesn't support the 440LX, but it may be possible to 19 * make it do so (the 440LX's register definitions are different, but 20 * not completely so - I haven't studied them in enough detail to know 21 * how easy this would be). 22 */ 23 24#include <linux/module.h> 25#include <linux/init.h> 26 27#include <linux/pci.h> 28#include <linux/pci_ids.h> 29 30 31#include <linux/edac.h> 32#include "edac_core.h" 33 34#define I82443_REVISION "0.1" 35 36#define EDAC_MOD_STR "i82443bxgx_edac" 37 38/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory 39 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory 40 * rows" "The 82443BX supports multiple-bit error detection and 41 * single-bit error correction when ECC mode is enabled and 42 * single/multi-bit error detection when correction is disabled. 43 * During writes to the DRAM, the 82443BX generates ECC for the data 44 * on a QWord basis. Partial QWord writes require a read-modify-write 45 * cycle when ECC is enabled." 46*/ 47 48/* "Additionally, the 82443BX ensures that the data is corrected in 49 * main memory so that accumulation of errors is prevented. Another 50 * error within the same QWord would result in a double-bit error 51 * which is unrecoverable. This is known as hardware scrubbing since 52 * it requires no software intervention to correct the data in memory." 53 */ 54 55/* [Also see page 100 (section 4.3), "DRAM Interface"] 56 * [Also see page 112 (section 4.6.1.4), ECC] 57 */ 58 59#define I82443BXGX_NR_CSROWS 8 60#define I82443BXGX_NR_CHANS 1 61#define I82443BXGX_NR_DIMMS 4 62 63/* 82443 PCI Device 0 */ 64#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI 65 * config space offset */ 66#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if 67 * row is non-ECC */ 68#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */ 69 70#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */ 71#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */ 72#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */ 73#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */ 74#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */ 75 76#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6 77 78/* 82443 PCI Device 0 */ 79#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI 80 * config space offset, Error Address 81 * Pointer Register */ 82#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */ 83#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */ 84#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */ 85 86#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI 87 * config space offset. */ 88#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */ 89#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */ 90 91#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI 92 * config space offset. */ 93#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */ 94#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */ 95#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */ 96#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */ 97 98#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI 99 * config space offset. */ 100#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */ 101#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */ 102#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */ 103#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */ 104 105#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI 106 * config space offset. */ 107 108 109struct i82443bxgx_edacmc_error_info { 110 u32 eap; 111}; 112 113static struct edac_pci_ctl_info *i82443bxgx_pci; 114 115static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has 116 * already registered driver 117 */ 118 119static int i82443bxgx_registered = 1; 120 121static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci, 122 struct i82443bxgx_edacmc_error_info 123 *info) 124{ 125 struct pci_dev *pdev; 126 pdev = to_pci_dev(mci->dev); 127 pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap); 128 if (info->eap & I82443BXGX_EAP_OFFSET_SBE) 129 /* Clear error to allow next error to be reported [p.61] */ 130 pci_write_bits32(pdev, I82443BXGX_EAP, 131 I82443BXGX_EAP_OFFSET_SBE, 132 I82443BXGX_EAP_OFFSET_SBE); 133 134 if (info->eap & I82443BXGX_EAP_OFFSET_MBE) 135 /* Clear error to allow next error to be reported [p.61] */ 136 pci_write_bits32(pdev, I82443BXGX_EAP, 137 I82443BXGX_EAP_OFFSET_MBE, 138 I82443BXGX_EAP_OFFSET_MBE); 139} 140 141static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci, 142 struct 143 i82443bxgx_edacmc_error_info 144 *info, int handle_errors) 145{ 146 int error_found = 0; 147 u32 eapaddr, page, pageoffset; 148 149 /* bits 30:12 hold the 4kb block in which the error occurred 150 * [p.61] */ 151 eapaddr = (info->eap & 0xfffff000); 152 page = eapaddr >> PAGE_SHIFT; 153 pageoffset = eapaddr - (page << PAGE_SHIFT); 154 155 if (info->eap & I82443BXGX_EAP_OFFSET_SBE) { 156 error_found = 1; 157 if (handle_errors) 158 edac_mc_handle_ce(mci, page, pageoffset, 159 /* 440BX/GX don't make syndrome information 160 * available */ 161 0, edac_mc_find_csrow_by_page(mci, page), 0, 162 mci->ctl_name); 163 } 164 165 if (info->eap & I82443BXGX_EAP_OFFSET_MBE) { 166 error_found = 1; 167 if (handle_errors) 168 edac_mc_handle_ue(mci, page, pageoffset, 169 edac_mc_find_csrow_by_page(mci, page), 170 mci->ctl_name); 171 } 172 173 return error_found; 174} 175 176static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) 177{ 178 struct i82443bxgx_edacmc_error_info info; 179 180 debugf1("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__); 181 i82443bxgx_edacmc_get_error_info(mci, &info); 182 i82443bxgx_edacmc_process_error_info(mci, &info, 1); 183} 184 185static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, 186 struct pci_dev *pdev, 187 enum edac_type edac_mode, 188 enum mem_type mtype) 189{ 190 struct csrow_info *csrow; 191 int index; 192 u8 drbar, dramc; 193 u32 row_base, row_high_limit, row_high_limit_last; 194 195 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); 196 row_high_limit_last = 0; 197 for (index = 0; index < mci->nr_csrows; index++) { 198 csrow = &mci->csrows[index]; 199 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); 200 debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n", 201 mci->mc_idx, __FILE__, __func__, index, drbar); 202 row_high_limit = ((u32) drbar << 23); 203 /* find the DRAM Chip Select Base address and mask */ 204 debugf1("MC%d: %s: %s() Row=%d, " 205 "Boundry Address=%#0x, Last = %#0x\n", 206 mci->mc_idx, __FILE__, __func__, index, row_high_limit, 207 row_high_limit_last); 208 209 /* 440GX goes to 2GB, represented with a DRB of 0. */ 210 if (row_high_limit_last && !row_high_limit) 211 row_high_limit = 1UL << 31; 212 213 /* This row is empty [p.49] */ 214 if (row_high_limit == row_high_limit_last) 215 continue; 216 row_base = row_high_limit_last; 217 csrow->first_page = row_base >> PAGE_SHIFT; 218 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; 219 csrow->nr_pages = csrow->last_page - csrow->first_page + 1; 220 /* EAP reports in 4kilobyte granularity [61] */ 221 csrow->grain = 1 << 12; 222 csrow->mtype = mtype; 223 csrow->dtype = DEV_UNKNOWN; 224 /* Mode is global to all rows on 440BX */ 225 csrow->edac_mode = edac_mode; 226 row_high_limit_last = row_high_limit; 227 } 228} 229 230static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) 231{ 232 struct mem_ctl_info *mci; 233 u8 dramc; 234 u32 nbxcfg, ecc_mode; 235 enum mem_type mtype; 236 enum edac_type edac_mode; 237 238 debugf0("MC: %s: %s()\n", __FILE__, __func__); 239 240 /* Something is really hosed if PCI config space reads from 241 * the MC aren't working. 242 */ 243 if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg)) 244 return -EIO; 245 246 mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS, 0); 247 248 if (mci == NULL) 249 return -ENOMEM; 250 251 debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci); 252 mci->dev = &pdev->dev; 253 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; 254 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 255 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); 256 switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) { 257 case I82443BXGX_DRAMC_DRAM_IS_EDO: 258 mtype = MEM_EDO; 259 break; 260 case I82443BXGX_DRAMC_DRAM_IS_SDRAM: 261 mtype = MEM_SDR; 262 break; 263 case I82443BXGX_DRAMC_DRAM_IS_RSDRAM: 264 mtype = MEM_RDR; 265 break; 266 default: 267 debugf0("Unknown/reserved DRAM type value " 268 "in DRAMC register!\n"); 269 mtype = -MEM_UNKNOWN; 270 } 271 272 if ((mtype == MEM_SDR) || (mtype == MEM_RDR)) 273 mci->edac_cap = mci->edac_ctl_cap; 274 else 275 mci->edac_cap = EDAC_FLAG_NONE; 276 277 mci->scrub_cap = SCRUB_FLAG_HW_SRC; 278 pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg); 279 ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) & 280 (BIT(0) | BIT(1))); 281 282 mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB) 283 ? SCRUB_HW_SRC : SCRUB_NONE; 284 285 switch (ecc_mode) { 286 case I82443BXGX_NBXCFG_INTEGRITY_NONE: 287 edac_mode = EDAC_NONE; 288 break; 289 case I82443BXGX_NBXCFG_INTEGRITY_EC: 290 edac_mode = EDAC_EC; 291 break; 292 case I82443BXGX_NBXCFG_INTEGRITY_ECC: 293 case I82443BXGX_NBXCFG_INTEGRITY_SCRUB: 294 edac_mode = EDAC_SECDED; 295 break; 296 default: 297 debugf0("%s(): Unknown/reserved ECC state " 298 "in NBXCFG register!\n", __func__); 299 edac_mode = EDAC_UNKNOWN; 300 break; 301 } 302 303 i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype); 304 305 /* Many BIOSes don't clear error flags on boot, so do this 306 * here, or we get "phantom" errors occuring at module-load 307 * time. */ 308 pci_write_bits32(pdev, I82443BXGX_EAP, 309 (I82443BXGX_EAP_OFFSET_SBE | 310 I82443BXGX_EAP_OFFSET_MBE), 311 (I82443BXGX_EAP_OFFSET_SBE | 312 I82443BXGX_EAP_OFFSET_MBE)); 313 314 mci->mod_name = EDAC_MOD_STR; 315 mci->mod_ver = I82443_REVISION; 316 mci->ctl_name = "I82443BXGX"; 317 mci->dev_name = pci_name(pdev); 318 mci->edac_check = i82443bxgx_edacmc_check; 319 mci->ctl_page_to_phys = NULL; 320 321 if (edac_mc_add_mc(mci)) { 322 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 323 goto fail; 324 } 325 326 /* allocating generic PCI control info */ 327 i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 328 if (!i82443bxgx_pci) { 329 printk(KERN_WARNING 330 "%s(): Unable to create PCI control\n", 331 __func__); 332 printk(KERN_WARNING 333 "%s(): PCI error report via EDAC not setup\n", 334 __func__); 335 } 336 337 debugf3("MC: %s: %s(): success\n", __FILE__, __func__); 338 return 0; 339 340fail: 341 edac_mc_free(mci); 342 return -ENODEV; 343} 344 345EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1); 346 347/* returns count (>= 0), or negative on error */ 348static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev, 349 const struct pci_device_id *ent) 350{ 351 int rc; 352 353 debugf0("MC: %s: %s()\n", __FILE__, __func__); 354 355 /* don't need to call pci_enable_device() */ 356 rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); 357 358 if (mci_pdev == NULL) 359 mci_pdev = pci_dev_get(pdev); 360 361 return rc; 362} 363 364static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) 365{ 366 struct mem_ctl_info *mci; 367 368 debugf0("%s: %s()\n", __FILE__, __func__); 369 370 if (i82443bxgx_pci) 371 edac_pci_release_generic_ctl(i82443bxgx_pci); 372 373 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 374 return; 375 376 edac_mc_free(mci); 377} 378 379EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one); 380 381static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = { 382 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)}, 383 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)}, 384 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)}, 385 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)}, 386 {0,} /* 0 terminated list. */ 387}; 388 389MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl); 390 391static struct pci_driver i82443bxgx_edacmc_driver = { 392 .name = EDAC_MOD_STR, 393 .probe = i82443bxgx_edacmc_init_one, 394 .remove = __devexit_p(i82443bxgx_edacmc_remove_one), 395 .id_table = i82443bxgx_pci_tbl, 396}; 397 398static int __init i82443bxgx_edacmc_init(void) 399{ 400 int pci_rc; 401 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 402 opstate_init(); 403 404 pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver); 405 if (pci_rc < 0) 406 goto fail0; 407 408 if (mci_pdev == NULL) { 409 const struct pci_device_id *id = &i82443bxgx_pci_tbl[0]; 410 int i = 0; 411 i82443bxgx_registered = 0; 412 413 while (mci_pdev == NULL && id->vendor != 0) { 414 mci_pdev = pci_get_device(id->vendor, 415 id->device, NULL); 416 i++; 417 id = &i82443bxgx_pci_tbl[i]; 418 } 419 if (!mci_pdev) { 420 debugf0("i82443bxgx pci_get_device fail\n"); 421 pci_rc = -ENODEV; 422 goto fail1; 423 } 424 425 pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl); 426 427 if (pci_rc < 0) { 428 debugf0("i82443bxgx init fail\n"); 429 pci_rc = -ENODEV; 430 goto fail1; 431 } 432 } 433 434 return 0; 435 436fail1: 437 pci_unregister_driver(&i82443bxgx_edacmc_driver); 438 439fail0: 440 if (mci_pdev != NULL) 441 pci_dev_put(mci_pdev); 442 443 return pci_rc; 444} 445 446static void __exit i82443bxgx_edacmc_exit(void) 447{ 448 pci_unregister_driver(&i82443bxgx_edacmc_driver); 449 450 if (!i82443bxgx_registered) 451 i82443bxgx_edacmc_remove_one(mci_pdev); 452 453 if (mci_pdev) 454 pci_dev_put(mci_pdev); 455} 456 457module_init(i82443bxgx_edacmc_init); 458module_exit(i82443bxgx_edacmc_exit); 459 460MODULE_LICENSE("GPL"); 461MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD"); 462MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers"); 463 464module_param(edac_op_state, int, 0444); 465MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 466