1 2/* drivers/atm/firestream.c - FireStream 155 (MB86697) and 3 * FireStream 50 (MB86695) device driver 4 */ 5 6/* Written & (C) 2000 by R.E.Wolff@BitWizard.nl 7 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA 8 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd 9 */ 10 11/* 12 This program is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 2 of the License, or 15 (at your option) any later version. 16 17 This program is distributed in the hope that it will be useful, 18 but WITHOUT ANY WARRANTY; without even the implied warranty of 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 GNU General Public License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; if not, write to the Free Software 24 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 26 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian 27 system and in the file COPYING in the Linux kernel source. 28*/ 29 30 31#include <linux/module.h> 32#include <linux/sched.h> 33#include <linux/kernel.h> 34#include <linux/mm.h> 35#include <linux/pci.h> 36#include <linux/poison.h> 37#include <linux/errno.h> 38#include <linux/atm.h> 39#include <linux/atmdev.h> 40#include <linux/sonet.h> 41#include <linux/skbuff.h> 42#include <linux/netdevice.h> 43#include <linux/delay.h> 44#include <linux/ioport.h> /* for request_region */ 45#include <linux/uio.h> 46#include <linux/init.h> 47#include <linux/capability.h> 48#include <linux/bitops.h> 49#include <linux/slab.h> 50#include <asm/byteorder.h> 51#include <asm/system.h> 52#include <asm/string.h> 53#include <asm/io.h> 54#include <asm/atomic.h> 55#include <asm/uaccess.h> 56#include <linux/wait.h> 57 58#include "firestream.h" 59 60static int loopback = 0; 61static int num=0x5a; 62 63/* According to measurements (but they look suspicious to me!) done in 64 * '97, 37% of the packets are one cell in size. So it pays to have 65 * buffers allocated at that size. A large jump in percentage of 66 * packets occurs at packets around 536 bytes in length. So it also 67 * pays to have those pre-allocated. Unfortunately, we can't fully 68 * take advantage of this as the majority of the packets is likely to 69 * be TCP/IP (As where obviously the measurement comes from) There the 70 * link would be opened with say a 1500 byte MTU, and we can't handle 71 * smaller buffers more efficiently than the larger ones. -- REW 72 */ 73 74/* Due to the way Linux memory management works, specifying "576" as 75 * an allocation size here isn't going to help. They are allocated 76 * from 1024-byte regions anyway. With the size of the sk_buffs (quite 77 * large), it doesn't pay to allocate the smallest size (64) -- REW */ 78 79/* This is all guesswork. Hard numbers to back this up or disprove this, 80 * are appreciated. -- REW */ 81 82/* The last entry should be about 64k. However, the "buffer size" is 83 * passed to the chip in a 16 bit field. I don't know how "65536" 84 * would be interpreted. -- REW */ 85 86#define NP FS_NR_FREE_POOLS 87static int rx_buf_sizes[NP] = {128, 256, 512, 1024, 2048, 4096, 16384, 65520}; 88/* log2: 7 8 9 10 11 12 14 16 */ 89 90/* debug */ 91static int rx_pool_sizes[NP] = {128, 128, 128, 64, 64, 64, 32, 32}; 92/* log2: 10 10 9 8 7 6 5 5 */ 93/* sumlog2: 17 18 18 18 18 18 19 21 */ 94/* mem allocated: 128k 256k 256k 256k 256k 256k 512k 2M */ 95/* tot mem: almost 4M */ 96 97/* NP is shorter, so that it fits on a single line. */ 98#undef NP 99 100 101 102 103/* Optimization hints and tips. 104 105 The FireStream chips are very capable of reducing the amount of 106 "interrupt-traffic" for the CPU. This driver requests an interrupt on EVERY 107 action. You could try to minimize this a bit. 108 109 Besides that, the userspace->kernel copy and the PCI bus are the 110 performance limiting issues for this driver. 111 112 You could queue up a bunch of outgoing packets without telling the 113 FireStream. I'm not sure that's going to win you much though. The 114 Linux layer won't tell us in advance when it's not going to give us 115 any more packets in a while. So this is tricky to implement right without 116 introducing extra delays. 117 118 -- REW 119 */ 120 121 122 123 124/* The strings that define what the RX queue entry is all about. */ 125/* Fujitsu: Please tell me which ones can have a pointer to a 126 freepool descriptor! */ 127static char *res_strings[] = { 128 "RX OK: streaming not EOP", 129 "RX OK: streaming EOP", 130 "RX OK: Single buffer packet", 131 "RX OK: packet mode", 132 "RX OK: F4 OAM (end to end)", 133 "RX OK: F4 OAM (Segment)", 134 "RX OK: F5 OAM (end to end)", 135 "RX OK: F5 OAM (Segment)", 136 "RX OK: RM cell", 137 "RX OK: TRANSP cell", 138 "RX OK: TRANSPC cell", 139 "Unmatched cell", 140 "reserved 12", 141 "reserved 13", 142 "reserved 14", 143 "Unrecognized cell", 144 "reserved 16", 145 "reassemby abort: AAL5 abort", 146 "packet purged", 147 "packet ageing timeout", 148 "channel ageing timeout", 149 "calculated length error", 150 "programmed length limit error", 151 "aal5 crc32 error", 152 "oam transp or transpc crc10 error", 153 "reserved 25", 154 "reserved 26", 155 "reserved 27", 156 "reserved 28", 157 "reserved 29", 158 "reserved 30", 159 "reassembly abort: no buffers", 160 "receive buffer overflow", 161 "change in GFC", 162 "receive buffer full", 163 "low priority discard - no receive descriptor", 164 "low priority discard - missing end of packet", 165 "reserved 41", 166 "reserved 42", 167 "reserved 43", 168 "reserved 44", 169 "reserved 45", 170 "reserved 46", 171 "reserved 47", 172 "reserved 48", 173 "reserved 49", 174 "reserved 50", 175 "reserved 51", 176 "reserved 52", 177 "reserved 53", 178 "reserved 54", 179 "reserved 55", 180 "reserved 56", 181 "reserved 57", 182 "reserved 58", 183 "reserved 59", 184 "reserved 60", 185 "reserved 61", 186 "reserved 62", 187 "reserved 63", 188}; 189 190static char *irq_bitname[] = { 191 "LPCO", 192 "DPCO", 193 "RBRQ0_W", 194 "RBRQ1_W", 195 "RBRQ2_W", 196 "RBRQ3_W", 197 "RBRQ0_NF", 198 "RBRQ1_NF", 199 "RBRQ2_NF", 200 "RBRQ3_NF", 201 "BFP_SC", 202 "INIT", 203 "INIT_ERR", 204 "USCEO", 205 "UPEC0", 206 "VPFCO", 207 "CRCCO", 208 "HECO", 209 "TBRQ_W", 210 "TBRQ_NF", 211 "CTPQ_E", 212 "GFC_C0", 213 "PCI_FTL", 214 "CSQ_W", 215 "CSQ_NF", 216 "EXT_INT", 217 "RXDMA_S" 218}; 219 220 221#define PHY_EOF -1 222#define PHY_CLEARALL -2 223 224struct reginit_item { 225 int reg, val; 226}; 227 228 229static struct reginit_item PHY_NTC_INIT[] __devinitdata = { 230 { PHY_CLEARALL, 0x40 }, 231 { 0x12, 0x0001 }, 232 { 0x13, 0x7605 }, 233 { 0x1A, 0x0001 }, 234 { 0x1B, 0x0005 }, 235 { 0x38, 0x0003 }, 236 { 0x39, 0x0006 }, /* changed here to make loopback */ 237 { 0x01, 0x5262 }, 238 { 0x15, 0x0213 }, 239 { 0x00, 0x0003 }, 240 { PHY_EOF, 0}, /* -1 signals end of list */ 241}; 242 243 244/* Safetyfeature: If the card interrupts more than this number of times 245 in a jiffy (1/100th of a second) then we just disable the interrupt and 246 print a message. This prevents the system from hanging. 247 248 150000 packets per second is close to the limit a PC is going to have 249 anyway. We therefore have to disable this for production. -- REW */ 250#undef IRQ_RATE_LIMIT // 100 251 252/* Interrupts work now. Unlike serial cards, ATM cards don't work all 253 that great without interrupts. -- REW */ 254#undef FS_POLL_FREQ // 100 255 256/* 257 This driver can spew a whole lot of debugging output at you. If you 258 need maximum performance, you should disable the DEBUG define. To 259 aid in debugging in the field, I'm leaving the compile-time debug 260 features enabled, and disable them "runtime". That allows me to 261 instruct people with problems to enable debugging without requiring 262 them to recompile... -- REW 263*/ 264#define DEBUG 265 266#ifdef DEBUG 267#define fs_dprintk(f, str...) if (fs_debug & f) printk (str) 268#else 269#define fs_dprintk(f, str...) /* nothing */ 270#endif 271 272 273static int fs_keystream = 0; 274 275#ifdef DEBUG 276/* I didn't forget to set this to zero before shipping. Hit me with a stick 277 if you get this with the debug default not set to zero again. -- REW */ 278static int fs_debug = 0; 279#else 280#define fs_debug 0 281#endif 282 283#ifdef MODULE 284#ifdef DEBUG 285module_param(fs_debug, int, 0644); 286#endif 287module_param(loopback, int, 0); 288module_param(num, int, 0); 289module_param(fs_keystream, int, 0); 290#endif 291 292 293#define FS_DEBUG_FLOW 0x00000001 294#define FS_DEBUG_OPEN 0x00000002 295#define FS_DEBUG_QUEUE 0x00000004 296#define FS_DEBUG_IRQ 0x00000008 297#define FS_DEBUG_INIT 0x00000010 298#define FS_DEBUG_SEND 0x00000020 299#define FS_DEBUG_PHY 0x00000040 300#define FS_DEBUG_CLEANUP 0x00000080 301#define FS_DEBUG_QOS 0x00000100 302#define FS_DEBUG_TXQ 0x00000200 303#define FS_DEBUG_ALLOC 0x00000400 304#define FS_DEBUG_TXMEM 0x00000800 305#define FS_DEBUG_QSIZE 0x00001000 306 307 308#define func_enter() fs_dprintk(FS_DEBUG_FLOW, "fs: enter %s\n", __func__) 309#define func_exit() fs_dprintk(FS_DEBUG_FLOW, "fs: exit %s\n", __func__) 310 311 312static struct fs_dev *fs_boards = NULL; 313 314#ifdef DEBUG 315 316static void my_hd (void *addr, int len) 317{ 318 int j, ch; 319 unsigned char *ptr = addr; 320 321 while (len > 0) { 322 printk ("%p ", ptr); 323 for (j=0;j < ((len < 16)?len:16);j++) { 324 printk ("%02x %s", ptr[j], (j==7)?" ":""); 325 } 326 for ( ;j < 16;j++) { 327 printk (" %s", (j==7)?" ":""); 328 } 329 for (j=0;j < ((len < 16)?len:16);j++) { 330 ch = ptr[j]; 331 printk ("%c", (ch < 0x20)?'.':((ch > 0x7f)?'.':ch)); 332 } 333 printk ("\n"); 334 ptr += 16; 335 len -= 16; 336 } 337} 338#else /* DEBUG */ 339static void my_hd (void *addr, int len){} 340#endif /* DEBUG */ 341 342/********** free an skb (as per ATM device driver documentation) **********/ 343 344/* Hmm. If this is ATM specific, why isn't there an ATM routine for this? 345 * I copied it over from the ambassador driver. -- REW */ 346 347static inline void fs_kfree_skb (struct sk_buff * skb) 348{ 349 if (ATM_SKB(skb)->vcc->pop) 350 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb); 351 else 352 dev_kfree_skb_any (skb); 353} 354 355 356 357 358/* It seems the ATM forum recommends this horribly complicated 16bit 359 * floating point format. Turns out the Ambassador uses the exact same 360 * encoding. I just copied it over. If Mitch agrees, I'll move it over 361 * to the atm_misc file or something like that. (and remove it from 362 * here and the ambassador driver) -- REW 363 */ 364 365/* The good thing about this format is that it is monotonic. So, 366 a conversion routine need not be very complicated. To be able to 367 round "nearest" we need to take along a few extra bits. Lets 368 put these after 16 bits, so that we can just return the top 16 369 bits of the 32bit number as the result: 370 371 int mr (unsigned int rate, int r) 372 { 373 int e = 16+9; 374 static int round[4]={0, 0, 0xffff, 0x8000}; 375 if (!rate) return 0; 376 while (rate & 0xfc000000) { 377 rate >>= 1; 378 e++; 379 } 380 while (! (rate & 0xfe000000)) { 381 rate <<= 1; 382 e--; 383 } 384 385// Now the mantissa is in positions bit 16-25. Excepf for the "hidden 1" that's in bit 26. 386 rate &= ~0x02000000; 387// Next add in the exponent 388 rate |= e << (16+9); 389// And perform the rounding: 390 return (rate + round[r]) >> 16; 391 } 392 393 14 lines-of-code. Compare that with the 120 that the Ambassador 394 guys needed. (would be 8 lines shorter if I'd try to really reduce 395 the number of lines: 396 397 int mr (unsigned int rate, int r) 398 { 399 int e = 16+9; 400 static int round[4]={0, 0, 0xffff, 0x8000}; 401 if (!rate) return 0; 402 for (; rate & 0xfc000000 ;rate >>= 1, e++); 403 for (;!(rate & 0xfe000000);rate <<= 1, e--); 404 return ((rate & ~0x02000000) | (e << (16+9)) + round[r]) >> 16; 405 } 406 407 Exercise for the reader: Remove one more line-of-code, without 408 cheating. (Just joining two lines is cheating). (I know it's 409 possible, don't think you've beat me if you found it... If you 410 manage to lose two lines or more, keep me updated! ;-) 411 412 -- REW */ 413 414 415#define ROUND_UP 1 416#define ROUND_DOWN 2 417#define ROUND_NEAREST 3 418/********** make rate (not quite as much fun as Horizon) **********/ 419 420static unsigned int make_rate (unsigned int rate, int r, 421 u16 * bits, unsigned int * actual) 422{ 423 unsigned char exp = -1; /* hush gcc */ 424 unsigned int man = -1; /* hush gcc */ 425 426 fs_dprintk (FS_DEBUG_QOS, "make_rate %u", rate); 427 428 /* rates in cells per second, ITU format (nasty 16-bit floating-point) 429 given 5-bit e and 9-bit m: 430 rate = EITHER (1+m/2^9)*2^e OR 0 431 bits = EITHER 1<<14 | e<<9 | m OR 0 432 (bit 15 is "reserved", bit 14 "non-zero") 433 smallest rate is 0 (special representation) 434 largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1) 435 smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0) 436 simple algorithm: 437 find position of top bit, this gives e 438 remove top bit and shift (rounding if feeling clever) by 9-e 439 */ 440 /* Ambassador ucode bug: please don't set bit 14! so 0 rate not 441 representable. // This should move into the ambassador driver 442 when properly merged. -- REW */ 443 444 if (rate > 0xffc00000U) { 445 /* larger than largest representable rate */ 446 447 if (r == ROUND_UP) { 448 return -EINVAL; 449 } else { 450 exp = 31; 451 man = 511; 452 } 453 454 } else if (rate) { 455 /* representable rate */ 456 457 exp = 31; 458 man = rate; 459 460 /* invariant: rate = man*2^(exp-31) */ 461 while (!(man & (1<<31))) { 462 exp = exp - 1; 463 man = man<<1; 464 } 465 466 /* man has top bit set 467 rate = (2^31+(man-2^31))*2^(exp-31) 468 rate = (1+(man-2^31)/2^31)*2^exp 469 */ 470 man = man<<1; 471 man &= 0xffffffffU; /* a nop on 32-bit systems */ 472 /* rate = (1+man/2^32)*2^exp 473 474 exp is in the range 0 to 31, man is in the range 0 to 2^32-1 475 time to lose significance... we want m in the range 0 to 2^9-1 476 rounding presents a minor problem... we first decide which way 477 we are rounding (based on given rounding direction and possibly 478 the bits of the mantissa that are to be discarded). 479 */ 480 481 switch (r) { 482 case ROUND_DOWN: { 483 /* just truncate */ 484 man = man>>(32-9); 485 break; 486 } 487 case ROUND_UP: { 488 /* check all bits that we are discarding */ 489 if (man & (~0U>>9)) { 490 man = (man>>(32-9)) + 1; 491 if (man == (1<<9)) { 492 /* no need to check for round up outside of range */ 493 man = 0; 494 exp += 1; 495 } 496 } else { 497 man = (man>>(32-9)); 498 } 499 break; 500 } 501 case ROUND_NEAREST: { 502 /* check msb that we are discarding */ 503 if (man & (1<<(32-9-1))) { 504 man = (man>>(32-9)) + 1; 505 if (man == (1<<9)) { 506 /* no need to check for round up outside of range */ 507 man = 0; 508 exp += 1; 509 } 510 } else { 511 man = (man>>(32-9)); 512 } 513 break; 514 } 515 } 516 517 } else { 518 /* zero rate - not representable */ 519 520 if (r == ROUND_DOWN) { 521 return -EINVAL; 522 } else { 523 exp = 0; 524 man = 0; 525 } 526 } 527 528 fs_dprintk (FS_DEBUG_QOS, "rate: man=%u, exp=%hu", man, exp); 529 530 if (bits) 531 *bits = /* (1<<14) | */ (exp<<9) | man; 532 533 if (actual) 534 *actual = (exp >= 9) 535 ? (1 << exp) + (man << (exp-9)) 536 : (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp)); 537 538 return 0; 539} 540 541 542 543 544/* FireStream access routines */ 545/* For DEEP-DOWN debugging these can be rigged to intercept accesses to 546 certain registers or to just log all accesses. */ 547 548static inline void write_fs (struct fs_dev *dev, int offset, u32 val) 549{ 550 writel (val, dev->base + offset); 551} 552 553 554static inline u32 read_fs (struct fs_dev *dev, int offset) 555{ 556 return readl (dev->base + offset); 557} 558 559 560 561static inline struct FS_QENTRY *get_qentry (struct fs_dev *dev, struct queue *q) 562{ 563 return bus_to_virt (read_fs (dev, Q_WP(q->offset)) & Q_ADDR_MASK); 564} 565 566 567static void submit_qentry (struct fs_dev *dev, struct queue *q, struct FS_QENTRY *qe) 568{ 569 u32 wp; 570 struct FS_QENTRY *cqe; 571 572 /* udelay (5); */ 573 while ((wp = read_fs (dev, Q_WP (q->offset))) & Q_FULL) { 574 fs_dprintk (FS_DEBUG_TXQ, "Found queue at %x full. Waiting.\n", 575 q->offset); 576 schedule (); 577 } 578 579 wp &= ~0xf; 580 cqe = bus_to_virt (wp); 581 if (qe != cqe) { 582 fs_dprintk (FS_DEBUG_TXQ, "q mismatch! %p %p\n", qe, cqe); 583 } 584 585 write_fs (dev, Q_WP(q->offset), Q_INCWRAP); 586 587 { 588 static int c; 589 if (!(c++ % 100)) 590 { 591 int rp, wp; 592 rp = read_fs (dev, Q_RP(q->offset)); 593 wp = read_fs (dev, Q_WP(q->offset)); 594 fs_dprintk (FS_DEBUG_TXQ, "q at %d: %x-%x: %x entries.\n", 595 q->offset, rp, wp, wp-rp); 596 } 597 } 598} 599 600#ifdef DEBUG_EXTRA 601static struct FS_QENTRY pq[60]; 602static int qp; 603 604static struct FS_BPENTRY dq[60]; 605static int qd; 606static void *da[60]; 607#endif 608 609static void submit_queue (struct fs_dev *dev, struct queue *q, 610 u32 cmd, u32 p1, u32 p2, u32 p3) 611{ 612 struct FS_QENTRY *qe; 613 614 qe = get_qentry (dev, q); 615 qe->cmd = cmd; 616 qe->p0 = p1; 617 qe->p1 = p2; 618 qe->p2 = p3; 619 submit_qentry (dev, q, qe); 620 621#ifdef DEBUG_EXTRA 622 pq[qp].cmd = cmd; 623 pq[qp].p0 = p1; 624 pq[qp].p1 = p2; 625 pq[qp].p2 = p3; 626 qp++; 627 if (qp >= 60) qp = 0; 628#endif 629} 630 631/* Test the "other" way one day... -- REW */ 632#define submit_command submit_queue 633 634 635 636static void process_return_queue (struct fs_dev *dev, struct queue *q) 637{ 638 long rq; 639 struct FS_QENTRY *qe; 640 void *tc; 641 642 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) { 643 fs_dprintk (FS_DEBUG_QUEUE, "reaping return queue entry at %lx\n", rq); 644 qe = bus_to_virt (rq); 645 646 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. (%d)\n", 647 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe)); 648 649 switch (STATUS_CODE (qe)) { 650 case 5: 651 tc = bus_to_virt (qe->p0); 652 fs_dprintk (FS_DEBUG_ALLOC, "Free tc: %p\n", tc); 653 kfree (tc); 654 break; 655 } 656 657 write_fs (dev, Q_RP(q->offset), Q_INCWRAP); 658 } 659} 660 661 662static void process_txdone_queue (struct fs_dev *dev, struct queue *q) 663{ 664 long rq; 665 long tmp; 666 struct FS_QENTRY *qe; 667 struct sk_buff *skb; 668 struct FS_BPENTRY *td; 669 670 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) { 671 fs_dprintk (FS_DEBUG_QUEUE, "reaping txdone entry at %lx\n", rq); 672 qe = bus_to_virt (rq); 673 674 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x: %d\n", 675 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe)); 676 677 if (STATUS_CODE (qe) != 2) 678 fs_dprintk (FS_DEBUG_TXMEM, "queue entry: %08x %08x %08x %08x: %d\n", 679 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe)); 680 681 682 switch (STATUS_CODE (qe)) { 683 case 0x01: /* This is for AAL0 where we put the chip in streaming mode */ 684 /* Fall through */ 685 case 0x02: 686 /* Process a real txdone entry. */ 687 tmp = qe->p0; 688 if (tmp & 0x0f) 689 printk (KERN_WARNING "td not aligned: %ld\n", tmp); 690 tmp &= ~0x0f; 691 td = bus_to_virt (tmp); 692 693 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p.\n", 694 td->flags, td->next, td->bsa, td->aal_bufsize, td->skb ); 695 696 skb = td->skb; 697 if (skb == FS_VCC (ATM_SKB(skb)->vcc)->last_skb) { 698 wake_up_interruptible (& FS_VCC (ATM_SKB(skb)->vcc)->close_wait); 699 FS_VCC (ATM_SKB(skb)->vcc)->last_skb = NULL; 700 } 701 td->dev->ntxpckts--; 702 703 { 704 static int c=0; 705 706 if (!(c++ % 100)) { 707 fs_dprintk (FS_DEBUG_QSIZE, "[%d]", td->dev->ntxpckts); 708 } 709 } 710 711 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx); 712 713 fs_dprintk (FS_DEBUG_TXMEM, "i"); 714 fs_dprintk (FS_DEBUG_ALLOC, "Free t-skb: %p\n", skb); 715 fs_kfree_skb (skb); 716 717 fs_dprintk (FS_DEBUG_ALLOC, "Free trans-d: %p\n", td); 718 memset (td, ATM_POISON_FREE, sizeof(struct FS_BPENTRY)); 719 kfree (td); 720 break; 721 default: 722 /* Here we get the tx purge inhibit command ... */ 723 /* Action, I believe, is "don't do anything". -- REW */ 724 ; 725 } 726 727 write_fs (dev, Q_RP(q->offset), Q_INCWRAP); 728 } 729} 730 731 732static void process_incoming (struct fs_dev *dev, struct queue *q) 733{ 734 long rq; 735 struct FS_QENTRY *qe; 736 struct FS_BPENTRY *pe; 737 struct sk_buff *skb; 738 unsigned int channo; 739 struct atm_vcc *atm_vcc; 740 741 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) { 742 fs_dprintk (FS_DEBUG_QUEUE, "reaping incoming queue entry at %lx\n", rq); 743 qe = bus_to_virt (rq); 744 745 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. ", 746 qe->cmd, qe->p0, qe->p1, qe->p2); 747 748 fs_dprintk (FS_DEBUG_QUEUE, "-> %x: %s\n", 749 STATUS_CODE (qe), 750 res_strings[STATUS_CODE(qe)]); 751 752 pe = bus_to_virt (qe->p0); 753 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p %p.\n", 754 pe->flags, pe->next, pe->bsa, pe->aal_bufsize, 755 pe->skb, pe->fp); 756 757 channo = qe->cmd & 0xffff; 758 759 if (channo < dev->nchannels) 760 atm_vcc = dev->atm_vccs[channo]; 761 else 762 atm_vcc = NULL; 763 764 /* Single buffer packet */ 765 switch (STATUS_CODE (qe)) { 766 case 0x1: 767 /* Fall through for streaming mode */ 768 case 0x2:/* Packet received OK.... */ 769 if (atm_vcc) { 770 skb = pe->skb; 771 pe->fp->n--; 772 skb_put (skb, qe->p1 & 0xffff); 773 ATM_SKB(skb)->vcc = atm_vcc; 774 atomic_inc(&atm_vcc->stats->rx); 775 __net_timestamp(skb); 776 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p (pushed)\n", skb); 777 atm_vcc->push (atm_vcc, skb); 778 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe); 779 kfree (pe); 780 } else { 781 printk (KERN_ERR "Got a receive on a non-open channel %d.\n", channo); 782 } 783 break; 784 case 0x17:/* AAL 5 CRC32 error. IFF the length field is nonzero, a buffer 785 has been consumed and needs to be processed. -- REW */ 786 if (qe->p1 & 0xffff) { 787 pe = bus_to_virt (qe->p0); 788 pe->fp->n--; 789 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", pe->skb); 790 dev_kfree_skb_any (pe->skb); 791 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe); 792 kfree (pe); 793 } 794 if (atm_vcc) 795 atomic_inc(&atm_vcc->stats->rx_drop); 796 break; 797 case 0x1f: /* Reassembly abort: no buffers. */ 798 /* Silently increment error counter. */ 799 if (atm_vcc) 800 atomic_inc(&atm_vcc->stats->rx_drop); 801 break; 802 default: /* Hmm. Haven't written the code to handle the others yet... -- REW */ 803 printk (KERN_WARNING "Don't know what to do with RX status %x: %s.\n", 804 STATUS_CODE(qe), res_strings[STATUS_CODE (qe)]); 805 } 806 write_fs (dev, Q_RP(q->offset), Q_INCWRAP); 807 } 808} 809 810 811 812#define DO_DIRECTION(tp) ((tp)->traffic_class != ATM_NONE) 813 814static int fs_open(struct atm_vcc *atm_vcc) 815{ 816 struct fs_dev *dev; 817 struct fs_vcc *vcc; 818 struct fs_transmit_config *tc; 819 struct atm_trafprm * txtp; 820 struct atm_trafprm * rxtp; 821 /* struct fs_receive_config *rc;*/ 822 /* struct FS_QENTRY *qe; */ 823 int error; 824 int bfp; 825 int to; 826 unsigned short tmc0; 827 short vpi = atm_vcc->vpi; 828 int vci = atm_vcc->vci; 829 830 func_enter (); 831 832 dev = FS_DEV(atm_vcc->dev); 833 fs_dprintk (FS_DEBUG_OPEN, "fs: open on dev: %p, vcc at %p\n", 834 dev, atm_vcc); 835 836 if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC) 837 set_bit(ATM_VF_ADDR, &atm_vcc->flags); 838 839 if ((atm_vcc->qos.aal != ATM_AAL5) && 840 (atm_vcc->qos.aal != ATM_AAL2)) 841 return -EINVAL; 842 843 fs_dprintk (FS_DEBUG_OPEN, "fs: (itf %d): open %d.%d\n", 844 atm_vcc->dev->number, atm_vcc->vpi, atm_vcc->vci); 845 846 847 vcc = kmalloc(sizeof(struct fs_vcc), GFP_KERNEL); 848 fs_dprintk (FS_DEBUG_ALLOC, "Alloc VCC: %p(%Zd)\n", vcc, sizeof(struct fs_vcc)); 849 if (!vcc) { 850 clear_bit(ATM_VF_ADDR, &atm_vcc->flags); 851 return -ENOMEM; 852 } 853 854 atm_vcc->dev_data = vcc; 855 vcc->last_skb = NULL; 856 857 init_waitqueue_head (&vcc->close_wait); 858 859 txtp = &atm_vcc->qos.txtp; 860 rxtp = &atm_vcc->qos.rxtp; 861 862 if (!test_bit(ATM_VF_PARTIAL, &atm_vcc->flags)) { 863 if (IS_FS50(dev)) { 864 /* Increment the channel numer: take a free one next time. */ 865 for (to=33;to;to--, dev->channo++) { 866 /* We only have 32 channels */ 867 if (dev->channo >= 32) 868 dev->channo = 0; 869 /* If we need to do RX, AND the RX is inuse, try the next */ 870 if (DO_DIRECTION(rxtp) && dev->atm_vccs[dev->channo]) 871 continue; 872 /* If we need to do TX, AND the TX is inuse, try the next */ 873 if (DO_DIRECTION(txtp) && test_bit (dev->channo, dev->tx_inuse)) 874 continue; 875 /* Ok, both are free! (or not needed) */ 876 break; 877 } 878 if (!to) { 879 printk ("No more free channels for FS50..\n"); 880 return -EBUSY; 881 } 882 vcc->channo = dev->channo; 883 dev->channo &= dev->channel_mask; 884 885 } else { 886 vcc->channo = (vpi << FS155_VCI_BITS) | (vci); 887 if (((DO_DIRECTION(rxtp) && dev->atm_vccs[vcc->channo])) || 888 ( DO_DIRECTION(txtp) && test_bit (vcc->channo, dev->tx_inuse))) { 889 printk ("Channel is in use for FS155.\n"); 890 return -EBUSY; 891 } 892 } 893 fs_dprintk (FS_DEBUG_OPEN, "OK. Allocated channel %x(%d).\n", 894 vcc->channo, vcc->channo); 895 } 896 897 if (DO_DIRECTION (txtp)) { 898 tc = kmalloc (sizeof (struct fs_transmit_config), GFP_KERNEL); 899 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tc: %p(%Zd)\n", 900 tc, sizeof (struct fs_transmit_config)); 901 if (!tc) { 902 fs_dprintk (FS_DEBUG_OPEN, "fs: can't alloc transmit_config.\n"); 903 return -ENOMEM; 904 } 905 906 /* Allocate the "open" entry from the high priority txq. This makes 907 it most likely that the chip will notice it. It also prevents us 908 from having to wait for completion. On the other hand, we may 909 need to wait for completion anyway, to see if it completed 910 successfully. */ 911 912 switch (atm_vcc->qos.aal) { 913 case ATM_AAL2: 914 case ATM_AAL0: 915 tc->flags = 0 916 | TC_FLAGS_TRANSPARENT_PAYLOAD 917 | TC_FLAGS_PACKET 918 | (1 << 28) 919 | TC_FLAGS_TYPE_UBR 920 | TC_FLAGS_CAL0; 921 break; 922 case ATM_AAL5: 923 tc->flags = 0 924 | TC_FLAGS_AAL5 925 | TC_FLAGS_PACKET /* ??? */ 926 | TC_FLAGS_TYPE_CBR 927 | TC_FLAGS_CAL0; 928 break; 929 default: 930 printk ("Unknown aal: %d\n", atm_vcc->qos.aal); 931 tc->flags = 0; 932 } 933 /* Docs are vague about this atm_hdr field. By the way, the FS 934 * chip makes odd errors if lower bits are set.... -- REW */ 935 tc->atm_hdr = (vpi << 20) | (vci << 4); 936 tmc0 = 0; 937 { 938 int pcr = atm_pcr_goal (txtp); 939 940 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr); 941 942 if (IS_FS50(dev)) { 943 if (pcr > 51840000/53/8) pcr = 51840000/53/8; 944 } else { 945 if (pcr > 155520000/53/8) pcr = 155520000/53/8; 946 } 947 if (!pcr) { 948 /* no rate cap */ 949 tmc0 = IS_FS50(dev)?0x61BE:0x64c9; /* Just copied over the bits from Fujitsu -- REW */ 950 } else { 951 int r; 952 if (pcr < 0) { 953 r = ROUND_DOWN; 954 pcr = -pcr; 955 } else { 956 r = ROUND_UP; 957 } 958 error = make_rate (pcr, r, &tmc0, NULL); 959 if (error) { 960 kfree(tc); 961 return error; 962 } 963 } 964 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr); 965 } 966 967 tc->TMC[0] = tmc0 | 0x4000; 968 tc->TMC[1] = 0; /* Unused */ 969 tc->TMC[2] = 0; /* Unused */ 970 tc->TMC[3] = 0; /* Unused */ 971 972 tc->spec = 0; /* UTOPIA address, UDF, HEC: Unused -> 0 */ 973 tc->rtag[0] = 0; /* What should I do with routing tags??? 974 -- Not used -- AS -- Thanks -- REW*/ 975 tc->rtag[1] = 0; 976 tc->rtag[2] = 0; 977 978 if (fs_debug & FS_DEBUG_OPEN) { 979 fs_dprintk (FS_DEBUG_OPEN, "TX config record:\n"); 980 my_hd (tc, sizeof (*tc)); 981 } 982 983 /* We now use the "submit_command" function to submit commands to 984 the firestream. There is a define up near the definition of 985 that routine that switches this routine between immediate write 986 to the immediate comamnd registers and queuing the commands in 987 the HPTXQ for execution. This last technique might be more 988 efficient if we know we're going to submit a whole lot of 989 commands in one go, but this driver is not setup to be able to 990 use such a construct. So it probably doen't matter much right 991 now. -- REW */ 992 993 /* The command is IMMediate and INQueue. The parameters are out-of-line.. */ 994 submit_command (dev, &dev->hp_txq, 995 QE_CMD_CONFIG_TX | QE_CMD_IMM_INQ | vcc->channo, 996 virt_to_bus (tc), 0, 0); 997 998 submit_command (dev, &dev->hp_txq, 999 QE_CMD_TX_EN | QE_CMD_IMM_INQ | vcc->channo, 1000 0, 0, 0); 1001 set_bit (vcc->channo, dev->tx_inuse); 1002 } 1003 1004 if (DO_DIRECTION (rxtp)) { 1005 dev->atm_vccs[vcc->channo] = atm_vcc; 1006 1007 for (bfp = 0;bfp < FS_NR_FREE_POOLS; bfp++) 1008 if (atm_vcc->qos.rxtp.max_sdu <= dev->rx_fp[bfp].bufsize) break; 1009 if (bfp >= FS_NR_FREE_POOLS) { 1010 fs_dprintk (FS_DEBUG_OPEN, "No free pool fits sdu: %d.\n", 1011 atm_vcc->qos.rxtp.max_sdu); 1012 1013 dev->atm_vccs[vcc->channo] = NULL; 1014 kfree (vcc); 1015 return -EINVAL; 1016 } 1017 1018 switch (atm_vcc->qos.aal) { 1019 case ATM_AAL0: 1020 case ATM_AAL2: 1021 submit_command (dev, &dev->hp_txq, 1022 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo, 1023 RC_FLAGS_TRANSP | 1024 RC_FLAGS_BFPS_BFP * bfp | 1025 RC_FLAGS_RXBM_PSB, 0, 0); 1026 break; 1027 case ATM_AAL5: 1028 submit_command (dev, &dev->hp_txq, 1029 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo, 1030 RC_FLAGS_AAL5 | 1031 RC_FLAGS_BFPS_BFP * bfp | 1032 RC_FLAGS_RXBM_PSB, 0, 0); 1033 break; 1034 }; 1035 if (IS_FS50 (dev)) { 1036 submit_command (dev, &dev->hp_txq, 1037 QE_CMD_REG_WR | QE_CMD_IMM_INQ, 1038 0x80 + vcc->channo, 1039 (vpi << 16) | vci, 0 ); 1040 } 1041 submit_command (dev, &dev->hp_txq, 1042 QE_CMD_RX_EN | QE_CMD_IMM_INQ | vcc->channo, 1043 0, 0, 0); 1044 } 1045 1046 /* Indicate we're done! */ 1047 set_bit(ATM_VF_READY, &atm_vcc->flags); 1048 1049 func_exit (); 1050 return 0; 1051} 1052 1053 1054static void fs_close(struct atm_vcc *atm_vcc) 1055{ 1056 struct fs_dev *dev = FS_DEV (atm_vcc->dev); 1057 struct fs_vcc *vcc = FS_VCC (atm_vcc); 1058 struct atm_trafprm * txtp; 1059 struct atm_trafprm * rxtp; 1060 1061 func_enter (); 1062 1063 clear_bit(ATM_VF_READY, &atm_vcc->flags); 1064 1065 fs_dprintk (FS_DEBUG_QSIZE, "--==**[%d]**==--", dev->ntxpckts); 1066 if (vcc->last_skb) { 1067 fs_dprintk (FS_DEBUG_QUEUE, "Waiting for skb %p to be sent.\n", 1068 vcc->last_skb); 1069 interruptible_sleep_on (& vcc->close_wait); 1070 } 1071 1072 txtp = &atm_vcc->qos.txtp; 1073 rxtp = &atm_vcc->qos.rxtp; 1074 1075 1076 1077 if (DO_DIRECTION (txtp)) { 1078 submit_command (dev, &dev->hp_txq, 1079 QE_CMD_TX_PURGE_INH | /*QE_CMD_IMM_INQ|*/ vcc->channo, 0,0,0); 1080 clear_bit (vcc->channo, dev->tx_inuse); 1081 } 1082 1083 if (DO_DIRECTION (rxtp)) { 1084 submit_command (dev, &dev->hp_txq, 1085 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0); 1086 dev->atm_vccs [vcc->channo] = NULL; 1087 1088 /* This means that this is configured as a receive channel */ 1089 if (IS_FS50 (dev)) { 1090 /* Disable the receive filter. Is 0/0 indeed an invalid receive 1091 channel? -- REW. Yes it is. -- Hang. Ok. I'll use -1 1092 (0xfff...) -- REW */ 1093 submit_command (dev, &dev->hp_txq, 1094 QE_CMD_REG_WR | QE_CMD_IMM_INQ, 1095 0x80 + vcc->channo, -1, 0 ); 1096 } 1097 } 1098 1099 fs_dprintk (FS_DEBUG_ALLOC, "Free vcc: %p\n", vcc); 1100 kfree (vcc); 1101 1102 func_exit (); 1103} 1104 1105 1106static int fs_send (struct atm_vcc *atm_vcc, struct sk_buff *skb) 1107{ 1108 struct fs_dev *dev = FS_DEV (atm_vcc->dev); 1109 struct fs_vcc *vcc = FS_VCC (atm_vcc); 1110 struct FS_BPENTRY *td; 1111 1112 func_enter (); 1113 1114 fs_dprintk (FS_DEBUG_TXMEM, "I"); 1115 fs_dprintk (FS_DEBUG_SEND, "Send: atm_vcc %p skb %p vcc %p dev %p\n", 1116 atm_vcc, skb, vcc, dev); 1117 1118 fs_dprintk (FS_DEBUG_ALLOC, "Alloc t-skb: %p (atm_send)\n", skb); 1119 1120 ATM_SKB(skb)->vcc = atm_vcc; 1121 1122 vcc->last_skb = skb; 1123 1124 td = kmalloc (sizeof (struct FS_BPENTRY), GFP_ATOMIC); 1125 fs_dprintk (FS_DEBUG_ALLOC, "Alloc transd: %p(%Zd)\n", td, sizeof (struct FS_BPENTRY)); 1126 if (!td) { 1127 /* Oops out of mem */ 1128 return -ENOMEM; 1129 } 1130 1131 fs_dprintk (FS_DEBUG_SEND, "first word in buffer: %x\n", 1132 *(int *) skb->data); 1133 1134 td->flags = TD_EPI | TD_DATA | skb->len; 1135 td->next = 0; 1136 td->bsa = virt_to_bus (skb->data); 1137 td->skb = skb; 1138 td->dev = dev; 1139 dev->ntxpckts++; 1140 1141#ifdef DEBUG_EXTRA 1142 da[qd] = td; 1143 dq[qd].flags = td->flags; 1144 dq[qd].next = td->next; 1145 dq[qd].bsa = td->bsa; 1146 dq[qd].skb = td->skb; 1147 dq[qd].dev = td->dev; 1148 qd++; 1149 if (qd >= 60) qd = 0; 1150#endif 1151 1152 submit_queue (dev, &dev->hp_txq, 1153 QE_TRANSMIT_DE | vcc->channo, 1154 virt_to_bus (td), 0, 1155 virt_to_bus (td)); 1156 1157 fs_dprintk (FS_DEBUG_QUEUE, "in send: txq %d txrq %d\n", 1158 read_fs (dev, Q_EA (dev->hp_txq.offset)) - 1159 read_fs (dev, Q_SA (dev->hp_txq.offset)), 1160 read_fs (dev, Q_EA (dev->tx_relq.offset)) - 1161 read_fs (dev, Q_SA (dev->tx_relq.offset))); 1162 1163 func_exit (); 1164 return 0; 1165} 1166 1167 1168/* Some function placeholders for functions we don't yet support. */ 1169 1170 1171 1172static const struct atmdev_ops ops = { 1173 .open = fs_open, 1174 .close = fs_close, 1175 .send = fs_send, 1176 .owner = THIS_MODULE, 1177 /* ioctl: fs_ioctl, */ 1178 /* getsockopt: fs_getsockopt, */ 1179 /* setsockopt: fs_setsockopt, */ 1180 /* change_qos: fs_change_qos, */ 1181 1182 /* For now implement these internally here... */ 1183 /* phy_put: fs_phy_put, */ 1184 /* phy_get: fs_phy_get, */ 1185}; 1186 1187 1188static void __devinit undocumented_pci_fix (struct pci_dev *pdev) 1189{ 1190 u32 tint; 1191 1192 /* The Windows driver says: */ 1193 /* Switch off FireStream Retry Limit Threshold 1194 */ 1195 1196 /* The register at 0x28 is documented as "reserved", no further 1197 comments. */ 1198 1199 pci_read_config_dword (pdev, 0x28, &tint); 1200 if (tint != 0x80) { 1201 tint = 0x80; 1202 pci_write_config_dword (pdev, 0x28, tint); 1203 } 1204} 1205 1206 1207 1208/************************************************************************** 1209 * PHY routines * 1210 **************************************************************************/ 1211 1212static void __devinit write_phy (struct fs_dev *dev, int regnum, int val) 1213{ 1214 submit_command (dev, &dev->hp_txq, QE_CMD_PRP_WR | QE_CMD_IMM_INQ, 1215 regnum, val, 0); 1216} 1217 1218static int __devinit init_phy (struct fs_dev *dev, struct reginit_item *reginit) 1219{ 1220 int i; 1221 1222 func_enter (); 1223 while (reginit->reg != PHY_EOF) { 1224 if (reginit->reg == PHY_CLEARALL) { 1225 /* "PHY_CLEARALL means clear all registers. Numregisters is in "val". */ 1226 for (i=0;i<reginit->val;i++) { 1227 write_phy (dev, i, 0); 1228 } 1229 } else { 1230 write_phy (dev, reginit->reg, reginit->val); 1231 } 1232 reginit++; 1233 } 1234 func_exit (); 1235 return 0; 1236} 1237 1238static void reset_chip (struct fs_dev *dev) 1239{ 1240 int i; 1241 1242 write_fs (dev, SARMODE0, SARMODE0_SRTS0); 1243 1244 /* Undocumented delay */ 1245 udelay (128); 1246 1247 /* The "internal registers are documented to all reset to zero, but 1248 comments & code in the Windows driver indicates that the pools are 1249 NOT reset. */ 1250 for (i=0;i < FS_NR_FREE_POOLS;i++) { 1251 write_fs (dev, FP_CNF (RXB_FP(i)), 0); 1252 write_fs (dev, FP_SA (RXB_FP(i)), 0); 1253 write_fs (dev, FP_EA (RXB_FP(i)), 0); 1254 write_fs (dev, FP_CNT (RXB_FP(i)), 0); 1255 write_fs (dev, FP_CTU (RXB_FP(i)), 0); 1256 } 1257 1258 /* The same goes for the match channel registers, although those are 1259 NOT documented that way in the Windows driver. -- REW */ 1260 /* The Windows driver DOES write 0 to these registers somewhere in 1261 the init sequence. However, a small hardware-feature, will 1262 prevent reception of data on VPI/VCI = 0/0 (Unless the channel 1263 allocated happens to have no disabled channels that have a lower 1264 number. -- REW */ 1265 1266 /* Clear the match channel registers. */ 1267 if (IS_FS50 (dev)) { 1268 for (i=0;i<FS50_NR_CHANNELS;i++) { 1269 write_fs (dev, 0x200 + i * 4, -1); 1270 } 1271 } 1272} 1273 1274static void __devinit *aligned_kmalloc (int size, gfp_t flags, int alignment) 1275{ 1276 void *t; 1277 1278 if (alignment <= 0x10) { 1279 t = kmalloc (size, flags); 1280 if ((unsigned long)t & (alignment-1)) { 1281 printk ("Kmalloc doesn't align things correctly! %p\n", t); 1282 kfree (t); 1283 return aligned_kmalloc (size, flags, alignment * 4); 1284 } 1285 return t; 1286 } 1287 printk (KERN_ERR "Request for > 0x10 alignment not yet implemented (hard!)\n"); 1288 return NULL; 1289} 1290 1291static int __devinit init_q (struct fs_dev *dev, 1292 struct queue *txq, int queue, int nentries, int is_rq) 1293{ 1294 int sz = nentries * sizeof (struct FS_QENTRY); 1295 struct FS_QENTRY *p; 1296 1297 func_enter (); 1298 1299 fs_dprintk (FS_DEBUG_INIT, "Inititing queue at %x: %d entries:\n", 1300 queue, nentries); 1301 1302 p = aligned_kmalloc (sz, GFP_KERNEL, 0x10); 1303 fs_dprintk (FS_DEBUG_ALLOC, "Alloc queue: %p(%d)\n", p, sz); 1304 1305 if (!p) return 0; 1306 1307 write_fs (dev, Q_SA(queue), virt_to_bus(p)); 1308 write_fs (dev, Q_EA(queue), virt_to_bus(p+nentries-1)); 1309 write_fs (dev, Q_WP(queue), virt_to_bus(p)); 1310 write_fs (dev, Q_RP(queue), virt_to_bus(p)); 1311 if (is_rq) { 1312 /* Configuration for the receive queue: 0: interrupt immediately, 1313 no pre-warning to empty queues: We do our best to keep the 1314 queue filled anyway. */ 1315 write_fs (dev, Q_CNF(queue), 0 ); 1316 } 1317 1318 txq->sa = p; 1319 txq->ea = p; 1320 txq->offset = queue; 1321 1322 func_exit (); 1323 return 1; 1324} 1325 1326 1327static int __devinit init_fp (struct fs_dev *dev, 1328 struct freepool *fp, int queue, int bufsize, int nr_buffers) 1329{ 1330 func_enter (); 1331 1332 fs_dprintk (FS_DEBUG_INIT, "Inititing free pool at %x:\n", queue); 1333 1334 write_fs (dev, FP_CNF(queue), (bufsize * RBFP_RBS) | RBFP_RBSVAL | RBFP_CME); 1335 write_fs (dev, FP_SA(queue), 0); 1336 write_fs (dev, FP_EA(queue), 0); 1337 write_fs (dev, FP_CTU(queue), 0); 1338 write_fs (dev, FP_CNT(queue), 0); 1339 1340 fp->offset = queue; 1341 fp->bufsize = bufsize; 1342 fp->nr_buffers = nr_buffers; 1343 1344 func_exit (); 1345 return 1; 1346} 1347 1348 1349static inline int nr_buffers_in_freepool (struct fs_dev *dev, struct freepool *fp) 1350{ 1351 return fp->n; 1352} 1353 1354 1355/* Check if this gets going again if a pool ever runs out. -- Yes, it 1356 does. I've seen "receive abort: no buffers" and things started 1357 working again after that... -- REW */ 1358 1359static void top_off_fp (struct fs_dev *dev, struct freepool *fp, 1360 gfp_t gfp_flags) 1361{ 1362 struct FS_BPENTRY *qe, *ne; 1363 struct sk_buff *skb; 1364 int n = 0; 1365 u32 qe_tmp; 1366 1367 fs_dprintk (FS_DEBUG_QUEUE, "Topping off queue at %x (%d-%d/%d)\n", 1368 fp->offset, read_fs (dev, FP_CNT (fp->offset)), fp->n, 1369 fp->nr_buffers); 1370 while (nr_buffers_in_freepool(dev, fp) < fp->nr_buffers) { 1371 1372 skb = alloc_skb (fp->bufsize, gfp_flags); 1373 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-skb: %p(%d)\n", skb, fp->bufsize); 1374 if (!skb) break; 1375 ne = kmalloc (sizeof (struct FS_BPENTRY), gfp_flags); 1376 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-d: %p(%Zd)\n", ne, sizeof (struct FS_BPENTRY)); 1377 if (!ne) { 1378 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", skb); 1379 dev_kfree_skb_any (skb); 1380 break; 1381 } 1382 1383 fs_dprintk (FS_DEBUG_QUEUE, "Adding skb %p desc %p -> %p(%p) ", 1384 skb, ne, skb->data, skb->head); 1385 n++; 1386 ne->flags = FP_FLAGS_EPI | fp->bufsize; 1387 ne->next = virt_to_bus (NULL); 1388 ne->bsa = virt_to_bus (skb->data); 1389 ne->aal_bufsize = fp->bufsize; 1390 ne->skb = skb; 1391 ne->fp = fp; 1392 1393 1394 qe_tmp = read_fs (dev, FP_EA(fp->offset)); 1395 fs_dprintk (FS_DEBUG_QUEUE, "link at %x\n", qe_tmp); 1396 if (qe_tmp) { 1397 qe = bus_to_virt ((long) qe_tmp); 1398 qe->next = virt_to_bus(ne); 1399 qe->flags &= ~FP_FLAGS_EPI; 1400 } else 1401 write_fs (dev, FP_SA(fp->offset), virt_to_bus(ne)); 1402 1403 write_fs (dev, FP_EA(fp->offset), virt_to_bus (ne)); 1404 fp->n++; 1405 write_fs (dev, FP_CTU(fp->offset), 1); 1406 } 1407 1408 fs_dprintk (FS_DEBUG_QUEUE, "Added %d entries. \n", n); 1409} 1410 1411static void __devexit free_queue (struct fs_dev *dev, struct queue *txq) 1412{ 1413 func_enter (); 1414 1415 write_fs (dev, Q_SA(txq->offset), 0); 1416 write_fs (dev, Q_EA(txq->offset), 0); 1417 write_fs (dev, Q_RP(txq->offset), 0); 1418 write_fs (dev, Q_WP(txq->offset), 0); 1419 /* Configuration ? */ 1420 1421 fs_dprintk (FS_DEBUG_ALLOC, "Free queue: %p\n", txq->sa); 1422 kfree (txq->sa); 1423 1424 func_exit (); 1425} 1426 1427static void __devexit free_freepool (struct fs_dev *dev, struct freepool *fp) 1428{ 1429 func_enter (); 1430 1431 write_fs (dev, FP_CNF(fp->offset), 0); 1432 write_fs (dev, FP_SA (fp->offset), 0); 1433 write_fs (dev, FP_EA (fp->offset), 0); 1434 write_fs (dev, FP_CNT(fp->offset), 0); 1435 write_fs (dev, FP_CTU(fp->offset), 0); 1436 1437 func_exit (); 1438} 1439 1440 1441 1442static irqreturn_t fs_irq (int irq, void *dev_id) 1443{ 1444 int i; 1445 u32 status; 1446 struct fs_dev *dev = dev_id; 1447 1448 status = read_fs (dev, ISR); 1449 if (!status) 1450 return IRQ_NONE; 1451 1452 func_enter (); 1453 1454#ifdef IRQ_RATE_LIMIT 1455 /* Aaargh! I'm ashamed. This costs more lines-of-code than the actual 1456 interrupt routine!. (Well, used to when I wrote that comment) -- REW */ 1457 { 1458 static int lastjif; 1459 static int nintr=0; 1460 1461 if (lastjif == jiffies) { 1462 if (++nintr > IRQ_RATE_LIMIT) { 1463 free_irq (dev->irq, dev_id); 1464 printk (KERN_ERR "fs: Too many interrupts. Turning off interrupt %d.\n", 1465 dev->irq); 1466 } 1467 } else { 1468 lastjif = jiffies; 1469 nintr = 0; 1470 } 1471 } 1472#endif 1473 fs_dprintk (FS_DEBUG_QUEUE, "in intr: txq %d txrq %d\n", 1474 read_fs (dev, Q_EA (dev->hp_txq.offset)) - 1475 read_fs (dev, Q_SA (dev->hp_txq.offset)), 1476 read_fs (dev, Q_EA (dev->tx_relq.offset)) - 1477 read_fs (dev, Q_SA (dev->tx_relq.offset))); 1478 1479 /* print the bits in the ISR register. */ 1480 if (fs_debug & FS_DEBUG_IRQ) { 1481 /* The FS_DEBUG things are unnecessary here. But this way it is 1482 clear for grep that these are debug prints. */ 1483 fs_dprintk (FS_DEBUG_IRQ, "IRQ status:"); 1484 for (i=0;i<27;i++) 1485 if (status & (1 << i)) 1486 fs_dprintk (FS_DEBUG_IRQ, " %s", irq_bitname[i]); 1487 fs_dprintk (FS_DEBUG_IRQ, "\n"); 1488 } 1489 1490 if (status & ISR_RBRQ0_W) { 1491 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (0)!!!!\n"); 1492 process_incoming (dev, &dev->rx_rq[0]); 1493 /* items mentioned on RBRQ0 are from FP 0 or 1. */ 1494 top_off_fp (dev, &dev->rx_fp[0], GFP_ATOMIC); 1495 top_off_fp (dev, &dev->rx_fp[1], GFP_ATOMIC); 1496 } 1497 1498 if (status & ISR_RBRQ1_W) { 1499 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (1)!!!!\n"); 1500 process_incoming (dev, &dev->rx_rq[1]); 1501 top_off_fp (dev, &dev->rx_fp[2], GFP_ATOMIC); 1502 top_off_fp (dev, &dev->rx_fp[3], GFP_ATOMIC); 1503 } 1504 1505 if (status & ISR_RBRQ2_W) { 1506 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (2)!!!!\n"); 1507 process_incoming (dev, &dev->rx_rq[2]); 1508 top_off_fp (dev, &dev->rx_fp[4], GFP_ATOMIC); 1509 top_off_fp (dev, &dev->rx_fp[5], GFP_ATOMIC); 1510 } 1511 1512 if (status & ISR_RBRQ3_W) { 1513 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (3)!!!!\n"); 1514 process_incoming (dev, &dev->rx_rq[3]); 1515 top_off_fp (dev, &dev->rx_fp[6], GFP_ATOMIC); 1516 top_off_fp (dev, &dev->rx_fp[7], GFP_ATOMIC); 1517 } 1518 1519 if (status & ISR_CSQ_W) { 1520 fs_dprintk (FS_DEBUG_IRQ, "Command executed ok!\n"); 1521 process_return_queue (dev, &dev->st_q); 1522 } 1523 1524 if (status & ISR_TBRQ_W) { 1525 fs_dprintk (FS_DEBUG_IRQ, "Data tramsitted!\n"); 1526 process_txdone_queue (dev, &dev->tx_relq); 1527 } 1528 1529 func_exit (); 1530 return IRQ_HANDLED; 1531} 1532 1533 1534#ifdef FS_POLL_FREQ 1535static void fs_poll (unsigned long data) 1536{ 1537 struct fs_dev *dev = (struct fs_dev *) data; 1538 1539 fs_irq (0, dev); 1540 dev->timer.expires = jiffies + FS_POLL_FREQ; 1541 add_timer (&dev->timer); 1542} 1543#endif 1544 1545static int __devinit fs_init (struct fs_dev *dev) 1546{ 1547 struct pci_dev *pci_dev; 1548 int isr, to; 1549 int i; 1550 1551 func_enter (); 1552 pci_dev = dev->pci_dev; 1553 1554 printk (KERN_INFO "found a FireStream %d card, base %16llx, irq%d.\n", 1555 IS_FS50(dev)?50:155, 1556 (unsigned long long)pci_resource_start(pci_dev, 0), 1557 dev->pci_dev->irq); 1558 1559 if (fs_debug & FS_DEBUG_INIT) 1560 my_hd ((unsigned char *) dev, sizeof (*dev)); 1561 1562 undocumented_pci_fix (pci_dev); 1563 1564 dev->hw_base = pci_resource_start(pci_dev, 0); 1565 1566 dev->base = ioremap(dev->hw_base, 0x1000); 1567 1568 reset_chip (dev); 1569 1570 write_fs (dev, SARMODE0, 0 1571 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */ 1572 | (1 * SARMODE0_INTMODE_READCLEAR) 1573 | (1 * SARMODE0_CWRE) 1574 | (IS_FS50(dev) ? SARMODE0_PRPWT_FS50_5: 1575 SARMODE0_PRPWT_FS155_3) 1576 | (1 * SARMODE0_CALSUP_1) 1577 | (IS_FS50(dev) ? (0 1578 | SARMODE0_RXVCS_32 1579 | SARMODE0_ABRVCS_32 1580 | SARMODE0_TXVCS_32): 1581 (0 1582 | SARMODE0_RXVCS_1k 1583 | SARMODE0_ABRVCS_1k 1584 | SARMODE0_TXVCS_1k))); 1585 1586 /* 10ms * 100 is 1 second. That should be enough, as AN3:9 says it takes 1587 1ms. */ 1588 to = 100; 1589 while (--to) { 1590 isr = read_fs (dev, ISR); 1591 1592 /* This bit is documented as "RESERVED" */ 1593 if (isr & ISR_INIT_ERR) { 1594 printk (KERN_ERR "Error initializing the FS... \n"); 1595 goto unmap; 1596 } 1597 if (isr & ISR_INIT) { 1598 fs_dprintk (FS_DEBUG_INIT, "Ha! Initialized OK!\n"); 1599 break; 1600 } 1601 1602 /* Try again after 10ms. */ 1603 msleep(10); 1604 } 1605 1606 if (!to) { 1607 printk (KERN_ERR "timeout initializing the FS... \n"); 1608 goto unmap; 1609 } 1610 1611 dev->channel_mask = 0x1f; 1612 dev->channo = 0; 1613 1614 /* AN3: 10 */ 1615 write_fs (dev, SARMODE1, 0 1616 | (fs_keystream * SARMODE1_DEFHEC) 1617 | ((loopback == 1) * SARMODE1_TSTLP) 1618 | (1 * SARMODE1_DCRM) 1619 | (1 * SARMODE1_DCOAM) 1620 | (0 * SARMODE1_OAMCRC) 1621 | (0 * SARMODE1_DUMPE) 1622 | (0 * SARMODE1_GPLEN) 1623 | (0 * SARMODE1_GNAM) 1624 | (0 * SARMODE1_GVAS) 1625 | (0 * SARMODE1_GPAS) 1626 | (1 * SARMODE1_GPRI) 1627 | (0 * SARMODE1_PMS) 1628 | (0 * SARMODE1_GFCR) 1629 | (1 * SARMODE1_HECM2) 1630 | (1 * SARMODE1_HECM1) 1631 | (1 * SARMODE1_HECM0) 1632 | (1 << 12) /* That's what hang's driver does. Program to 0 */ 1633 | (0 * 0xff)); 1634 1635 1636 /* Cal prescale etc */ 1637 1638 /* AN3: 11 */ 1639 write_fs (dev, TMCONF, 0x0000000f); 1640 write_fs (dev, CALPRESCALE, 0x01010101 * num); 1641 write_fs (dev, 0x80, 0x000F00E4); 1642 1643 /* AN3: 12 */ 1644 write_fs (dev, CELLOSCONF, 0 1645 | ( 0 * CELLOSCONF_CEN) 1646 | ( CELLOSCONF_SC1) 1647 | (0x80 * CELLOSCONF_COBS) 1648 | (num * CELLOSCONF_COPK) /* Changed from 0xff to 0x5a */ 1649 | (num * CELLOSCONF_COST));/* after a hint from Hang. 1650 * performance jumped 50->70... */ 1651 1652 /* Magic value by Hang */ 1653 write_fs (dev, CELLOSCONF_COST, 0x0B809191); 1654 1655 if (IS_FS50 (dev)) { 1656 write_fs (dev, RAS0, RAS0_DCD_XHLT); 1657 dev->atm_dev->ci_range.vpi_bits = 12; 1658 dev->atm_dev->ci_range.vci_bits = 16; 1659 dev->nchannels = FS50_NR_CHANNELS; 1660 } else { 1661 write_fs (dev, RAS0, RAS0_DCD_XHLT 1662 | (((1 << FS155_VPI_BITS) - 1) * RAS0_VPSEL) 1663 | (((1 << FS155_VCI_BITS) - 1) * RAS0_VCSEL)); 1664 /* We can chose the split arbitarily. We might be able to 1665 support more. Whatever. This should do for now. */ 1666 dev->atm_dev->ci_range.vpi_bits = FS155_VPI_BITS; 1667 dev->atm_dev->ci_range.vci_bits = FS155_VCI_BITS; 1668 1669 /* Address bits we can't use should be compared to 0. */ 1670 write_fs (dev, RAC, 0); 1671 1672 /* Manual (AN9, page 6) says ASF1=0 means compare Utopia address 1673 * too. I can't find ASF1 anywhere. Anyway, we AND with just the 1674 * other bits, then compare with 0, which is exactly what we 1675 * want. */ 1676 write_fs (dev, RAM, (1 << (28 - FS155_VPI_BITS - FS155_VCI_BITS)) - 1); 1677 dev->nchannels = FS155_NR_CHANNELS; 1678 } 1679 dev->atm_vccs = kcalloc (dev->nchannels, sizeof (struct atm_vcc *), 1680 GFP_KERNEL); 1681 fs_dprintk (FS_DEBUG_ALLOC, "Alloc atmvccs: %p(%Zd)\n", 1682 dev->atm_vccs, dev->nchannels * sizeof (struct atm_vcc *)); 1683 1684 if (!dev->atm_vccs) { 1685 printk (KERN_WARNING "Couldn't allocate memory for VCC buffers. Woops!\n"); 1686 goto unmap; 1687 } 1688 1689 dev->tx_inuse = kzalloc (dev->nchannels / 8 /* bits/byte */ , GFP_KERNEL); 1690 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tx_inuse: %p(%d)\n", 1691 dev->atm_vccs, dev->nchannels / 8); 1692 1693 if (!dev->tx_inuse) { 1694 printk (KERN_WARNING "Couldn't allocate memory for tx_inuse bits!\n"); 1695 goto unmap; 1696 } 1697 /* -- RAS1 : FS155 and 50 differ. Default (0) should be OK for both */ 1698 /* -- RAS2 : FS50 only: Default is OK. */ 1699 1700 /* DMAMODE, default should be OK. -- REW */ 1701 write_fs (dev, DMAMR, DMAMR_TX_MODE_FULL); 1702 1703 init_q (dev, &dev->hp_txq, TX_PQ(TXQ_HP), TXQ_NENTRIES, 0); 1704 init_q (dev, &dev->lp_txq, TX_PQ(TXQ_LP), TXQ_NENTRIES, 0); 1705 init_q (dev, &dev->tx_relq, TXB_RQ, TXQ_NENTRIES, 1); 1706 init_q (dev, &dev->st_q, ST_Q, TXQ_NENTRIES, 1); 1707 1708 for (i=0;i < FS_NR_FREE_POOLS;i++) { 1709 init_fp (dev, &dev->rx_fp[i], RXB_FP(i), 1710 rx_buf_sizes[i], rx_pool_sizes[i]); 1711 top_off_fp (dev, &dev->rx_fp[i], GFP_KERNEL); 1712 } 1713 1714 1715 for (i=0;i < FS_NR_RX_QUEUES;i++) 1716 init_q (dev, &dev->rx_rq[i], RXB_RQ(i), RXRQ_NENTRIES, 1); 1717 1718 dev->irq = pci_dev->irq; 1719 if (request_irq (dev->irq, fs_irq, IRQF_SHARED, "firestream", dev)) { 1720 printk (KERN_WARNING "couldn't get irq %d for firestream.\n", pci_dev->irq); 1721 goto unmap; 1722 } 1723 fs_dprintk (FS_DEBUG_INIT, "Grabbed irq %d for dev at %p.\n", dev->irq, dev); 1724 1725 /* We want to be notified of most things. Just the statistics count 1726 overflows are not interesting */ 1727 write_fs (dev, IMR, 0 1728 | ISR_RBRQ0_W 1729 | ISR_RBRQ1_W 1730 | ISR_RBRQ2_W 1731 | ISR_RBRQ3_W 1732 | ISR_TBRQ_W 1733 | ISR_CSQ_W); 1734 1735 write_fs (dev, SARMODE0, 0 1736 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */ 1737 | (1 * SARMODE0_GINT) 1738 | (1 * SARMODE0_INTMODE_READCLEAR) 1739 | (0 * SARMODE0_CWRE) 1740 | (IS_FS50(dev)?SARMODE0_PRPWT_FS50_5: 1741 SARMODE0_PRPWT_FS155_3) 1742 | (1 * SARMODE0_CALSUP_1) 1743 | (IS_FS50 (dev)?(0 1744 | SARMODE0_RXVCS_32 1745 | SARMODE0_ABRVCS_32 1746 | SARMODE0_TXVCS_32): 1747 (0 1748 | SARMODE0_RXVCS_1k 1749 | SARMODE0_ABRVCS_1k 1750 | SARMODE0_TXVCS_1k)) 1751 | (1 * SARMODE0_RUN)); 1752 1753 init_phy (dev, PHY_NTC_INIT); 1754 1755 if (loopback == 2) { 1756 write_phy (dev, 0x39, 0x000e); 1757 } 1758 1759#ifdef FS_POLL_FREQ 1760 init_timer (&dev->timer); 1761 dev->timer.data = (unsigned long) dev; 1762 dev->timer.function = fs_poll; 1763 dev->timer.expires = jiffies + FS_POLL_FREQ; 1764 add_timer (&dev->timer); 1765#endif 1766 1767 dev->atm_dev->dev_data = dev; 1768 1769 func_exit (); 1770 return 0; 1771unmap: 1772 iounmap(dev->base); 1773 return 1; 1774} 1775 1776static int __devinit firestream_init_one (struct pci_dev *pci_dev, 1777 const struct pci_device_id *ent) 1778{ 1779 struct atm_dev *atm_dev; 1780 struct fs_dev *fs_dev; 1781 1782 if (pci_enable_device(pci_dev)) 1783 goto err_out; 1784 1785 fs_dev = kzalloc (sizeof (struct fs_dev), GFP_KERNEL); 1786 fs_dprintk (FS_DEBUG_ALLOC, "Alloc fs-dev: %p(%Zd)\n", 1787 fs_dev, sizeof (struct fs_dev)); 1788 if (!fs_dev) 1789 goto err_out; 1790 atm_dev = atm_dev_register("fs", &ops, -1, NULL); 1791 if (!atm_dev) 1792 goto err_out_free_fs_dev; 1793 1794 fs_dev->pci_dev = pci_dev; 1795 fs_dev->atm_dev = atm_dev; 1796 fs_dev->flags = ent->driver_data; 1797 1798 if (fs_init(fs_dev)) 1799 goto err_out_free_atm_dev; 1800 1801 fs_dev->next = fs_boards; 1802 fs_boards = fs_dev; 1803 return 0; 1804 1805 err_out_free_atm_dev: 1806 atm_dev_deregister(atm_dev); 1807 err_out_free_fs_dev: 1808 kfree(fs_dev); 1809 err_out: 1810 return -ENODEV; 1811} 1812 1813static void __devexit firestream_remove_one (struct pci_dev *pdev) 1814{ 1815 int i; 1816 struct fs_dev *dev, *nxtdev; 1817 struct fs_vcc *vcc; 1818 struct FS_BPENTRY *fp, *nxt; 1819 1820 func_enter (); 1821 1822 1823 for (dev = fs_boards;dev != NULL;dev=nxtdev) { 1824 fs_dprintk (FS_DEBUG_CLEANUP, "Releasing resources for dev at %p.\n", dev); 1825 1826 1827 for (i=0;i < dev->nchannels;i++) { 1828 if (dev->atm_vccs[i]) { 1829 vcc = FS_VCC (dev->atm_vccs[i]); 1830 submit_command (dev, &dev->hp_txq, 1831 QE_CMD_TX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0); 1832 submit_command (dev, &dev->hp_txq, 1833 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0); 1834 1835 } 1836 } 1837 1838 1839 for (i=0;i < FS_NR_FREE_POOLS;i++) { 1840 for (fp=bus_to_virt (read_fs (dev, FP_SA(dev->rx_fp[i].offset))); 1841 !(fp->flags & FP_FLAGS_EPI);fp = nxt) { 1842 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb); 1843 dev_kfree_skb_any (fp->skb); 1844 nxt = bus_to_virt (fp->next); 1845 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp); 1846 kfree (fp); 1847 } 1848 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb); 1849 dev_kfree_skb_any (fp->skb); 1850 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp); 1851 kfree (fp); 1852 } 1853 1854 /* Hang the chip in "reset", prevent it clobbering memory that is 1855 no longer ours. */ 1856 reset_chip (dev); 1857 1858 fs_dprintk (FS_DEBUG_CLEANUP, "Freeing irq%d.\n", dev->irq); 1859 free_irq (dev->irq, dev); 1860 del_timer (&dev->timer); 1861 1862 atm_dev_deregister(dev->atm_dev); 1863 free_queue (dev, &dev->hp_txq); 1864 free_queue (dev, &dev->lp_txq); 1865 free_queue (dev, &dev->tx_relq); 1866 free_queue (dev, &dev->st_q); 1867 1868 fs_dprintk (FS_DEBUG_ALLOC, "Free atmvccs: %p\n", dev->atm_vccs); 1869 kfree (dev->atm_vccs); 1870 1871 for (i=0;i< FS_NR_FREE_POOLS;i++) 1872 free_freepool (dev, &dev->rx_fp[i]); 1873 1874 for (i=0;i < FS_NR_RX_QUEUES;i++) 1875 free_queue (dev, &dev->rx_rq[i]); 1876 1877 iounmap(dev->base); 1878 fs_dprintk (FS_DEBUG_ALLOC, "Free fs-dev: %p\n", dev); 1879 nxtdev = dev->next; 1880 kfree (dev); 1881 } 1882 1883 func_exit (); 1884} 1885 1886static struct pci_device_id firestream_pci_tbl[] = { 1887 { PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS50), FS_IS50}, 1888 { PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS155), FS_IS155}, 1889 { 0, } 1890}; 1891 1892MODULE_DEVICE_TABLE(pci, firestream_pci_tbl); 1893 1894static struct pci_driver firestream_driver = { 1895 .name = "firestream", 1896 .id_table = firestream_pci_tbl, 1897 .probe = firestream_init_one, 1898 .remove = __devexit_p(firestream_remove_one), 1899}; 1900 1901static int __init firestream_init_module (void) 1902{ 1903 int error; 1904 1905 func_enter (); 1906 error = pci_register_driver(&firestream_driver); 1907 func_exit (); 1908 return error; 1909} 1910 1911static void __exit firestream_cleanup_module(void) 1912{ 1913 pci_unregister_driver(&firestream_driver); 1914} 1915 1916module_init(firestream_init_module); 1917module_exit(firestream_cleanup_module); 1918 1919MODULE_LICENSE("GPL"); 1920