1/* 2 * pata_ns87415.c - NS87415 (non PARISC) PATA 3 * 4 * (C) 2005 Red Hat <alan@lxorguk.ukuu.org.uk> 5 * 6 * This is a fairly generic MWDMA controller. It has some limitations 7 * as it requires timing reloads on PIO/DMA transitions but it is otherwise 8 * fairly well designed. 9 * 10 * This driver assumes the firmware has left the chip in a valid ST506 11 * compliant state, either legacy IRQ 14/15 or native INTA shared. You 12 * may need to add platform code if your system fails to do this. 13 * 14 * The same cell appears in the 87560 controller used by some PARISC 15 * systems. This has its own special mountain of errata. 16 * 17 * TODO: 18 * Test PARISC SuperIO 19 * Get someone to test on SPARC 20 * Implement lazy pio/dma switching for better performance 21 * 8bit shared timing. 22 * See if we need to kill the FIFO for ATAPI 23 */ 24 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/init.h> 29#include <linux/blkdev.h> 30#include <linux/delay.h> 31#include <linux/device.h> 32#include <scsi/scsi_host.h> 33#include <linux/libata.h> 34#include <linux/ata.h> 35 36#define DRV_NAME "pata_ns87415" 37#define DRV_VERSION "0.0.1" 38 39/** 40 * ns87415_set_mode - Initialize host controller mode timings 41 * @ap: Port whose timings we are configuring 42 * @adev: Device whose timings we are configuring 43 * @mode: Mode to set 44 * 45 * Program the mode registers for this controller, channel and 46 * device. Because the chip is quite an old design we have to do this 47 * for PIO/DMA switches. 48 * 49 * LOCKING: 50 * None (inherited from caller). 51 */ 52 53static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) 54{ 55 struct pci_dev *dev = to_pci_dev(ap->host->dev); 56 int unit = 2 * ap->port_no + adev->devno; 57 int timing = 0x44 + 2 * unit; 58 unsigned long T = 1000000000 / 33333; /* PCI clocks */ 59 struct ata_timing t; 60 u16 clocking; 61 u8 iordy; 62 u8 status; 63 64 /* Timing register format is 17 - low nybble read timing with 65 the high nybble being 16 - x for recovery time in PCI clocks */ 66 67 ata_timing_compute(adev, adev->pio_mode, &t, T, 0); 68 69 clocking = 17 - clamp_val(t.active, 2, 17); 70 clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4; 71 /* Use the same timing for read and write bytes */ 72 clocking |= (clocking << 8); 73 pci_write_config_word(dev, timing, clocking); 74 75 /* Set the IORDY enable versus DMA enable on or off properly */ 76 pci_read_config_byte(dev, 0x42, &iordy); 77 iordy &= ~(1 << (4 + unit)); 78 if (mode >= XFER_MW_DMA_0 || !ata_pio_need_iordy(adev)) 79 iordy |= (1 << (4 + unit)); 80 81 /* Paranoia: We shouldn't ever get here with busy write buffers 82 but if so wait */ 83 84 pci_read_config_byte(dev, 0x43, &status); 85 while (status & 0x03) { 86 udelay(1); 87 pci_read_config_byte(dev, 0x43, &status); 88 } 89 /* Flip the IORDY/DMA bits now we are sure the write buffers are 90 clear */ 91 pci_write_config_byte(dev, 0x42, iordy); 92 93 /* TODO: Set byte 54 command timing to the best 8bit 94 mode shared by all four devices */ 95} 96 97/** 98 * ns87415_set_piomode - Initialize host controller PATA PIO timings 99 * @ap: Port whose timings we are configuring 100 * @adev: Device to program 101 * 102 * Set PIO mode for device, in host controller PCI config space. 103 * 104 * LOCKING: 105 * None (inherited from caller). 106 */ 107 108static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev) 109{ 110 ns87415_set_mode(ap, adev, adev->pio_mode); 111} 112 113/** 114 * ns87415_bmdma_setup - Set up DMA 115 * @qc: Command block 116 * 117 * Set up for bus masterng DMA. We have to do this ourselves 118 * rather than use the helper due to a chip erratum 119 */ 120 121static void ns87415_bmdma_setup(struct ata_queued_cmd *qc) 122{ 123 struct ata_port *ap = qc->ap; 124 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 125 u8 dmactl; 126 127 /* load PRD table addr. */ 128 mb(); /* make sure PRD table writes are visible to controller */ 129 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); 130 131 /* specify data direction, triple-check start bit is clear */ 132 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 133 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 134 /* Due to an erratum we need to write these bits to the wrong 135 place - which does save us an I/O bizarrely */ 136 dmactl |= ATA_DMA_INTR | ATA_DMA_ERR; 137 if (!rw) 138 dmactl |= ATA_DMA_WR; 139 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 140 /* issue r/w command */ 141 ap->ops->sff_exec_command(ap, &qc->tf); 142} 143 144 145static void ns87415_bmdma_start(struct ata_queued_cmd *qc) 146{ 147 ns87415_set_mode(qc->ap, qc->dev, qc->dev->dma_mode); 148 ata_bmdma_start(qc); 149} 150 151/** 152 * ns87415_bmdma_stop - End DMA transfer 153 * @qc: Command block 154 * 155 * End DMA mode and switch the controller back into PIO mode 156 */ 157 158static void ns87415_bmdma_stop(struct ata_queued_cmd *qc) 159{ 160 ata_bmdma_stop(qc); 161 ns87415_set_mode(qc->ap, qc->dev, qc->dev->pio_mode); 162} 163 164/** 165 * ns87415_irq_clear - Clear interrupt 166 * @ap: Channel to clear 167 * 168 * Erratum: Due to a chip bug regisers 02 and 0A bit 1 and 2 (the 169 * error bits) are reset by writing to register 00 or 08. 170 */ 171 172static void ns87415_irq_clear(struct ata_port *ap) 173{ 174 void __iomem *mmio = ap->ioaddr.bmdma_addr; 175 176 if (!mmio) 177 return; 178 iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR), 179 mmio + ATA_DMA_CMD); 180} 181 182/** 183 * ns87415_check_atapi_dma - ATAPI DMA filter 184 * @qc: Command block 185 * 186 * Disable ATAPI DMA (for now). We may be able to do DMA if we 187 * kill the prefetching. This isn't clear. 188 */ 189 190static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc) 191{ 192 return -EOPNOTSUPP; 193} 194 195#if defined(CONFIG_SUPERIO) 196 197/* SUPERIO 87560 is a PoS chip that NatSem denies exists. 198 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations 199 * which use the integrated NS87514 cell for CD-ROM support. 200 * i.e we have to support for CD-ROM installs. 201 * See drivers/parisc/superio.c for more gory details. 202 * 203 * Workarounds taken from drivers/ide/pci/ns87415.c 204 */ 205 206#include <asm/superio.h> 207 208#define SUPERIO_IDE_MAX_RETRIES 25 209 210 211static u8 ns87560_read_buggy(void __iomem *port) 212{ 213 u8 tmp; 214 int retries = SUPERIO_IDE_MAX_RETRIES; 215 do { 216 tmp = ioread8(port); 217 if (tmp != 0) 218 return tmp; 219 udelay(50); 220 } while(retries-- > 0); 221 return tmp; 222} 223 224/** 225 * ns87560_check_status 226 * @ap: channel to check 227 * 228 * Return the status of the channel working around the 229 * 87560 flaws. 230 */ 231 232static u8 ns87560_check_status(struct ata_port *ap) 233{ 234 return ns87560_read_buggy(ap->ioaddr.status_addr); 235} 236 237void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 238{ 239 struct ata_ioports *ioaddr = &ap->ioaddr; 240 241 tf->command = ns87560_check_status(ap); 242 tf->feature = ioread8(ioaddr->error_addr); 243 tf->nsect = ioread8(ioaddr->nsect_addr); 244 tf->lbal = ioread8(ioaddr->lbal_addr); 245 tf->lbam = ioread8(ioaddr->lbam_addr); 246 tf->lbah = ioread8(ioaddr->lbah_addr); 247 tf->device = ns87560_read_buggy(ioaddr->device_addr); 248 249 if (tf->flags & ATA_TFLAG_LBA48) { 250 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 251 tf->hob_feature = ioread8(ioaddr->error_addr); 252 tf->hob_nsect = ioread8(ioaddr->nsect_addr); 253 tf->hob_lbal = ioread8(ioaddr->lbal_addr); 254 tf->hob_lbam = ioread8(ioaddr->lbam_addr); 255 tf->hob_lbah = ioread8(ioaddr->lbah_addr); 256 iowrite8(tf->ctl, ioaddr->ctl_addr); 257 ap->last_ctl = tf->ctl; 258 } 259} 260 261/** 262 * ns87560_bmdma_status 263 * @ap: channel to check 264 * 265 * Return the DMA status of the channel working around the 266 * 87560 flaws. 267 */ 268 269static u8 ns87560_bmdma_status(struct ata_port *ap) 270{ 271 return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 272} 273#endif /* 87560 SuperIO Support */ 274 275static struct ata_port_operations ns87415_pata_ops = { 276 .inherits = &ata_bmdma_port_ops, 277 278 .check_atapi_dma = ns87415_check_atapi_dma, 279 .bmdma_setup = ns87415_bmdma_setup, 280 .bmdma_start = ns87415_bmdma_start, 281 .bmdma_stop = ns87415_bmdma_stop, 282 .sff_irq_clear = ns87415_irq_clear, 283 284 .cable_detect = ata_cable_40wire, 285 .set_piomode = ns87415_set_piomode, 286}; 287 288#if defined(CONFIG_SUPERIO) 289static struct ata_port_operations ns87560_pata_ops = { 290 .inherits = &ns87415_pata_ops, 291 .sff_tf_read = ns87560_tf_read, 292 .sff_check_status = ns87560_check_status, 293 .bmdma_status = ns87560_bmdma_status, 294}; 295#endif 296 297static struct scsi_host_template ns87415_sht = { 298 ATA_BMDMA_SHT(DRV_NAME), 299}; 300 301static void ns87415_fixup(struct pci_dev *pdev) 302{ 303 /* Select 512 byte sectors */ 304 pci_write_config_byte(pdev, 0x55, 0xEE); 305 /* Select PIO0 8bit clocking */ 306 pci_write_config_byte(pdev, 0x54, 0xB7); 307} 308 309/** 310 * ns87415_init_one - Register 87415 ATA PCI device with kernel services 311 * @pdev: PCI device to register 312 * @ent: Entry in ns87415_pci_tbl matching with @pdev 313 * 314 * Called from kernel PCI layer. We probe for combined mode (sigh), 315 * and then hand over control to libata, for it to do the rest. 316 * 317 * LOCKING: 318 * Inherited from PCI layer (may sleep). 319 * 320 * RETURNS: 321 * Zero on success, or -ERRNO value. 322 */ 323 324static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 325{ 326 static int printed_version; 327 static const struct ata_port_info info = { 328 .flags = ATA_FLAG_SLAVE_POSS, 329 .pio_mask = ATA_PIO4, 330 .mwdma_mask = ATA_MWDMA2, 331 .port_ops = &ns87415_pata_ops, 332 }; 333 const struct ata_port_info *ppi[] = { &info, NULL }; 334 int rc; 335#if defined(CONFIG_SUPERIO) 336 static const struct ata_port_info info87560 = { 337 .flags = ATA_FLAG_SLAVE_POSS, 338 .pio_mask = ATA_PIO4, 339 .mwdma_mask = ATA_MWDMA2, 340 .port_ops = &ns87560_pata_ops, 341 }; 342 343 if (PCI_SLOT(pdev->devfn) == 0x0E) 344 ppi[0] = &info87560; 345#endif 346 if (!printed_version++) 347 dev_printk(KERN_DEBUG, &pdev->dev, 348 "version " DRV_VERSION "\n"); 349 350 rc = pcim_enable_device(pdev); 351 if (rc) 352 return rc; 353 354 ns87415_fixup(pdev); 355 356 return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0); 357} 358 359static const struct pci_device_id ns87415_pci_tbl[] = { 360 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), }, 361 362 { } /* terminate list */ 363}; 364 365#ifdef CONFIG_PM 366static int ns87415_reinit_one(struct pci_dev *pdev) 367{ 368 struct ata_host *host = dev_get_drvdata(&pdev->dev); 369 int rc; 370 371 rc = ata_pci_device_do_resume(pdev); 372 if (rc) 373 return rc; 374 375 ns87415_fixup(pdev); 376 377 ata_host_resume(host); 378 return 0; 379} 380#endif 381 382static struct pci_driver ns87415_pci_driver = { 383 .name = DRV_NAME, 384 .id_table = ns87415_pci_tbl, 385 .probe = ns87415_init_one, 386 .remove = ata_pci_remove_one, 387#ifdef CONFIG_PM 388 .suspend = ata_pci_device_suspend, 389 .resume = ns87415_reinit_one, 390#endif 391}; 392 393static int __init ns87415_init(void) 394{ 395 return pci_register_driver(&ns87415_pci_driver); 396} 397 398static void __exit ns87415_exit(void) 399{ 400 pci_unregister_driver(&ns87415_pci_driver); 401} 402 403module_init(ns87415_init); 404module_exit(ns87415_exit); 405 406MODULE_AUTHOR("Alan Cox"); 407MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers"); 408MODULE_LICENSE("GPL"); 409MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); 410MODULE_VERSION(DRV_VERSION); 411