1/* 2 * pata_hpt3x3 - HPT3x3 driver 3 * (c) Copyright 2005-2006 Red Hat 4 * 5 * Was pata_hpt34x but the naming was confusing as it supported the 6 * 343 and 363 so it has been renamed. 7 * 8 * Based on: 9 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002 10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 11 * 12 * May be copied or modified under the terms of the GNU General Public 13 * License 14 */ 15 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/pci.h> 19#include <linux/init.h> 20#include <linux/blkdev.h> 21#include <linux/delay.h> 22#include <scsi/scsi_host.h> 23#include <linux/libata.h> 24 25#define DRV_NAME "pata_hpt3x3" 26#define DRV_VERSION "0.6.1" 27 28/** 29 * hpt3x3_set_piomode - PIO setup 30 * @ap: ATA interface 31 * @adev: device on the interface 32 * 33 * Set our PIO requirements. This is fairly simple on the HPT3x3 as 34 * all we have to do is clear the MWDMA and UDMA bits then load the 35 * mode number. 36 */ 37 38static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev) 39{ 40 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 41 u32 r1, r2; 42 int dn = 2 * ap->port_no + adev->devno; 43 44 pci_read_config_dword(pdev, 0x44, &r1); 45 pci_read_config_dword(pdev, 0x48, &r2); 46 /* Load the PIO timing number */ 47 r1 &= ~(7 << (3 * dn)); 48 r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn); 49 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */ 50 51 pci_write_config_dword(pdev, 0x44, r1); 52 pci_write_config_dword(pdev, 0x48, r2); 53} 54 55#if defined(CONFIG_PATA_HPT3X3_DMA) 56/** 57 * hpt3x3_set_dmamode - DMA timing setup 58 * @ap: ATA interface 59 * @adev: Device being configured 60 * 61 * Set up the channel for MWDMA or UDMA modes. Much the same as with 62 * PIO, load the mode number and then set MWDMA or UDMA flag. 63 * 64 * 0x44 : bit 0-2 master mode, 3-5 slave mode, etc 65 * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc 66 */ 67 68static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev) 69{ 70 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 71 u32 r1, r2; 72 int dn = 2 * ap->port_no + adev->devno; 73 int mode_num = adev->dma_mode & 0x0F; 74 75 pci_read_config_dword(pdev, 0x44, &r1); 76 pci_read_config_dword(pdev, 0x48, &r2); 77 /* Load the timing number */ 78 r1 &= ~(7 << (3 * dn)); 79 r1 |= (mode_num << (3 * dn)); 80 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */ 81 82 if (adev->dma_mode >= XFER_UDMA_0) 83 r2 |= (0x01 << dn); /* Ultra mode */ 84 else 85 r2 |= (0x10 << dn); /* MWDMA */ 86 87 pci_write_config_dword(pdev, 0x44, r1); 88 pci_write_config_dword(pdev, 0x48, r2); 89} 90 91 92static void hpt3x3_freeze(struct ata_port *ap) 93{ 94 void __iomem *mmio = ap->ioaddr.bmdma_addr; 95 96 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START, 97 mmio + ATA_DMA_CMD); 98 ata_sff_dma_pause(ap); 99 ata_sff_freeze(ap); 100} 101 102 103static void hpt3x3_bmdma_setup(struct ata_queued_cmd *qc) 104{ 105 struct ata_port *ap = qc->ap; 106 u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 107 r |= ATA_DMA_INTR | ATA_DMA_ERR; 108 iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 109 return ata_bmdma_setup(qc); 110} 111 112/** 113 * hpt3x3_atapi_dma - ATAPI DMA check 114 * @qc: Queued command 115 * 116 * Just say no - we don't do ATAPI DMA 117 */ 118 119static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc) 120{ 121 return 1; 122} 123 124#endif /* CONFIG_PATA_HPT3X3_DMA */ 125 126static struct scsi_host_template hpt3x3_sht = { 127 ATA_BMDMA_SHT(DRV_NAME), 128}; 129 130static struct ata_port_operations hpt3x3_port_ops = { 131 .inherits = &ata_bmdma_port_ops, 132 .cable_detect = ata_cable_40wire, 133 .set_piomode = hpt3x3_set_piomode, 134#if defined(CONFIG_PATA_HPT3X3_DMA) 135 .set_dmamode = hpt3x3_set_dmamode, 136 .bmdma_setup = hpt3x3_bmdma_setup, 137 .check_atapi_dma= hpt3x3_atapi_dma, 138 .freeze = hpt3x3_freeze, 139#endif 140 141}; 142 143/** 144 * hpt3x3_init_chipset - chip setup 145 * @dev: PCI device 146 * 147 * Perform the setup required at boot and on resume. 148 */ 149 150static void hpt3x3_init_chipset(struct pci_dev *dev) 151{ 152 u16 cmd; 153 /* Initialize the board */ 154 pci_write_config_word(dev, 0x80, 0x00); 155 /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */ 156 pci_read_config_word(dev, PCI_COMMAND, &cmd); 157 if (cmd & PCI_COMMAND_MEMORY) 158 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0); 159 else 160 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); 161} 162 163 164static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 165{ 166 static int printed_version; 167 static const struct ata_port_info info = { 168 .flags = ATA_FLAG_SLAVE_POSS, 169 .pio_mask = ATA_PIO4, 170#if defined(CONFIG_PATA_HPT3X3_DMA) 171 /* Further debug needed */ 172 .mwdma_mask = ATA_MWDMA2, 173 .udma_mask = ATA_UDMA2, 174#endif 175 .port_ops = &hpt3x3_port_ops 176 }; 177 /* Register offsets of taskfiles in BAR4 area */ 178 static const u8 offset_cmd[2] = { 0x20, 0x28 }; 179 static const u8 offset_ctl[2] = { 0x36, 0x3E }; 180 const struct ata_port_info *ppi[] = { &info, NULL }; 181 struct ata_host *host; 182 int i, rc; 183 void __iomem *base; 184 185 hpt3x3_init_chipset(pdev); 186 187 if (!printed_version++) 188 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 189 190 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 191 if (!host) 192 return -ENOMEM; 193 /* acquire resources and fill host */ 194 rc = pcim_enable_device(pdev); 195 if (rc) 196 return rc; 197 198 /* Everything is relative to BAR4 if we set up this way */ 199 rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME); 200 if (rc == -EBUSY) 201 pcim_pin_device(pdev); 202 if (rc) 203 return rc; 204 host->iomap = pcim_iomap_table(pdev); 205 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 206 if (rc) 207 return rc; 208 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 209 if (rc) 210 return rc; 211 212 base = host->iomap[4]; /* Bus mastering base */ 213 214 for (i = 0; i < host->n_ports; i++) { 215 struct ata_port *ap = host->ports[i]; 216 struct ata_ioports *ioaddr = &ap->ioaddr; 217 218 ioaddr->cmd_addr = base + offset_cmd[i]; 219 ioaddr->altstatus_addr = 220 ioaddr->ctl_addr = base + offset_ctl[i]; 221 ioaddr->scr_addr = NULL; 222 ata_sff_std_ports(ioaddr); 223 ioaddr->bmdma_addr = base + 8 * i; 224 225 ata_port_pbar_desc(ap, 4, -1, "ioport"); 226 ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd"); 227 } 228 pci_set_master(pdev); 229 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 230 IRQF_SHARED, &hpt3x3_sht); 231} 232 233#ifdef CONFIG_PM 234static int hpt3x3_reinit_one(struct pci_dev *dev) 235{ 236 struct ata_host *host = dev_get_drvdata(&dev->dev); 237 int rc; 238 239 rc = ata_pci_device_do_resume(dev); 240 if (rc) 241 return rc; 242 243 hpt3x3_init_chipset(dev); 244 245 ata_host_resume(host); 246 return 0; 247} 248#endif 249 250static const struct pci_device_id hpt3x3[] = { 251 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), }, 252 253 { }, 254}; 255 256static struct pci_driver hpt3x3_pci_driver = { 257 .name = DRV_NAME, 258 .id_table = hpt3x3, 259 .probe = hpt3x3_init_one, 260 .remove = ata_pci_remove_one, 261#ifdef CONFIG_PM 262 .suspend = ata_pci_device_suspend, 263 .resume = hpt3x3_reinit_one, 264#endif 265}; 266 267static int __init hpt3x3_init(void) 268{ 269 return pci_register_driver(&hpt3x3_pci_driver); 270} 271 272 273static void __exit hpt3x3_exit(void) 274{ 275 pci_unregister_driver(&hpt3x3_pci_driver); 276} 277 278 279MODULE_AUTHOR("Alan Cox"); 280MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363"); 281MODULE_LICENSE("GPL"); 282MODULE_DEVICE_TABLE(pci, hpt3x3); 283MODULE_VERSION(DRV_VERSION); 284 285module_init(hpt3x3_init); 286module_exit(hpt3x3_exit); 287