1/* time.c: UltraSparc timer and TOD clock support. 2 * 3 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net) 4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 5 * 6 * Based largely on code which is: 7 * 8 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) 9 */ 10 11#include <linux/errno.h> 12#include <linux/module.h> 13#include <linux/sched.h> 14#include <linux/kernel.h> 15#include <linux/param.h> 16#include <linux/string.h> 17#include <linux/mm.h> 18#include <linux/interrupt.h> 19#include <linux/time.h> 20#include <linux/timex.h> 21#include <linux/init.h> 22#include <linux/ioport.h> 23#include <linux/mc146818rtc.h> 24#include <linux/delay.h> 25#include <linux/profile.h> 26#include <linux/bcd.h> 27#include <linux/jiffies.h> 28#include <linux/cpufreq.h> 29#include <linux/percpu.h> 30#include <linux/miscdevice.h> 31#include <linux/rtc.h> 32#include <linux/rtc/m48t59.h> 33#include <linux/kernel_stat.h> 34#include <linux/clockchips.h> 35#include <linux/clocksource.h> 36#include <linux/of_device.h> 37#include <linux/platform_device.h> 38#include <linux/ftrace.h> 39 40#include <asm/oplib.h> 41#include <asm/timer.h> 42#include <asm/irq.h> 43#include <asm/io.h> 44#include <asm/prom.h> 45#include <asm/starfire.h> 46#include <asm/smp.h> 47#include <asm/sections.h> 48#include <asm/cpudata.h> 49#include <asm/uaccess.h> 50#include <asm/irq_regs.h> 51 52#include "entry.h" 53 54DEFINE_SPINLOCK(rtc_lock); 55 56#define TICK_PRIV_BIT (1UL << 63) 57#define TICKCMP_IRQ_BIT (1UL << 63) 58 59#ifdef CONFIG_SMP 60unsigned long profile_pc(struct pt_regs *regs) 61{ 62 unsigned long pc = instruction_pointer(regs); 63 64 if (in_lock_functions(pc)) 65 return regs->u_regs[UREG_RETPC]; 66 return pc; 67} 68EXPORT_SYMBOL(profile_pc); 69#endif 70 71static void tick_disable_protection(void) 72{ 73 __asm__ __volatile__( 74 " ba,pt %%xcc, 1f\n" 75 " nop\n" 76 " .align 64\n" 77 "1: rd %%tick, %%g2\n" 78 " add %%g2, 6, %%g2\n" 79 " andn %%g2, %0, %%g2\n" 80 " wrpr %%g2, 0, %%tick\n" 81 " rdpr %%tick, %%g0" 82 : /* no outputs */ 83 : "r" (TICK_PRIV_BIT) 84 : "g2"); 85} 86 87static void tick_disable_irq(void) 88{ 89 __asm__ __volatile__( 90 " ba,pt %%xcc, 1f\n" 91 " nop\n" 92 " .align 64\n" 93 "1: wr %0, 0x0, %%tick_cmpr\n" 94 " rd %%tick_cmpr, %%g0" 95 : /* no outputs */ 96 : "r" (TICKCMP_IRQ_BIT)); 97} 98 99static void tick_init_tick(void) 100{ 101 tick_disable_protection(); 102 tick_disable_irq(); 103} 104 105static unsigned long long tick_get_tick(void) 106{ 107 unsigned long ret; 108 109 __asm__ __volatile__("rd %%tick, %0\n\t" 110 "mov %0, %0" 111 : "=r" (ret)); 112 113 return ret & ~TICK_PRIV_BIT; 114} 115 116static int tick_add_compare(unsigned long adj) 117{ 118 unsigned long orig_tick, new_tick, new_compare; 119 120 __asm__ __volatile__("rd %%tick, %0" 121 : "=r" (orig_tick)); 122 123 orig_tick &= ~TICKCMP_IRQ_BIT; 124 125 __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" 126 " add %1, %2, %0\n\t" 127 ".align 64\n" 128 "1:\n\t" 129 "wr %0, 0, %%tick_cmpr\n\t" 130 "rd %%tick_cmpr, %%g0\n\t" 131 : "=r" (new_compare) 132 : "r" (orig_tick), "r" (adj)); 133 134 __asm__ __volatile__("rd %%tick, %0" 135 : "=r" (new_tick)); 136 new_tick &= ~TICKCMP_IRQ_BIT; 137 138 return ((long)(new_tick - (orig_tick+adj))) > 0L; 139} 140 141static unsigned long tick_add_tick(unsigned long adj) 142{ 143 unsigned long new_tick; 144 145 /* Also need to handle Blackbird bug here too. */ 146 __asm__ __volatile__("rd %%tick, %0\n\t" 147 "add %0, %1, %0\n\t" 148 "wrpr %0, 0, %%tick\n\t" 149 : "=&r" (new_tick) 150 : "r" (adj)); 151 152 return new_tick; 153} 154 155static struct sparc64_tick_ops tick_operations __read_mostly = { 156 .name = "tick", 157 .init_tick = tick_init_tick, 158 .disable_irq = tick_disable_irq, 159 .get_tick = tick_get_tick, 160 .add_tick = tick_add_tick, 161 .add_compare = tick_add_compare, 162 .softint_mask = 1UL << 0, 163}; 164 165struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations; 166EXPORT_SYMBOL(tick_ops); 167 168static void stick_disable_irq(void) 169{ 170 __asm__ __volatile__( 171 "wr %0, 0x0, %%asr25" 172 : /* no outputs */ 173 : "r" (TICKCMP_IRQ_BIT)); 174} 175 176static void stick_init_tick(void) 177{ 178 /* Writes to the %tick and %stick register are not 179 * allowed on sun4v. The Hypervisor controls that 180 * bit, per-strand. 181 */ 182 if (tlb_type != hypervisor) { 183 tick_disable_protection(); 184 tick_disable_irq(); 185 186 /* Let the user get at STICK too. */ 187 __asm__ __volatile__( 188 " rd %%asr24, %%g2\n" 189 " andn %%g2, %0, %%g2\n" 190 " wr %%g2, 0, %%asr24" 191 : /* no outputs */ 192 : "r" (TICK_PRIV_BIT) 193 : "g1", "g2"); 194 } 195 196 stick_disable_irq(); 197} 198 199static unsigned long long stick_get_tick(void) 200{ 201 unsigned long ret; 202 203 __asm__ __volatile__("rd %%asr24, %0" 204 : "=r" (ret)); 205 206 return ret & ~TICK_PRIV_BIT; 207} 208 209static unsigned long stick_add_tick(unsigned long adj) 210{ 211 unsigned long new_tick; 212 213 __asm__ __volatile__("rd %%asr24, %0\n\t" 214 "add %0, %1, %0\n\t" 215 "wr %0, 0, %%asr24\n\t" 216 : "=&r" (new_tick) 217 : "r" (adj)); 218 219 return new_tick; 220} 221 222static int stick_add_compare(unsigned long adj) 223{ 224 unsigned long orig_tick, new_tick; 225 226 __asm__ __volatile__("rd %%asr24, %0" 227 : "=r" (orig_tick)); 228 orig_tick &= ~TICKCMP_IRQ_BIT; 229 230 __asm__ __volatile__("wr %0, 0, %%asr25" 231 : /* no outputs */ 232 : "r" (orig_tick + adj)); 233 234 __asm__ __volatile__("rd %%asr24, %0" 235 : "=r" (new_tick)); 236 new_tick &= ~TICKCMP_IRQ_BIT; 237 238 return ((long)(new_tick - (orig_tick+adj))) > 0L; 239} 240 241static struct sparc64_tick_ops stick_operations __read_mostly = { 242 .name = "stick", 243 .init_tick = stick_init_tick, 244 .disable_irq = stick_disable_irq, 245 .get_tick = stick_get_tick, 246 .add_tick = stick_add_tick, 247 .add_compare = stick_add_compare, 248 .softint_mask = 1UL << 16, 249}; 250 251/* On Hummingbird the STICK/STICK_CMPR register is implemented 252 * in I/O space. There are two 64-bit registers each, the 253 * first holds the low 32-bits of the value and the second holds 254 * the high 32-bits. 255 * 256 * Since STICK is constantly updating, we have to access it carefully. 257 * 258 * The sequence we use to read is: 259 * 1) read high 260 * 2) read low 261 * 3) read high again, if it rolled re-read both low and high again. 262 * 263 * Writing STICK safely is also tricky: 264 * 1) write low to zero 265 * 2) write high 266 * 3) write low 267 */ 268#define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL 269#define HBIRD_STICK_ADDR 0x1fe0000f070UL 270 271static unsigned long __hbird_read_stick(void) 272{ 273 unsigned long ret, tmp1, tmp2, tmp3; 274 unsigned long addr = HBIRD_STICK_ADDR+8; 275 276 __asm__ __volatile__("ldxa [%1] %5, %2\n" 277 "1:\n\t" 278 "sub %1, 0x8, %1\n\t" 279 "ldxa [%1] %5, %3\n\t" 280 "add %1, 0x8, %1\n\t" 281 "ldxa [%1] %5, %4\n\t" 282 "cmp %4, %2\n\t" 283 "bne,a,pn %%xcc, 1b\n\t" 284 " mov %4, %2\n\t" 285 "sllx %4, 32, %4\n\t" 286 "or %3, %4, %0\n\t" 287 : "=&r" (ret), "=&r" (addr), 288 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3) 289 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr)); 290 291 return ret; 292} 293 294static void __hbird_write_stick(unsigned long val) 295{ 296 unsigned long low = (val & 0xffffffffUL); 297 unsigned long high = (val >> 32UL); 298 unsigned long addr = HBIRD_STICK_ADDR; 299 300 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t" 301 "add %0, 0x8, %0\n\t" 302 "stxa %3, [%0] %4\n\t" 303 "sub %0, 0x8, %0\n\t" 304 "stxa %2, [%0] %4" 305 : "=&r" (addr) 306 : "0" (addr), "r" (low), "r" (high), 307 "i" (ASI_PHYS_BYPASS_EC_E)); 308} 309 310static void __hbird_write_compare(unsigned long val) 311{ 312 unsigned long low = (val & 0xffffffffUL); 313 unsigned long high = (val >> 32UL); 314 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL; 315 316 __asm__ __volatile__("stxa %3, [%0] %4\n\t" 317 "sub %0, 0x8, %0\n\t" 318 "stxa %2, [%0] %4" 319 : "=&r" (addr) 320 : "0" (addr), "r" (low), "r" (high), 321 "i" (ASI_PHYS_BYPASS_EC_E)); 322} 323 324static void hbtick_disable_irq(void) 325{ 326 __hbird_write_compare(TICKCMP_IRQ_BIT); 327} 328 329static void hbtick_init_tick(void) 330{ 331 tick_disable_protection(); 332 333 __hbird_write_stick(__hbird_read_stick()); 334 335 hbtick_disable_irq(); 336} 337 338static unsigned long long hbtick_get_tick(void) 339{ 340 return __hbird_read_stick() & ~TICK_PRIV_BIT; 341} 342 343static unsigned long hbtick_add_tick(unsigned long adj) 344{ 345 unsigned long val; 346 347 val = __hbird_read_stick() + adj; 348 __hbird_write_stick(val); 349 350 return val; 351} 352 353static int hbtick_add_compare(unsigned long adj) 354{ 355 unsigned long val = __hbird_read_stick(); 356 unsigned long val2; 357 358 val &= ~TICKCMP_IRQ_BIT; 359 val += adj; 360 __hbird_write_compare(val); 361 362 val2 = __hbird_read_stick() & ~TICKCMP_IRQ_BIT; 363 364 return ((long)(val2 - val)) > 0L; 365} 366 367static struct sparc64_tick_ops hbtick_operations __read_mostly = { 368 .name = "hbtick", 369 .init_tick = hbtick_init_tick, 370 .disable_irq = hbtick_disable_irq, 371 .get_tick = hbtick_get_tick, 372 .add_tick = hbtick_add_tick, 373 .add_compare = hbtick_add_compare, 374 .softint_mask = 1UL << 0, 375}; 376 377static unsigned long timer_ticks_per_nsec_quotient __read_mostly; 378 379int update_persistent_clock(struct timespec now) 380{ 381 struct rtc_device *rtc = rtc_class_open("rtc0"); 382 int err = -1; 383 384 if (rtc) { 385 err = rtc_set_mmss(rtc, now.tv_sec); 386 rtc_class_close(rtc); 387 } 388 389 return err; 390} 391 392unsigned long cmos_regs; 393EXPORT_SYMBOL(cmos_regs); 394 395static struct resource rtc_cmos_resource; 396 397static struct platform_device rtc_cmos_device = { 398 .name = "rtc_cmos", 399 .id = -1, 400 .resource = &rtc_cmos_resource, 401 .num_resources = 1, 402}; 403 404static int __devinit rtc_probe(struct platform_device *op, const struct of_device_id *match) 405{ 406 struct resource *r; 407 408 printk(KERN_INFO "%s: RTC regs at 0x%llx\n", 409 op->dev.of_node->full_name, op->resource[0].start); 410 411 /* The CMOS RTC driver only accepts IORESOURCE_IO, so cons 412 * up a fake resource so that the probe works for all cases. 413 * When the RTC is behind an ISA bus it will have IORESOURCE_IO 414 * already, whereas when it's behind EBUS is will be IORESOURCE_MEM. 415 */ 416 417 r = &rtc_cmos_resource; 418 r->flags = IORESOURCE_IO; 419 r->name = op->resource[0].name; 420 r->start = op->resource[0].start; 421 r->end = op->resource[0].end; 422 423 cmos_regs = op->resource[0].start; 424 return platform_device_register(&rtc_cmos_device); 425} 426 427static struct of_device_id __initdata rtc_match[] = { 428 { 429 .name = "rtc", 430 .compatible = "m5819", 431 }, 432 { 433 .name = "rtc", 434 .compatible = "isa-m5819p", 435 }, 436 { 437 .name = "rtc", 438 .compatible = "isa-m5823p", 439 }, 440 { 441 .name = "rtc", 442 .compatible = "ds1287", 443 }, 444 {}, 445}; 446 447static struct of_platform_driver rtc_driver = { 448 .probe = rtc_probe, 449 .driver = { 450 .name = "rtc", 451 .owner = THIS_MODULE, 452 .of_match_table = rtc_match, 453 }, 454}; 455 456static struct platform_device rtc_bq4802_device = { 457 .name = "rtc-bq4802", 458 .id = -1, 459 .num_resources = 1, 460}; 461 462static int __devinit bq4802_probe(struct platform_device *op, const struct of_device_id *match) 463{ 464 465 printk(KERN_INFO "%s: BQ4802 regs at 0x%llx\n", 466 op->dev.of_node->full_name, op->resource[0].start); 467 468 rtc_bq4802_device.resource = &op->resource[0]; 469 return platform_device_register(&rtc_bq4802_device); 470} 471 472static struct of_device_id __initdata bq4802_match[] = { 473 { 474 .name = "rtc", 475 .compatible = "bq4802", 476 }, 477 {}, 478}; 479 480static struct of_platform_driver bq4802_driver = { 481 .probe = bq4802_probe, 482 .driver = { 483 .name = "bq4802", 484 .owner = THIS_MODULE, 485 .of_match_table = bq4802_match, 486 }, 487}; 488 489static unsigned char mostek_read_byte(struct device *dev, u32 ofs) 490{ 491 struct platform_device *pdev = to_platform_device(dev); 492 void __iomem *regs = (void __iomem *) pdev->resource[0].start; 493 494 return readb(regs + ofs); 495} 496 497static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) 498{ 499 struct platform_device *pdev = to_platform_device(dev); 500 void __iomem *regs = (void __iomem *) pdev->resource[0].start; 501 502 writeb(val, regs + ofs); 503} 504 505static struct m48t59_plat_data m48t59_data = { 506 .read_byte = mostek_read_byte, 507 .write_byte = mostek_write_byte, 508}; 509 510static struct platform_device m48t59_rtc = { 511 .name = "rtc-m48t59", 512 .id = 0, 513 .num_resources = 1, 514 .dev = { 515 .platform_data = &m48t59_data, 516 }, 517}; 518 519static int __devinit mostek_probe(struct platform_device *op, const struct of_device_id *match) 520{ 521 struct device_node *dp = op->dev.of_node; 522 523 /* On an Enterprise system there can be multiple mostek clocks. 524 * We should only match the one that is on the central FHC bus. 525 */ 526 if (!strcmp(dp->parent->name, "fhc") && 527 strcmp(dp->parent->parent->name, "central") != 0) 528 return -ENODEV; 529 530 printk(KERN_INFO "%s: Mostek regs at 0x%llx\n", 531 dp->full_name, op->resource[0].start); 532 533 m48t59_rtc.resource = &op->resource[0]; 534 return platform_device_register(&m48t59_rtc); 535} 536 537static struct of_device_id __initdata mostek_match[] = { 538 { 539 .name = "eeprom", 540 }, 541 {}, 542}; 543 544static struct of_platform_driver mostek_driver = { 545 .probe = mostek_probe, 546 .driver = { 547 .name = "mostek", 548 .owner = THIS_MODULE, 549 .of_match_table = mostek_match, 550 }, 551}; 552 553static struct platform_device rtc_sun4v_device = { 554 .name = "rtc-sun4v", 555 .id = -1, 556}; 557 558static struct platform_device rtc_starfire_device = { 559 .name = "rtc-starfire", 560 .id = -1, 561}; 562 563static int __init clock_init(void) 564{ 565 if (this_is_starfire) 566 return platform_device_register(&rtc_starfire_device); 567 568 if (tlb_type == hypervisor) 569 return platform_device_register(&rtc_sun4v_device); 570 571 (void) of_register_platform_driver(&rtc_driver); 572 (void) of_register_platform_driver(&mostek_driver); 573 (void) of_register_platform_driver(&bq4802_driver); 574 575 return 0; 576} 577 578/* Must be after subsys_initcall() so that busses are probed. Must 579 * be before device_initcall() because things like the RTC driver 580 * need to see the clock registers. 581 */ 582fs_initcall(clock_init); 583 584/* This is gets the master TICK_INT timer going. */ 585static unsigned long sparc64_init_timers(void) 586{ 587 struct device_node *dp; 588 unsigned long freq; 589 590 dp = of_find_node_by_path("/"); 591 if (tlb_type == spitfire) { 592 unsigned long ver, manuf, impl; 593 594 __asm__ __volatile__ ("rdpr %%ver, %0" 595 : "=&r" (ver)); 596 manuf = ((ver >> 48) & 0xffff); 597 impl = ((ver >> 32) & 0xffff); 598 if (manuf == 0x17 && impl == 0x13) { 599 /* Hummingbird, aka Ultra-IIe */ 600 tick_ops = &hbtick_operations; 601 freq = of_getintprop_default(dp, "stick-frequency", 0); 602 } else { 603 tick_ops = &tick_operations; 604 freq = local_cpu_data().clock_tick; 605 } 606 } else { 607 tick_ops = &stick_operations; 608 freq = of_getintprop_default(dp, "stick-frequency", 0); 609 } 610 611 return freq; 612} 613 614struct freq_table { 615 unsigned long clock_tick_ref; 616 unsigned int ref_freq; 617}; 618static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0 }; 619 620unsigned long sparc64_get_clock_tick(unsigned int cpu) 621{ 622 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu); 623 624 if (ft->clock_tick_ref) 625 return ft->clock_tick_ref; 626 return cpu_data(cpu).clock_tick; 627} 628EXPORT_SYMBOL(sparc64_get_clock_tick); 629 630#ifdef CONFIG_CPU_FREQ 631 632static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 633 void *data) 634{ 635 struct cpufreq_freqs *freq = data; 636 unsigned int cpu = freq->cpu; 637 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu); 638 639 if (!ft->ref_freq) { 640 ft->ref_freq = freq->old; 641 ft->clock_tick_ref = cpu_data(cpu).clock_tick; 642 } 643 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 644 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || 645 (val == CPUFREQ_RESUMECHANGE)) { 646 cpu_data(cpu).clock_tick = 647 cpufreq_scale(ft->clock_tick_ref, 648 ft->ref_freq, 649 freq->new); 650 } 651 652 return 0; 653} 654 655static struct notifier_block sparc64_cpufreq_notifier_block = { 656 .notifier_call = sparc64_cpufreq_notifier 657}; 658 659static int __init register_sparc64_cpufreq_notifier(void) 660{ 661 662 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block, 663 CPUFREQ_TRANSITION_NOTIFIER); 664 return 0; 665} 666 667core_initcall(register_sparc64_cpufreq_notifier); 668 669#endif /* CONFIG_CPU_FREQ */ 670 671static int sparc64_next_event(unsigned long delta, 672 struct clock_event_device *evt) 673{ 674 return tick_ops->add_compare(delta) ? -ETIME : 0; 675} 676 677static void sparc64_timer_setup(enum clock_event_mode mode, 678 struct clock_event_device *evt) 679{ 680 switch (mode) { 681 case CLOCK_EVT_MODE_ONESHOT: 682 case CLOCK_EVT_MODE_RESUME: 683 break; 684 685 case CLOCK_EVT_MODE_SHUTDOWN: 686 tick_ops->disable_irq(); 687 break; 688 689 case CLOCK_EVT_MODE_PERIODIC: 690 case CLOCK_EVT_MODE_UNUSED: 691 WARN_ON(1); 692 break; 693 }; 694} 695 696static struct clock_event_device sparc64_clockevent = { 697 .features = CLOCK_EVT_FEAT_ONESHOT, 698 .set_mode = sparc64_timer_setup, 699 .set_next_event = sparc64_next_event, 700 .rating = 100, 701 .shift = 30, 702 .irq = -1, 703}; 704static DEFINE_PER_CPU(struct clock_event_device, sparc64_events); 705 706void __irq_entry timer_interrupt(int irq, struct pt_regs *regs) 707{ 708 struct pt_regs *old_regs = set_irq_regs(regs); 709 unsigned long tick_mask = tick_ops->softint_mask; 710 int cpu = smp_processor_id(); 711 struct clock_event_device *evt = &per_cpu(sparc64_events, cpu); 712 713 clear_softint(tick_mask); 714 715 irq_enter(); 716 717 local_cpu_data().irq0_irqs++; 718 kstat_incr_irqs_this_cpu(0, irq_to_desc(0)); 719 720 if (unlikely(!evt->event_handler)) { 721 printk(KERN_WARNING 722 "Spurious SPARC64 timer interrupt on cpu %d\n", cpu); 723 } else 724 evt->event_handler(evt); 725 726 irq_exit(); 727 728 set_irq_regs(old_regs); 729} 730 731void __devinit setup_sparc64_timer(void) 732{ 733 struct clock_event_device *sevt; 734 unsigned long pstate; 735 736 /* Guarantee that the following sequences execute 737 * uninterrupted. 738 */ 739 __asm__ __volatile__("rdpr %%pstate, %0\n\t" 740 "wrpr %0, %1, %%pstate" 741 : "=r" (pstate) 742 : "i" (PSTATE_IE)); 743 744 tick_ops->init_tick(); 745 746 /* Restore PSTATE_IE. */ 747 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" 748 : /* no outputs */ 749 : "r" (pstate)); 750 751 sevt = &__get_cpu_var(sparc64_events); 752 753 memcpy(sevt, &sparc64_clockevent, sizeof(*sevt)); 754 sevt->cpumask = cpumask_of(smp_processor_id()); 755 756 clockevents_register_device(sevt); 757} 758 759#define SPARC64_NSEC_PER_CYC_SHIFT 10UL 760 761static struct clocksource clocksource_tick = { 762 .rating = 100, 763 .mask = CLOCKSOURCE_MASK(64), 764 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 765}; 766 767static unsigned long tb_ticks_per_usec __read_mostly; 768 769void __delay(unsigned long loops) 770{ 771 unsigned long bclock, now; 772 773 bclock = tick_ops->get_tick(); 774 do { 775 now = tick_ops->get_tick(); 776 } while ((now-bclock) < loops); 777} 778EXPORT_SYMBOL(__delay); 779 780void udelay(unsigned long usecs) 781{ 782 __delay(tb_ticks_per_usec * usecs); 783} 784EXPORT_SYMBOL(udelay); 785 786static cycle_t clocksource_tick_read(struct clocksource *cs) 787{ 788 return tick_ops->get_tick(); 789} 790 791void __init time_init(void) 792{ 793 unsigned long freq = sparc64_init_timers(); 794 795 tb_ticks_per_usec = freq / USEC_PER_SEC; 796 797 timer_ticks_per_nsec_quotient = 798 clocksource_hz2mult(freq, SPARC64_NSEC_PER_CYC_SHIFT); 799 800 clocksource_tick.name = tick_ops->name; 801 clocksource_calc_mult_shift(&clocksource_tick, freq, 4); 802 clocksource_tick.read = clocksource_tick_read; 803 804 printk("clocksource: mult[%x] shift[%d]\n", 805 clocksource_tick.mult, clocksource_tick.shift); 806 807 clocksource_register(&clocksource_tick); 808 809 sparc64_clockevent.name = tick_ops->name; 810 clockevents_calc_mult_shift(&sparc64_clockevent, freq, 4); 811 812 sparc64_clockevent.max_delta_ns = 813 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent); 814 sparc64_clockevent.min_delta_ns = 815 clockevent_delta2ns(0xF, &sparc64_clockevent); 816 817 printk("clockevent: mult[%x] shift[%d]\n", 818 sparc64_clockevent.mult, sparc64_clockevent.shift); 819 820 setup_sparc64_timer(); 821} 822 823unsigned long long sched_clock(void) 824{ 825 unsigned long ticks = tick_ops->get_tick(); 826 827 return (ticks * timer_ticks_per_nsec_quotient) 828 >> SPARC64_NSEC_PER_CYC_SHIFT; 829} 830 831int __devinit read_current_timer(unsigned long *timer_val) 832{ 833 *timer_val = tick_ops->get_tick(); 834 return 0; 835} 836