1/* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. 2 * 3 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6#include <linux/kernel.h> 7#include <linux/types.h> 8#include <linux/pci.h> 9#include <linux/init.h> 10#include <linux/slab.h> 11#include <linux/interrupt.h> 12#include <linux/of_device.h> 13 14#include <asm/iommu.h> 15#include <asm/irq.h> 16#include <asm/pstate.h> 17#include <asm/prom.h> 18#include <asm/upa.h> 19 20#include "pci_impl.h" 21#include "iommu_common.h" 22 23#define DRIVER_NAME "schizo" 24#define PFX DRIVER_NAME ": " 25 26/* This is a convention that at least Excalibur and Merlin 27 * follow. I suppose the SCHIZO used in Starcat and friends 28 * will do similar. 29 * 30 * The only way I could see this changing is if the newlink 31 * block requires more space in Schizo's address space than 32 * they predicted, thus requiring an address space reorg when 33 * the newer Schizo is taped out. 34 */ 35 36/* Streaming buffer control register. */ 37#define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ 38#define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ 39#define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ 40#define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 41#define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ 42 43/* IOMMU control register. */ 44#define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ 45#define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ 46#define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ 47#define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ 48#define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ 49#define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 50#define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ 51#define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ 52#define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ 53#define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ 54#define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ 55#define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ 56#define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ 57#define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ 58#define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ 59#define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ 60#define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ 61#define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 62 63/* Schizo config space address format is nearly identical to 64 * that of PSYCHO: 65 * 66 * 32 24 23 16 15 11 10 8 7 2 1 0 67 * --------------------------------------------------------- 68 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 | 69 * --------------------------------------------------------- 70 */ 71#define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space) 72#define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ 73 (((unsigned long)(BUS) << 16) | \ 74 ((unsigned long)(DEVFN) << 8) | \ 75 ((unsigned long)(REG))) 76 77static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm, 78 unsigned char bus, 79 unsigned int devfn, 80 int where) 81{ 82 if (!pbm) 83 return NULL; 84 bus -= pbm->pci_first_busno; 85 return (void *) 86 (SCHIZO_CONFIG_BASE(pbm) | 87 SCHIZO_CONFIG_ENCODE(bus, devfn, where)); 88} 89 90/* SCHIZO error handling support. */ 91enum schizo_error_type { 92 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR 93}; 94 95static DEFINE_SPINLOCK(stc_buf_lock); 96static unsigned long stc_error_buf[128]; 97static unsigned long stc_tag_buf[16]; 98static unsigned long stc_line_buf[16]; 99 100#define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */ 101#define SCHIZO_CE_INO 0x31 /* Correctable ECC error */ 102#define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */ 103#define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ 104#define SCHIZO_SERR_INO 0x34 /* Safari interface error */ 105 106#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ 107#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ 108#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ 109 110#define SCHIZO_STCERR_WRITE 0x2UL 111#define SCHIZO_STCERR_READ 0x1UL 112 113#define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL 114#define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL 115#define SCHIZO_STCTAG_VALID 0x8000000000000000UL 116#define SCHIZO_STCTAG_READ 0x4000000000000000UL 117 118#define SCHIZO_STCLINE_LINDX 0x0000000007800000UL 119#define SCHIZO_STCLINE_SPTR 0x000000000007e000UL 120#define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL 121#define SCHIZO_STCLINE_EPTR 0x000000000000003fUL 122#define SCHIZO_STCLINE_VALID 0x0000000000600000UL 123#define SCHIZO_STCLINE_FOFN 0x0000000000180000UL 124 125static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm, 126 enum schizo_error_type type) 127{ 128 struct strbuf *strbuf = &pbm->stc; 129 unsigned long regbase = pbm->pbm_regs; 130 unsigned long err_base, tag_base, line_base; 131 u64 control; 132 int i; 133 134 err_base = regbase + SCHIZO_STC_ERR; 135 tag_base = regbase + SCHIZO_STC_TAG; 136 line_base = regbase + SCHIZO_STC_LINE; 137 138 spin_lock(&stc_buf_lock); 139 140 /* This is __REALLY__ dangerous. When we put the 141 * streaming buffer into diagnostic mode to probe 142 * it's tags and error status, we _must_ clear all 143 * of the line tag valid bits before re-enabling 144 * the streaming buffer. If any dirty data lives 145 * in the STC when we do this, we will end up 146 * invalidating it before it has a chance to reach 147 * main memory. 148 */ 149 control = upa_readq(strbuf->strbuf_control); 150 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), 151 strbuf->strbuf_control); 152 for (i = 0; i < 128; i++) { 153 unsigned long val; 154 155 val = upa_readq(err_base + (i * 8UL)); 156 upa_writeq(0UL, err_base + (i * 8UL)); 157 stc_error_buf[i] = val; 158 } 159 for (i = 0; i < 16; i++) { 160 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL)); 161 stc_line_buf[i] = upa_readq(line_base + (i * 8UL)); 162 upa_writeq(0UL, tag_base + (i * 8UL)); 163 upa_writeq(0UL, line_base + (i * 8UL)); 164 } 165 166 /* OK, state is logged, exit diagnostic mode. */ 167 upa_writeq(control, strbuf->strbuf_control); 168 169 for (i = 0; i < 16; i++) { 170 int j, saw_error, first, last; 171 172 saw_error = 0; 173 first = i * 8; 174 last = first + 8; 175 for (j = first; j < last; j++) { 176 unsigned long errval = stc_error_buf[j]; 177 if (errval != 0) { 178 saw_error++; 179 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", 180 pbm->name, 181 j, 182 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, 183 (errval & SCHIZO_STCERR_READ) ? 1 : 0); 184 } 185 } 186 if (saw_error != 0) { 187 unsigned long tagval = stc_tag_buf[i]; 188 unsigned long lineval = stc_line_buf[i]; 189 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n", 190 pbm->name, 191 i, 192 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), 193 (tagval & SCHIZO_STCTAG_VPN), 194 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), 195 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); 196 197 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" 198 "V(%d)FOFN(%d)]\n", 199 pbm->name, 200 i, 201 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), 202 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), 203 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), 204 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), 205 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), 206 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); 207 } 208 } 209 210 spin_unlock(&stc_buf_lock); 211} 212 213/* IOMMU is per-PBM in Schizo, so interrogate both for anonymous 214 * controller level errors. 215 */ 216 217#define SCHIZO_IOMMU_TAG 0xa580UL 218#define SCHIZO_IOMMU_DATA 0xa600UL 219 220#define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL 221#define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL 222#define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL 223#define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL 224#define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL 225#define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL 226#define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL 227 228#define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL 229#define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL 230#define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL 231 232static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm, 233 enum schizo_error_type type) 234{ 235 struct iommu *iommu = pbm->iommu; 236 unsigned long iommu_tag[16]; 237 unsigned long iommu_data[16]; 238 unsigned long flags; 239 u64 control; 240 int i; 241 242 spin_lock_irqsave(&iommu->lock, flags); 243 control = upa_readq(iommu->iommu_control); 244 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { 245 unsigned long base; 246 char *type_string; 247 248 /* Clear the error encountered bit. */ 249 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; 250 upa_writeq(control, iommu->iommu_control); 251 252 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { 253 case 0: 254 type_string = "Protection Error"; 255 break; 256 case 1: 257 type_string = "Invalid Error"; 258 break; 259 case 2: 260 type_string = "TimeOut Error"; 261 break; 262 case 3: 263 default: 264 type_string = "ECC Error"; 265 break; 266 }; 267 printk("%s: IOMMU Error, type[%s]\n", 268 pbm->name, type_string); 269 270 /* Put the IOMMU into diagnostic mode and probe 271 * it's TLB for entries with error status. 272 * 273 * It is very possible for another DVMA to occur 274 * while we do this probe, and corrupt the system 275 * further. But we are so screwed at this point 276 * that we are likely to crash hard anyways, so 277 * get as much diagnostic information to the 278 * console as we can. 279 */ 280 upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB, 281 iommu->iommu_control); 282 283 base = pbm->pbm_regs; 284 285 for (i = 0; i < 16; i++) { 286 iommu_tag[i] = 287 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL)); 288 iommu_data[i] = 289 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL)); 290 291 /* Now clear out the entry. */ 292 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL)); 293 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL)); 294 } 295 296 /* Leave diagnostic mode. */ 297 upa_writeq(control, iommu->iommu_control); 298 299 for (i = 0; i < 16; i++) { 300 unsigned long tag, data; 301 302 tag = iommu_tag[i]; 303 if (!(tag & SCHIZO_IOMMU_TAG_ERR)) 304 continue; 305 306 data = iommu_data[i]; 307 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { 308 case 0: 309 type_string = "Protection Error"; 310 break; 311 case 1: 312 type_string = "Invalid Error"; 313 break; 314 case 2: 315 type_string = "TimeOut Error"; 316 break; 317 case 3: 318 default: 319 type_string = "ECC Error"; 320 break; 321 }; 322 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) " 323 "sz(%dK) vpg(%08lx)]\n", 324 pbm->name, i, type_string, 325 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), 326 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), 327 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), 328 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8), 329 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); 330 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", 331 pbm->name, i, 332 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), 333 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), 334 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); 335 } 336 } 337 if (pbm->stc.strbuf_enabled) 338 __schizo_check_stc_error_pbm(pbm, type); 339 spin_unlock_irqrestore(&iommu->lock, flags); 340} 341 342static void schizo_check_iommu_error(struct pci_pbm_info *pbm, 343 enum schizo_error_type type) 344{ 345 schizo_check_iommu_error_pbm(pbm, type); 346 if (pbm->sibling) 347 schizo_check_iommu_error_pbm(pbm->sibling, type); 348} 349 350/* Uncorrectable ECC error status gathering. */ 351#define SCHIZO_UE_AFSR 0x10030UL 352#define SCHIZO_UE_AFAR 0x10038UL 353 354#define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */ 355#define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */ 356#define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */ 357#define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */ 358#define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */ 359#define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */ 360#define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */ 361#define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */ 362#define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */ 363#define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */ 364#define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */ 365#define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */ 366#define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */ 367#define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */ 368 369static irqreturn_t schizo_ue_intr(int irq, void *dev_id) 370{ 371 struct pci_pbm_info *pbm = dev_id; 372 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR; 373 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR; 374 unsigned long afsr, afar, error_bits; 375 int reported, limit; 376 377 /* Latch uncorrectable error status. */ 378 afar = upa_readq(afar_reg); 379 380 /* If either of the error pending bits are set in the 381 * AFSR, the error status is being actively updated by 382 * the hardware and we must re-read to get a clean value. 383 */ 384 limit = 1000; 385 do { 386 afsr = upa_readq(afsr_reg); 387 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 388 389 /* Clear the primary/secondary error status bits. */ 390 error_bits = afsr & 391 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR | 392 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); 393 if (!error_bits) 394 return IRQ_NONE; 395 upa_writeq(error_bits, afsr_reg); 396 397 /* Log the error. */ 398 printk("%s: Uncorrectable Error, primary error type[%s]\n", 399 pbm->name, 400 (((error_bits & SCHIZO_UEAFSR_PPIO) ? 401 "PIO" : 402 ((error_bits & SCHIZO_UEAFSR_PDRD) ? 403 "DMA Read" : 404 ((error_bits & SCHIZO_UEAFSR_PDWR) ? 405 "DMA Write" : "???"))))); 406 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 407 pbm->name, 408 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 409 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 410 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 411 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 412 pbm->name, 413 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 414 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 415 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 416 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 417 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 418 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 419 printk("%s: UE Secondary errors [", pbm->name); 420 reported = 0; 421 if (afsr & SCHIZO_UEAFSR_SPIO) { 422 reported++; 423 printk("(PIO)"); 424 } 425 if (afsr & SCHIZO_UEAFSR_SDMA) { 426 reported++; 427 printk("(DMA)"); 428 } 429 if (!reported) 430 printk("(none)"); 431 printk("]\n"); 432 433 /* Interrogate IOMMU for error status. */ 434 schizo_check_iommu_error(pbm, UE_ERR); 435 436 return IRQ_HANDLED; 437} 438 439#define SCHIZO_CE_AFSR 0x10040UL 440#define SCHIZO_CE_AFAR 0x10048UL 441 442#define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL 443#define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL 444#define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL 445#define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL 446#define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL 447#define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL 448#define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL 449#define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL 450#define SCHIZO_CEAFSR_AID 0x000000001f000000UL 451#define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL 452#define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL 453#define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL 454#define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL 455#define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL 456 457static irqreturn_t schizo_ce_intr(int irq, void *dev_id) 458{ 459 struct pci_pbm_info *pbm = dev_id; 460 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR; 461 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR; 462 unsigned long afsr, afar, error_bits; 463 int reported, limit; 464 465 /* Latch error status. */ 466 afar = upa_readq(afar_reg); 467 468 /* If either of the error pending bits are set in the 469 * AFSR, the error status is being actively updated by 470 * the hardware and we must re-read to get a clean value. 471 */ 472 limit = 1000; 473 do { 474 afsr = upa_readq(afsr_reg); 475 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 476 477 /* Clear primary/secondary error status bits. */ 478 error_bits = afsr & 479 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR | 480 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); 481 if (!error_bits) 482 return IRQ_NONE; 483 upa_writeq(error_bits, afsr_reg); 484 485 /* Log the error. */ 486 printk("%s: Correctable Error, primary error type[%s]\n", 487 pbm->name, 488 (((error_bits & SCHIZO_CEAFSR_PPIO) ? 489 "PIO" : 490 ((error_bits & SCHIZO_CEAFSR_PDRD) ? 491 "DMA Read" : 492 ((error_bits & SCHIZO_CEAFSR_PDWR) ? 493 "DMA Write" : "???"))))); 494 495 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 496 pbm->name, 497 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 498 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 499 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 500 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 501 pbm->name, 502 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 503 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 504 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 505 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 506 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 507 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 508 printk("%s: CE Secondary errors [", pbm->name); 509 reported = 0; 510 if (afsr & SCHIZO_CEAFSR_SPIO) { 511 reported++; 512 printk("(PIO)"); 513 } 514 if (afsr & SCHIZO_CEAFSR_SDMA) { 515 reported++; 516 printk("(DMA)"); 517 } 518 if (!reported) 519 printk("(none)"); 520 printk("]\n"); 521 522 return IRQ_HANDLED; 523} 524 525#define SCHIZO_PCI_AFSR 0x2010UL 526#define SCHIZO_PCI_AFAR 0x2018UL 527 528#define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */ 529#define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */ 530#define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */ 531#define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */ 532#define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */ 533#define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */ 534#define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */ 535#define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */ 536#define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */ 537#define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */ 538#define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */ 539#define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */ 540#define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */ 541#define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */ 542#define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */ 543#define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */ 544#define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */ 545 546#define SCHIZO_PCI_CTRL (0x2000UL) 547#define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */ 548#define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */ 549#define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */ 550#define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */ 551#define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */ 552#define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */ 553#define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */ 554#define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */ 555#define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */ 556#define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */ 557#define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */ 558#define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */ 559#define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */ 560#define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */ 561#define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */ 562#define SCHIZO_PCICTRL_PTO_SHIFT 24UL 563#define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */ 564#define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */ 565#define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */ 566#define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */ 567#define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */ 568#define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */ 569#define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */ 570#define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */ 571#define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */ 572#define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */ 573#define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */ 574 575static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm) 576{ 577 unsigned long csr_reg, csr, csr_error_bits; 578 irqreturn_t ret = IRQ_NONE; 579 u16 stat; 580 581 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; 582 csr = upa_readq(csr_reg); 583 csr_error_bits = 584 csr & (SCHIZO_PCICTRL_BUS_UNUS | 585 SCHIZO_PCICTRL_TTO_ERR | 586 SCHIZO_PCICTRL_RTRY_ERR | 587 SCHIZO_PCICTRL_DTO_ERR | 588 SCHIZO_PCICTRL_SBH_ERR | 589 SCHIZO_PCICTRL_SERR); 590 if (csr_error_bits) { 591 /* Clear the errors. */ 592 upa_writeq(csr, csr_reg); 593 594 /* Log 'em. */ 595 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) 596 printk("%s: Bus unusable error asserted.\n", 597 pbm->name); 598 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR) 599 printk("%s: PCI TRDY# timeout error asserted.\n", 600 pbm->name); 601 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR) 602 printk("%s: PCI excessive retry error asserted.\n", 603 pbm->name); 604 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR) 605 printk("%s: PCI discard timeout error asserted.\n", 606 pbm->name); 607 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR) 608 printk("%s: PCI streaming byte hole error asserted.\n", 609 pbm->name); 610 if (csr_error_bits & SCHIZO_PCICTRL_SERR) 611 printk("%s: PCI SERR signal asserted.\n", 612 pbm->name); 613 ret = IRQ_HANDLED; 614 } 615 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat); 616 if (stat & (PCI_STATUS_PARITY | 617 PCI_STATUS_SIG_TARGET_ABORT | 618 PCI_STATUS_REC_TARGET_ABORT | 619 PCI_STATUS_REC_MASTER_ABORT | 620 PCI_STATUS_SIG_SYSTEM_ERROR)) { 621 printk("%s: PCI bus error, PCI_STATUS[%04x]\n", 622 pbm->name, stat); 623 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff); 624 ret = IRQ_HANDLED; 625 } 626 return ret; 627} 628 629static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id) 630{ 631 struct pci_pbm_info *pbm = dev_id; 632 unsigned long afsr_reg, afar_reg, base; 633 unsigned long afsr, afar, error_bits; 634 int reported; 635 636 base = pbm->pbm_regs; 637 638 afsr_reg = base + SCHIZO_PCI_AFSR; 639 afar_reg = base + SCHIZO_PCI_AFAR; 640 641 /* Latch error status. */ 642 afar = upa_readq(afar_reg); 643 afsr = upa_readq(afsr_reg); 644 645 /* Clear primary/secondary error status bits. */ 646 error_bits = afsr & 647 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 648 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 649 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 650 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 651 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 652 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); 653 if (!error_bits) 654 return schizo_pcierr_intr_other(pbm); 655 upa_writeq(error_bits, afsr_reg); 656 657 /* Log the error. */ 658 printk("%s: PCI Error, primary error type[%s]\n", 659 pbm->name, 660 (((error_bits & SCHIZO_PCIAFSR_PMA) ? 661 "Master Abort" : 662 ((error_bits & SCHIZO_PCIAFSR_PTA) ? 663 "Target Abort" : 664 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ? 665 "Excessive Retries" : 666 ((error_bits & SCHIZO_PCIAFSR_PPERR) ? 667 "Parity Error" : 668 ((error_bits & SCHIZO_PCIAFSR_PTTO) ? 669 "Timeout" : 670 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ? 671 "Bus Unusable" : "???")))))))); 672 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n", 673 pbm->name, 674 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, 675 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, 676 ((afsr & SCHIZO_PCIAFSR_CFG) ? 677 "Config" : 678 ((afsr & SCHIZO_PCIAFSR_MEM) ? 679 "Memory" : 680 ((afsr & SCHIZO_PCIAFSR_IO) ? 681 "I/O" : "???")))); 682 printk("%s: PCI AFAR [%016lx]\n", 683 pbm->name, afar); 684 printk("%s: PCI Secondary errors [", 685 pbm->name); 686 reported = 0; 687 if (afsr & SCHIZO_PCIAFSR_SMA) { 688 reported++; 689 printk("(Master Abort)"); 690 } 691 if (afsr & SCHIZO_PCIAFSR_STA) { 692 reported++; 693 printk("(Target Abort)"); 694 } 695 if (afsr & SCHIZO_PCIAFSR_SRTRY) { 696 reported++; 697 printk("(Excessive Retries)"); 698 } 699 if (afsr & SCHIZO_PCIAFSR_SPERR) { 700 reported++; 701 printk("(Parity Error)"); 702 } 703 if (afsr & SCHIZO_PCIAFSR_STTO) { 704 reported++; 705 printk("(Timeout)"); 706 } 707 if (afsr & SCHIZO_PCIAFSR_SUNUS) { 708 reported++; 709 printk("(Bus Unusable)"); 710 } 711 if (!reported) 712 printk("(none)"); 713 printk("]\n"); 714 715 /* For the error types shown, scan PBM's PCI bus for devices 716 * which have logged that error type. 717 */ 718 719 /* If we see a Target Abort, this could be the result of an 720 * IOMMU translation error of some sort. It is extremely 721 * useful to log this information as usually it indicates 722 * a bug in the IOMMU support code or a PCI device driver. 723 */ 724 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { 725 schizo_check_iommu_error(pbm, PCI_ERR); 726 pci_scan_for_target_abort(pbm, pbm->pci_bus); 727 } 728 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) 729 pci_scan_for_master_abort(pbm, pbm->pci_bus); 730 731 /* For excessive retries, PSYCHO/PBM will abort the device 732 * and there is no way to specifically check for excessive 733 * retries in the config space status registers. So what 734 * we hope is that we'll catch it via the master/target 735 * abort events. 736 */ 737 738 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) 739 pci_scan_for_parity_error(pbm, pbm->pci_bus); 740 741 return IRQ_HANDLED; 742} 743 744#define SCHIZO_SAFARI_ERRLOG 0x10018UL 745 746#define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL 747 748#define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */ 749#define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */ 750#define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */ 751#define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */ 752#define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */ 753#define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */ 754#define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */ 755#define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */ 756#define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */ 757#define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */ 758#define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */ 759#define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */ 760#define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */ 761#define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */ 762#define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */ 763#define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */ 764#define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */ 765#define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */ 766#define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */ 767#define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */ 768#define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */ 769#define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */ 770#define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */ 771#define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */ 772#define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */ 773#define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */ 774#define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */ 775#define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */ 776#define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */ 777#define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */ 778#define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */ 779 780/* We only expect UNMAP errors here. The rest of the Safari errors 781 * are marked fatal and thus cause a system reset. 782 */ 783static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id) 784{ 785 struct pci_pbm_info *pbm = dev_id; 786 u64 errlog; 787 788 errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 789 upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT), 790 pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 791 792 if (!(errlog & BUS_ERROR_UNMAP)) { 793 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n", 794 pbm->name, errlog); 795 796 return IRQ_HANDLED; 797 } 798 799 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", 800 pbm->name); 801 schizo_check_iommu_error(pbm, SAFARI_ERR); 802 803 return IRQ_HANDLED; 804} 805 806/* Nearly identical to PSYCHO equivalents... */ 807#define SCHIZO_ECC_CTRL 0x10020UL 808#define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 809#define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ 810#define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 811 812#define SCHIZO_SAFARI_ERRCTRL 0x10008UL 813#define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL 814#define SCHIZO_SAFARI_IRQCTRL 0x10010UL 815#define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL 816 817static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino) 818{ 819 ino &= IMAP_INO; 820 821 if (pbm->ino_bitmap & (1UL << ino)) 822 return 1; 823 824 return 0; 825} 826 827/* How the Tomatillo IRQs are routed around is pure guesswork here. 828 * 829 * All the Tomatillo devices I see in prtconf dumps seem to have only 830 * a single PCI bus unit attached to it. It would seem they are separate 831 * devices because their PortID (ie. JBUS ID) values are all different 832 * and thus the registers are mapped to totally different locations. 833 * 834 * However, two Tomatillo's look "similar" in that the only difference 835 * in their PortID is the lowest bit. 836 * 837 * So if we were to ignore this lower bit, it certainly looks like two 838 * PCI bus units of the same Tomatillo. I still have not really 839 * figured this out... 840 */ 841static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm) 842{ 843 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 844 u64 tmp, err_mask, err_no_mask; 845 int err; 846 847 /* Tomatillo IRQ property layout is: 848 * 0: PCIERR 849 * 1: UE ERR 850 * 2: CE ERR 851 * 3: SERR 852 * 4: POWER FAIL? 853 */ 854 855 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 856 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 857 "TOMATILLO_UE", pbm); 858 if (err) 859 printk(KERN_WARNING "%s: Could not register UE, " 860 "err=%d\n", pbm->name, err); 861 } 862 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 863 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 864 "TOMATILLO_CE", pbm); 865 if (err) 866 printk(KERN_WARNING "%s: Could not register CE, " 867 "err=%d\n", pbm->name, err); 868 } 869 err = 0; 870 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 871 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 872 "TOMATILLO_PCIERR", pbm); 873 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 874 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 875 "TOMATILLO_PCIERR", pbm); 876 } 877 if (err) 878 printk(KERN_WARNING "%s: Could not register PCIERR, " 879 "err=%d\n", pbm->name, err); 880 881 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 882 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 883 "TOMATILLO_SERR", pbm); 884 if (err) 885 printk(KERN_WARNING "%s: Could not register SERR, " 886 "err=%d\n", pbm->name, err); 887 } 888 889 /* Enable UE and CE interrupts for controller. */ 890 upa_writeq((SCHIZO_ECCCTRL_EE | 891 SCHIZO_ECCCTRL_UE | 892 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 893 894 /* Enable PCI Error interrupts and clear error 895 * bits. 896 */ 897 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 898 SCHIZO_PCICTRL_TTO_ERR | 899 SCHIZO_PCICTRL_RTRY_ERR | 900 SCHIZO_PCICTRL_SERR | 901 SCHIZO_PCICTRL_EEN); 902 903 err_no_mask = SCHIZO_PCICTRL_DTO_ERR; 904 905 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 906 tmp |= err_mask; 907 tmp &= ~err_no_mask; 908 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 909 910 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 911 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 912 SCHIZO_PCIAFSR_PTTO | 913 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 914 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 915 SCHIZO_PCIAFSR_STTO); 916 917 upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR); 918 919 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | 920 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | 921 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA | 922 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO | 923 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR | 924 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B | 925 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR | 926 BUS_ERROR_APERR | BUS_ERROR_UNMAP | 927 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); 928 929 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 930 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 931 932 upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)), 933 pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL); 934} 935 936static void schizo_register_error_handlers(struct pci_pbm_info *pbm) 937{ 938 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 939 u64 tmp, err_mask, err_no_mask; 940 int err; 941 942 /* Schizo IRQ property layout is: 943 * 0: PCIERR 944 * 1: UE ERR 945 * 2: CE ERR 946 * 3: SERR 947 * 4: POWER FAIL? 948 */ 949 950 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 951 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 952 "SCHIZO_UE", pbm); 953 if (err) 954 printk(KERN_WARNING "%s: Could not register UE, " 955 "err=%d\n", pbm->name, err); 956 } 957 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 958 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 959 "SCHIZO_CE", pbm); 960 if (err) 961 printk(KERN_WARNING "%s: Could not register CE, " 962 "err=%d\n", pbm->name, err); 963 } 964 err = 0; 965 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 966 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 967 "SCHIZO_PCIERR", pbm); 968 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 969 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 970 "SCHIZO_PCIERR", pbm); 971 } 972 if (err) 973 printk(KERN_WARNING "%s: Could not register PCIERR, " 974 "err=%d\n", pbm->name, err); 975 976 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 977 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 978 "SCHIZO_SERR", pbm); 979 if (err) 980 printk(KERN_WARNING "%s: Could not register SERR, " 981 "err=%d\n", pbm->name, err); 982 } 983 984 /* Enable UE and CE interrupts for controller. */ 985 upa_writeq((SCHIZO_ECCCTRL_EE | 986 SCHIZO_ECCCTRL_UE | 987 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 988 989 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 990 SCHIZO_PCICTRL_ESLCK | 991 SCHIZO_PCICTRL_TTO_ERR | 992 SCHIZO_PCICTRL_RTRY_ERR | 993 SCHIZO_PCICTRL_SBH_ERR | 994 SCHIZO_PCICTRL_SERR | 995 SCHIZO_PCICTRL_EEN); 996 997 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR | 998 SCHIZO_PCICTRL_SBH_INT); 999 1000 /* Enable PCI Error interrupts and clear error 1001 * bits for each PBM. 1002 */ 1003 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1004 tmp |= err_mask; 1005 tmp &= ~err_no_mask; 1006 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1007 1008 upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1009 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1010 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 1011 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 1012 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 1013 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS), 1014 pbm->pbm_regs + SCHIZO_PCI_AFSR); 1015 1016 /* Make all Safari error conditions fatal except unmapped 1017 * errors which we make generate interrupts. 1018 */ 1019 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS | 1020 BUS_ERROR_BADMA | BUS_ERROR_BADMB | 1021 BUS_ERROR_BADMC | 1022 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1023 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB | 1024 BUS_ERROR_CIQTO | 1025 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO | 1026 BUS_ERROR_UFPQTO | BUS_ERROR_APERR | 1027 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT | 1028 BUS_ERROR_ILL); 1029 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1030 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); 1031 1032 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 1033 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 1034} 1035 1036static void pbm_config_busmastering(struct pci_pbm_info *pbm) 1037{ 1038 u8 *addr; 1039 1040 /* Set cache-line size to 64 bytes, this is actually 1041 * a nop but I do it for completeness. 1042 */ 1043 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1044 0, PCI_CACHE_LINE_SIZE); 1045 pci_config_write8(addr, 64 / sizeof(u32)); 1046 1047 /* Set PBM latency timer to 64 PCI clocks. */ 1048 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1049 0, PCI_LATENCY_TIMER); 1050 pci_config_write8(addr, 64); 1051} 1052 1053static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm, 1054 struct device *parent) 1055{ 1056 pbm_config_busmastering(pbm); 1057 pbm->is_66mhz_capable = 1058 (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL) 1059 != NULL); 1060 1061 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 1062 1063 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1064 tomatillo_register_error_handlers(pbm); 1065 else 1066 schizo_register_error_handlers(pbm); 1067} 1068 1069#define SCHIZO_STRBUF_CONTROL (0x02800UL) 1070#define SCHIZO_STRBUF_FLUSH (0x02808UL) 1071#define SCHIZO_STRBUF_FSYNC (0x02810UL) 1072#define SCHIZO_STRBUF_CTXFLUSH (0x02818UL) 1073#define SCHIZO_STRBUF_CTXMATCH (0x10000UL) 1074 1075static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) 1076{ 1077 unsigned long base = pbm->pbm_regs; 1078 u64 control; 1079 1080 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1081 /* TOMATILLO lacks streaming cache. */ 1082 return; 1083 } 1084 1085 /* SCHIZO has context flushing. */ 1086 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; 1087 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; 1088 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; 1089 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; 1090 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; 1091 1092 pbm->stc.strbuf_flushflag = (volatile unsigned long *) 1093 ((((unsigned long)&pbm->stc.__flushflag_buf[0]) 1094 + 63UL) 1095 & ~63UL); 1096 pbm->stc.strbuf_flushflag_pa = (unsigned long) 1097 __pa(pbm->stc.strbuf_flushflag); 1098 1099 /* Turn off LRU locking and diag mode, enable the 1100 * streaming buffer and leave the rerun-disable 1101 * setting however OBP set it. 1102 */ 1103 control = upa_readq(pbm->stc.strbuf_control); 1104 control &= ~(SCHIZO_STRBUF_CTRL_LPTR | 1105 SCHIZO_STRBUF_CTRL_LENAB | 1106 SCHIZO_STRBUF_CTRL_DENAB); 1107 control |= SCHIZO_STRBUF_CTRL_ENAB; 1108 upa_writeq(control, pbm->stc.strbuf_control); 1109 1110 pbm->stc.strbuf_enabled = 1; 1111} 1112 1113#define SCHIZO_IOMMU_CONTROL (0x00200UL) 1114#define SCHIZO_IOMMU_TSBBASE (0x00208UL) 1115#define SCHIZO_IOMMU_FLUSH (0x00210UL) 1116#define SCHIZO_IOMMU_CTXFLUSH (0x00218UL) 1117 1118static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm) 1119{ 1120 static const u32 vdma_default[] = { 0xc0000000, 0x40000000 }; 1121 unsigned long i, tagbase, database; 1122 struct iommu *iommu = pbm->iommu; 1123 int tsbsize, err; 1124 const u32 *vdma; 1125 u32 dma_mask; 1126 u64 control; 1127 1128 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); 1129 if (!vdma) 1130 vdma = vdma_default; 1131 1132 dma_mask = vdma[0]; 1133 switch (vdma[1]) { 1134 case 0x20000000: 1135 dma_mask |= 0x1fffffff; 1136 tsbsize = 64; 1137 break; 1138 1139 case 0x40000000: 1140 dma_mask |= 0x3fffffff; 1141 tsbsize = 128; 1142 break; 1143 1144 case 0x80000000: 1145 dma_mask |= 0x7fffffff; 1146 tsbsize = 128; 1147 break; 1148 1149 default: 1150 printk(KERN_ERR PFX "Strange virtual-dma size.\n"); 1151 return -EINVAL; 1152 } 1153 1154 /* Register addresses, SCHIZO has iommu ctx flushing. */ 1155 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; 1156 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; 1157 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; 1158 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL); 1159 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; 1160 1161 /* We use the main control/status register of SCHIZO as the write 1162 * completion register. 1163 */ 1164 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; 1165 1166 /* 1167 * Invalidate TLB Entries. 1168 */ 1169 control = upa_readq(iommu->iommu_control); 1170 control |= SCHIZO_IOMMU_CTRL_DENAB; 1171 upa_writeq(control, iommu->iommu_control); 1172 1173 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; 1174 1175 for (i = 0; i < 16; i++) { 1176 upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL)); 1177 upa_writeq(0, pbm->pbm_regs + database + (i * 8UL)); 1178 } 1179 1180 /* Leave diag mode enabled for full-flushing done 1181 * in pci_iommu.c 1182 */ 1183 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, 1184 pbm->numa_node); 1185 if (err) { 1186 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err); 1187 return err; 1188 } 1189 1190 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 1191 1192 control = upa_readq(iommu->iommu_control); 1193 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); 1194 switch (tsbsize) { 1195 case 64: 1196 control |= SCHIZO_IOMMU_TSBSZ_64K; 1197 break; 1198 case 128: 1199 control |= SCHIZO_IOMMU_TSBSZ_128K; 1200 break; 1201 } 1202 1203 control |= SCHIZO_IOMMU_CTRL_ENAB; 1204 upa_writeq(control, iommu->iommu_control); 1205 1206 return 0; 1207} 1208 1209#define SCHIZO_PCI_IRQ_RETRY (0x1a00UL) 1210#define SCHIZO_IRQ_RETRY_INF 0xffUL 1211 1212#define SCHIZO_PCI_DIAG (0x2020UL) 1213#define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */ 1214#define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */ 1215#define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */ 1216#define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */ 1217#define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */ 1218#define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */ 1219#define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */ 1220#define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */ 1221#define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */ 1222 1223#define TOMATILLO_PCI_IOC_CSR (0x2248UL) 1224#define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL 1225#define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL 1226#define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL 1227#define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL 1228#define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL 1229#define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL 1230#define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL 1231#define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL 1232#define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL 1233#define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL 1234#define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL 1235#define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL 1236#define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL 1237#define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL 1238#define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL 1239 1240#define TOMATILLO_PCI_IOC_TDIAG (0x2250UL) 1241#define TOMATILLO_PCI_IOC_DDIAG (0x2290UL) 1242 1243static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) 1244{ 1245 u64 tmp; 1246 1247 upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY); 1248 1249 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1250 1251 /* Enable arbiter for all PCI slots. */ 1252 tmp |= 0xff; 1253 1254 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1255 pbm->chip_version >= 0x2) 1256 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; 1257 1258 if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL)) 1259 tmp |= SCHIZO_PCICTRL_PARK; 1260 else 1261 tmp &= ~SCHIZO_PCICTRL_PARK; 1262 1263 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1264 pbm->chip_version <= 0x1) 1265 tmp |= SCHIZO_PCICTRL_DTO_INT; 1266 else 1267 tmp &= ~SCHIZO_PCICTRL_DTO_INT; 1268 1269 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1270 tmp |= (SCHIZO_PCICTRL_MRM_PREF | 1271 SCHIZO_PCICTRL_RDO_PREF | 1272 SCHIZO_PCICTRL_RDL_PREF); 1273 1274 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1275 1276 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG); 1277 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | 1278 SCHIZO_PCIDIAG_D_RETRY | 1279 SCHIZO_PCIDIAG_D_INTSYNC); 1280 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG); 1281 1282 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1283 tmp = (TOMATILLO_IOC_PART_WPENAB | 1284 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | 1285 TOMATILLO_IOC_RDMULT_CPENAB | 1286 TOMATILLO_IOC_RDONE_CPENAB | 1287 TOMATILLO_IOC_RDLINE_CPENAB); 1288 1289 upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR); 1290 } 1291} 1292 1293static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm, 1294 struct platform_device *op, u32 portid, 1295 int chip_type) 1296{ 1297 const struct linux_prom64_registers *regs; 1298 struct device_node *dp = op->dev.of_node; 1299 const char *chipset_name; 1300 int is_pbm_a, err; 1301 1302 switch (chip_type) { 1303 case PBM_CHIP_TYPE_TOMATILLO: 1304 chipset_name = "TOMATILLO"; 1305 break; 1306 1307 case PBM_CHIP_TYPE_SCHIZO_PLUS: 1308 chipset_name = "SCHIZO+"; 1309 break; 1310 1311 case PBM_CHIP_TYPE_SCHIZO: 1312 default: 1313 chipset_name = "SCHIZO"; 1314 break; 1315 }; 1316 1317 /* For SCHIZO, three OBP regs: 1318 * 1) PBM controller regs 1319 * 2) Schizo front-end controller regs (same for both PBMs) 1320 * 3) PBM PCI config space 1321 * 1322 * For TOMATILLO, four OBP regs: 1323 * 1) PBM controller regs 1324 * 2) Tomatillo front-end controller regs 1325 * 3) PBM PCI config space 1326 * 4) Ichip regs 1327 */ 1328 regs = of_get_property(dp, "reg", NULL); 1329 1330 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000); 1331 1332 pbm->next = pci_pbm_root; 1333 pci_pbm_root = pbm; 1334 1335 pbm->numa_node = -1; 1336 1337 pbm->pci_ops = &sun4u_pci_ops; 1338 pbm->config_space_reg_bits = 8; 1339 1340 pbm->index = pci_num_pbms++; 1341 1342 pbm->portid = portid; 1343 pbm->op = op; 1344 1345 pbm->chip_type = chip_type; 1346 pbm->chip_version = of_getintprop_default(dp, "version#", 0); 1347 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0); 1348 1349 pbm->pbm_regs = regs[0].phys_addr; 1350 pbm->controller_regs = regs[1].phys_addr - 0x10000UL; 1351 1352 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) 1353 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL; 1354 1355 pbm->name = dp->full_name; 1356 1357 printk("%s: %s PCI Bus Module ver[%x:%x]\n", 1358 pbm->name, chipset_name, 1359 pbm->chip_version, pbm->chip_revision); 1360 1361 schizo_pbm_hw_init(pbm); 1362 1363 pci_determine_mem_io_space(pbm); 1364 1365 pci_get_pbm_props(pbm); 1366 1367 err = schizo_pbm_iommu_init(pbm); 1368 if (err) 1369 return err; 1370 1371 schizo_pbm_strbuf_init(pbm); 1372 1373 schizo_scan_bus(pbm, &op->dev); 1374 1375 return 0; 1376} 1377 1378static inline int portid_compare(u32 x, u32 y, int chip_type) 1379{ 1380 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1381 if (x == (y ^ 1)) 1382 return 1; 1383 return 0; 1384 } 1385 return (x == y); 1386} 1387 1388static struct pci_pbm_info * __devinit schizo_find_sibling(u32 portid, 1389 int chip_type) 1390{ 1391 struct pci_pbm_info *pbm; 1392 1393 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 1394 if (portid_compare(pbm->portid, portid, chip_type)) 1395 return pbm; 1396 } 1397 return NULL; 1398} 1399 1400static int __devinit __schizo_init(struct platform_device *op, unsigned long chip_type) 1401{ 1402 struct device_node *dp = op->dev.of_node; 1403 struct pci_pbm_info *pbm; 1404 struct iommu *iommu; 1405 u32 portid; 1406 int err; 1407 1408 portid = of_getintprop_default(dp, "portid", 0xff); 1409 1410 err = -ENOMEM; 1411 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 1412 if (!pbm) { 1413 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); 1414 goto out_err; 1415 } 1416 1417 pbm->sibling = schizo_find_sibling(portid, chip_type); 1418 1419 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); 1420 if (!iommu) { 1421 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n"); 1422 goto out_free_pbm; 1423 } 1424 1425 pbm->iommu = iommu; 1426 1427 if (schizo_pbm_init(pbm, op, portid, chip_type)) 1428 goto out_free_iommu; 1429 1430 if (pbm->sibling) 1431 pbm->sibling->sibling = pbm; 1432 1433 dev_set_drvdata(&op->dev, pbm); 1434 1435 return 0; 1436 1437out_free_iommu: 1438 kfree(pbm->iommu); 1439 1440out_free_pbm: 1441 kfree(pbm); 1442 1443out_err: 1444 return err; 1445} 1446 1447static int __devinit schizo_probe(struct platform_device *op, 1448 const struct of_device_id *match) 1449{ 1450 return __schizo_init(op, (unsigned long) match->data); 1451} 1452 1453/* The ordering of this table is very important. Some Tomatillo 1454 * nodes announce that they are compatible with both pci108e,a801 1455 * and pci108e,8001. So list the chips in reverse chronological 1456 * order. 1457 */ 1458static struct of_device_id __initdata schizo_match[] = { 1459 { 1460 .name = "pci", 1461 .compatible = "pci108e,a801", 1462 .data = (void *) PBM_CHIP_TYPE_TOMATILLO, 1463 }, 1464 { 1465 .name = "pci", 1466 .compatible = "pci108e,8002", 1467 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS, 1468 }, 1469 { 1470 .name = "pci", 1471 .compatible = "pci108e,8001", 1472 .data = (void *) PBM_CHIP_TYPE_SCHIZO, 1473 }, 1474 {}, 1475}; 1476 1477static struct of_platform_driver schizo_driver = { 1478 .driver = { 1479 .name = DRIVER_NAME, 1480 .owner = THIS_MODULE, 1481 .of_match_table = schizo_match, 1482 }, 1483 .probe = schizo_probe, 1484}; 1485 1486static int __init schizo_init(void) 1487{ 1488 return of_register_platform_driver(&schizo_driver); 1489} 1490 1491subsys_initcall(schizo_init); 1492