1/* 2 * SH7366 Setup 3 * 4 * Copyright (C) 2008 Renesas Solutions 5 * 6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12#include <linux/platform_device.h> 13#include <linux/init.h> 14#include <linux/serial.h> 15#include <linux/serial_sci.h> 16#include <linux/uio_driver.h> 17#include <linux/sh_timer.h> 18#include <linux/usb/r8a66597.h> 19#include <asm/clock.h> 20 21static struct plat_sci_port scif0_platform_data = { 22 .mapbase = 0xffe00000, 23 .flags = UPF_BOOT_AUTOCONF, 24 .type = PORT_SCIF, 25 .irqs = { 80, 80, 80, 80 }, 26}; 27 28static struct platform_device scif0_device = { 29 .name = "sh-sci", 30 .id = 0, 31 .dev = { 32 .platform_data = &scif0_platform_data, 33 }, 34}; 35 36static struct resource iic_resources[] = { 37 [0] = { 38 .name = "IIC", 39 .start = 0x04470000, 40 .end = 0x04470017, 41 .flags = IORESOURCE_MEM, 42 }, 43 [1] = { 44 .start = 96, 45 .end = 99, 46 .flags = IORESOURCE_IRQ, 47 }, 48}; 49 50static struct platform_device iic_device = { 51 .name = "i2c-sh_mobile", 52 .id = 0, /* "i2c0" clock */ 53 .num_resources = ARRAY_SIZE(iic_resources), 54 .resource = iic_resources, 55}; 56 57static struct r8a66597_platdata r8a66597_data = { 58 .on_chip = 1, 59}; 60 61static struct resource usb_host_resources[] = { 62 [0] = { 63 .start = 0xa4d80000, 64 .end = 0xa4d800ff, 65 .flags = IORESOURCE_MEM, 66 }, 67 [1] = { 68 .start = 65, 69 .end = 65, 70 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 71 }, 72}; 73 74static struct platform_device usb_host_device = { 75 .name = "r8a66597_hcd", 76 .id = -1, 77 .dev = { 78 .dma_mask = NULL, 79 .coherent_dma_mask = 0xffffffff, 80 .platform_data = &r8a66597_data, 81 }, 82 .num_resources = ARRAY_SIZE(usb_host_resources), 83 .resource = usb_host_resources, 84}; 85 86static struct uio_info vpu_platform_data = { 87 .name = "VPU5", 88 .version = "0", 89 .irq = 60, 90}; 91 92static struct resource vpu_resources[] = { 93 [0] = { 94 .name = "VPU", 95 .start = 0xfe900000, 96 .end = 0xfe902807, 97 .flags = IORESOURCE_MEM, 98 }, 99 [1] = { 100 /* place holder for contiguous memory */ 101 }, 102}; 103 104static struct platform_device vpu_device = { 105 .name = "uio_pdrv_genirq", 106 .id = 0, 107 .dev = { 108 .platform_data = &vpu_platform_data, 109 }, 110 .resource = vpu_resources, 111 .num_resources = ARRAY_SIZE(vpu_resources), 112}; 113 114static struct uio_info veu0_platform_data = { 115 .name = "VEU", 116 .version = "0", 117 .irq = 54, 118}; 119 120static struct resource veu0_resources[] = { 121 [0] = { 122 .name = "VEU(1)", 123 .start = 0xfe920000, 124 .end = 0xfe9200b7, 125 .flags = IORESOURCE_MEM, 126 }, 127 [1] = { 128 /* place holder for contiguous memory */ 129 }, 130}; 131 132static struct platform_device veu0_device = { 133 .name = "uio_pdrv_genirq", 134 .id = 1, 135 .dev = { 136 .platform_data = &veu0_platform_data, 137 }, 138 .resource = veu0_resources, 139 .num_resources = ARRAY_SIZE(veu0_resources), 140}; 141 142static struct uio_info veu1_platform_data = { 143 .name = "VEU", 144 .version = "0", 145 .irq = 27, 146}; 147 148static struct resource veu1_resources[] = { 149 [0] = { 150 .name = "VEU(2)", 151 .start = 0xfe924000, 152 .end = 0xfe9240b7, 153 .flags = IORESOURCE_MEM, 154 }, 155 [1] = { 156 /* place holder for contiguous memory */ 157 }, 158}; 159 160static struct platform_device veu1_device = { 161 .name = "uio_pdrv_genirq", 162 .id = 2, 163 .dev = { 164 .platform_data = &veu1_platform_data, 165 }, 166 .resource = veu1_resources, 167 .num_resources = ARRAY_SIZE(veu1_resources), 168}; 169 170static struct sh_timer_config cmt_platform_data = { 171 .channel_offset = 0x60, 172 .timer_bit = 5, 173 .clockevent_rating = 125, 174 .clocksource_rating = 200, 175}; 176 177static struct resource cmt_resources[] = { 178 [0] = { 179 .start = 0x044a0060, 180 .end = 0x044a006b, 181 .flags = IORESOURCE_MEM, 182 }, 183 [1] = { 184 .start = 104, 185 .flags = IORESOURCE_IRQ, 186 }, 187}; 188 189static struct platform_device cmt_device = { 190 .name = "sh_cmt", 191 .id = 0, 192 .dev = { 193 .platform_data = &cmt_platform_data, 194 }, 195 .resource = cmt_resources, 196 .num_resources = ARRAY_SIZE(cmt_resources), 197}; 198 199static struct sh_timer_config tmu0_platform_data = { 200 .channel_offset = 0x04, 201 .timer_bit = 0, 202 .clockevent_rating = 200, 203}; 204 205static struct resource tmu0_resources[] = { 206 [0] = { 207 .start = 0xffd80008, 208 .end = 0xffd80013, 209 .flags = IORESOURCE_MEM, 210 }, 211 [1] = { 212 .start = 16, 213 .flags = IORESOURCE_IRQ, 214 }, 215}; 216 217static struct platform_device tmu0_device = { 218 .name = "sh_tmu", 219 .id = 0, 220 .dev = { 221 .platform_data = &tmu0_platform_data, 222 }, 223 .resource = tmu0_resources, 224 .num_resources = ARRAY_SIZE(tmu0_resources), 225}; 226 227static struct sh_timer_config tmu1_platform_data = { 228 .channel_offset = 0x10, 229 .timer_bit = 1, 230 .clocksource_rating = 200, 231}; 232 233static struct resource tmu1_resources[] = { 234 [0] = { 235 .start = 0xffd80014, 236 .end = 0xffd8001f, 237 .flags = IORESOURCE_MEM, 238 }, 239 [1] = { 240 .start = 17, 241 .flags = IORESOURCE_IRQ, 242 }, 243}; 244 245static struct platform_device tmu1_device = { 246 .name = "sh_tmu", 247 .id = 1, 248 .dev = { 249 .platform_data = &tmu1_platform_data, 250 }, 251 .resource = tmu1_resources, 252 .num_resources = ARRAY_SIZE(tmu1_resources), 253}; 254 255static struct sh_timer_config tmu2_platform_data = { 256 .channel_offset = 0x1c, 257 .timer_bit = 2, 258}; 259 260static struct resource tmu2_resources[] = { 261 [0] = { 262 .start = 0xffd80020, 263 .end = 0xffd8002b, 264 .flags = IORESOURCE_MEM, 265 }, 266 [1] = { 267 .start = 18, 268 .flags = IORESOURCE_IRQ, 269 }, 270}; 271 272static struct platform_device tmu2_device = { 273 .name = "sh_tmu", 274 .id = 2, 275 .dev = { 276 .platform_data = &tmu2_platform_data, 277 }, 278 .resource = tmu2_resources, 279 .num_resources = ARRAY_SIZE(tmu2_resources), 280}; 281 282static struct platform_device *sh7366_devices[] __initdata = { 283 &scif0_device, 284 &cmt_device, 285 &tmu0_device, 286 &tmu1_device, 287 &tmu2_device, 288 &iic_device, 289 &usb_host_device, 290 &vpu_device, 291 &veu0_device, 292 &veu1_device, 293}; 294 295static int __init sh7366_devices_setup(void) 296{ 297 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 298 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 299 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 300 301 return platform_add_devices(sh7366_devices, 302 ARRAY_SIZE(sh7366_devices)); 303} 304arch_initcall(sh7366_devices_setup); 305 306static struct platform_device *sh7366_early_devices[] __initdata = { 307 &scif0_device, 308 &cmt_device, 309 &tmu0_device, 310 &tmu1_device, 311 &tmu2_device, 312}; 313 314void __init plat_early_device_setup(void) 315{ 316 early_platform_add_devices(sh7366_early_devices, 317 ARRAY_SIZE(sh7366_early_devices)); 318} 319 320enum { 321 UNUSED=0, 322 323 /* interrupt sources */ 324 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 325 ICB, 326 DMAC0, DMAC1, DMAC2, DMAC3, 327 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 328 MFI, VPU, USB, 329 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I, 330 DMAC4, DMAC5, DMAC_DADERR, 331 SCIF, SCIFA1, SCIFA2, 332 DENC, MSIOF, 333 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 334 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 335 SDHI0, SDHI1, SDHI2, SDHI3, 336 CMT, TSIF, SIU, 337 TMU0, TMU1, TMU2, 338 VEU2, LCDC, 339 340 /* interrupt groups */ 341 342 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI, 343}; 344 345static struct intc_vect vectors[] __initdata = { 346 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 347 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 348 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 349 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 350 INTC_VECT(ICB, 0x700), 351 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 352 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 353 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 354 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 355 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20), 356 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20), 357 INTC_VECT(MMC_MMC3I, 0xb40), 358 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 359 INTC_VECT(DMAC_DADERR, 0xbc0), 360 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20), 361 INTC_VECT(SCIFA2, 0xc40), 362 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80), 363 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 364 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 365 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 366 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 367 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 368 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 369 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 370 INTC_VECT(SIU, 0xf80), 371 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 372 INTC_VECT(TMU2, 0x440), 373 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580), 374}; 375 376static struct intc_group groups[] __initdata = { 377 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 378 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 379 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I), 380 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 381 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 382 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 383 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 384 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 385}; 386 387static struct intc_mask_reg mask_registers[] __initdata = { 388 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 389 { } }, 390 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 391 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 392 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 393 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 394 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 395 { 0, 0, 0, ICB } }, 396 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 397 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } }, 398 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 399 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } }, 400 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 401 { 0, 0, 0, 0, 0, 0, 0, MSIOF } }, 402 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 403 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 404 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 405 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 406 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 407 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 408 { 0, 0, 0, CMT, 0, USB, } }, 409 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 410 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } }, 411 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 412 { 0, 0, 0, 0, 0, 0, 0, TSIF } }, 413 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 414 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 415}; 416 417static struct intc_prio_reg prio_registers[] __initdata = { 418 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 419 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } }, 420 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 421 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 422 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 423 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } }, 424 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } }, 425 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } }, 426 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } }, 427 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 428 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 429 { 0xa408002c, 0, 16, 4, /* IPRL */ { } }, 430 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 431 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 432}; 433 434static struct intc_sense_reg sense_registers[] __initdata = { 435 { 0xa414001c, 16, 2, /* ICR1 */ 436 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 437}; 438 439static struct intc_mask_reg ack_registers[] __initdata = { 440 { 0xa4140024, 0, 8, /* INTREQ00 */ 441 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 442}; 443 444static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups, 445 mask_registers, prio_registers, sense_registers, 446 ack_registers); 447 448void __init plat_irq_setup(void) 449{ 450 register_intc_controller(&intc_desc); 451} 452 453void __init plat_mem_setup(void) 454{ 455 /* TODO: Register Node 1 */ 456} 457