1/* 2 * SH7750/SH7751 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11#include <linux/platform_device.h> 12#include <linux/init.h> 13#include <linux/serial.h> 14#include <linux/io.h> 15#include <linux/sh_timer.h> 16#include <linux/serial_sci.h> 17 18static struct resource rtc_resources[] = { 19 [0] = { 20 .start = 0xffc80000, 21 .end = 0xffc80000 + 0x58 - 1, 22 .flags = IORESOURCE_IO, 23 }, 24 [1] = { 25 /* Shared Period/Carry/Alarm IRQ */ 26 .start = 20, 27 .flags = IORESOURCE_IRQ, 28 }, 29}; 30 31static struct platform_device rtc_device = { 32 .name = "sh-rtc", 33 .id = -1, 34 .num_resources = ARRAY_SIZE(rtc_resources), 35 .resource = rtc_resources, 36}; 37 38static struct plat_sci_port scif0_platform_data = { 39 .mapbase = 0xffe00000, 40 .flags = UPF_BOOT_AUTOCONF, 41 .type = PORT_SCI, 42 .irqs = { 23, 23, 23, 0 }, 43}; 44 45static struct platform_device scif0_device = { 46 .name = "sh-sci", 47 .id = 0, 48 .dev = { 49 .platform_data = &scif0_platform_data, 50 }, 51}; 52 53static struct plat_sci_port scif1_platform_data = { 54 .mapbase = 0xffe80000, 55 .flags = UPF_BOOT_AUTOCONF, 56 .type = PORT_SCIF, 57 .irqs = { 40, 40, 40, 40 }, 58}; 59 60static struct platform_device scif1_device = { 61 .name = "sh-sci", 62 .id = 1, 63 .dev = { 64 .platform_data = &scif1_platform_data, 65 }, 66}; 67 68static struct sh_timer_config tmu0_platform_data = { 69 .channel_offset = 0x04, 70 .timer_bit = 0, 71 .clockevent_rating = 200, 72}; 73 74static struct resource tmu0_resources[] = { 75 [0] = { 76 .start = 0xffd80008, 77 .end = 0xffd80013, 78 .flags = IORESOURCE_MEM, 79 }, 80 [1] = { 81 .start = 16, 82 .flags = IORESOURCE_IRQ, 83 }, 84}; 85 86static struct platform_device tmu0_device = { 87 .name = "sh_tmu", 88 .id = 0, 89 .dev = { 90 .platform_data = &tmu0_platform_data, 91 }, 92 .resource = tmu0_resources, 93 .num_resources = ARRAY_SIZE(tmu0_resources), 94}; 95 96static struct sh_timer_config tmu1_platform_data = { 97 .channel_offset = 0x10, 98 .timer_bit = 1, 99 .clocksource_rating = 200, 100}; 101 102static struct resource tmu1_resources[] = { 103 [0] = { 104 .start = 0xffd80014, 105 .end = 0xffd8001f, 106 .flags = IORESOURCE_MEM, 107 }, 108 [1] = { 109 .start = 17, 110 .flags = IORESOURCE_IRQ, 111 }, 112}; 113 114static struct platform_device tmu1_device = { 115 .name = "sh_tmu", 116 .id = 1, 117 .dev = { 118 .platform_data = &tmu1_platform_data, 119 }, 120 .resource = tmu1_resources, 121 .num_resources = ARRAY_SIZE(tmu1_resources), 122}; 123 124static struct sh_timer_config tmu2_platform_data = { 125 .channel_offset = 0x1c, 126 .timer_bit = 2, 127}; 128 129static struct resource tmu2_resources[] = { 130 [0] = { 131 .start = 0xffd80020, 132 .end = 0xffd8002f, 133 .flags = IORESOURCE_MEM, 134 }, 135 [1] = { 136 .start = 18, 137 .flags = IORESOURCE_IRQ, 138 }, 139}; 140 141static struct platform_device tmu2_device = { 142 .name = "sh_tmu", 143 .id = 2, 144 .dev = { 145 .platform_data = &tmu2_platform_data, 146 }, 147 .resource = tmu2_resources, 148 .num_resources = ARRAY_SIZE(tmu2_resources), 149}; 150 151/* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 152#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 153 defined(CONFIG_CPU_SUBTYPE_SH7751R) 154 155static struct sh_timer_config tmu3_platform_data = { 156 .channel_offset = 0x04, 157 .timer_bit = 0, 158}; 159 160static struct resource tmu3_resources[] = { 161 [0] = { 162 .start = 0xfe100008, 163 .end = 0xfe100013, 164 .flags = IORESOURCE_MEM, 165 }, 166 [1] = { 167 .start = 72, 168 .flags = IORESOURCE_IRQ, 169 }, 170}; 171 172static struct platform_device tmu3_device = { 173 .name = "sh_tmu", 174 .id = 3, 175 .dev = { 176 .platform_data = &tmu3_platform_data, 177 }, 178 .resource = tmu3_resources, 179 .num_resources = ARRAY_SIZE(tmu3_resources), 180}; 181 182static struct sh_timer_config tmu4_platform_data = { 183 .channel_offset = 0x10, 184 .timer_bit = 1, 185}; 186 187static struct resource tmu4_resources[] = { 188 [0] = { 189 .start = 0xfe100014, 190 .end = 0xfe10001f, 191 .flags = IORESOURCE_MEM, 192 }, 193 [1] = { 194 .start = 76, 195 .flags = IORESOURCE_IRQ, 196 }, 197}; 198 199static struct platform_device tmu4_device = { 200 .name = "sh_tmu", 201 .id = 4, 202 .dev = { 203 .platform_data = &tmu4_platform_data, 204 }, 205 .resource = tmu4_resources, 206 .num_resources = ARRAY_SIZE(tmu4_resources), 207}; 208 209#endif 210 211static struct platform_device *sh7750_devices[] __initdata = { 212 &scif0_device, 213 &scif1_device, 214 &rtc_device, 215 &tmu0_device, 216 &tmu1_device, 217 &tmu2_device, 218#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 219 defined(CONFIG_CPU_SUBTYPE_SH7751R) 220 &tmu3_device, 221 &tmu4_device, 222#endif 223}; 224 225static int __init sh7750_devices_setup(void) 226{ 227 return platform_add_devices(sh7750_devices, 228 ARRAY_SIZE(sh7750_devices)); 229} 230arch_initcall(sh7750_devices_setup); 231 232static struct platform_device *sh7750_early_devices[] __initdata = { 233 &scif0_device, 234 &scif1_device, 235 &tmu0_device, 236 &tmu1_device, 237 &tmu2_device, 238#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 239 defined(CONFIG_CPU_SUBTYPE_SH7751R) 240 &tmu3_device, 241 &tmu4_device, 242#endif 243}; 244 245void __init plat_early_device_setup(void) 246{ 247 early_platform_add_devices(sh7750_early_devices, 248 ARRAY_SIZE(sh7750_early_devices)); 249} 250 251enum { 252 UNUSED = 0, 253 254 /* interrupt sources */ 255 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 256 HUDI, GPIOI, DMAC, 257 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 258 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 259 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, 260 261 /* interrupt groups */ 262 PCIC1, 263}; 264 265static struct intc_vect vectors[] __initdata = { 266 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 267 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 268 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 269 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 270 INTC_VECT(RTC, 0x4c0), 271 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500), 272 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540), 273 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 274 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 275 INTC_VECT(WDT, 0x560), 276 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 277}; 278 279static struct intc_prio_reg prio_registers[] __initdata = { 280 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 281 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 282 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 283 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 284 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, 285 TMU4, TMU3, 286 PCIC1, PCIC0_PCISERR } }, 287}; 288 289static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL, 290 NULL, prio_registers, NULL); 291 292/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 293#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 294 defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7091) 295static struct intc_vect vectors_dma4[] __initdata = { 296 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 297 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 298 INTC_VECT(DMAC, 0x6c0), 299}; 300 301static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 302 vectors_dma4, NULL, 303 NULL, prio_registers, NULL); 304#endif 305 306/* SH7750R and SH7751R both have 8-channel DMA controllers */ 307#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 308static struct intc_vect vectors_dma8[] __initdata = { 309 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 310 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 311 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 312 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 313 INTC_VECT(DMAC, 0x6c0), 314}; 315 316static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 317 vectors_dma8, NULL, 318 NULL, prio_registers, NULL); 319#endif 320 321/* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 322#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 323 defined(CONFIG_CPU_SUBTYPE_SH7751R) 324static struct intc_vect vectors_tmu34[] __initdata = { 325 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 326}; 327 328static struct intc_mask_reg mask_registers[] __initdata = { 329 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 330 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 331 0, 0, 0, 0, 0, 0, TMU4, TMU3, 332 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 333 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 334 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 335}; 336 337static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", 338 vectors_tmu34, NULL, 339 mask_registers, prio_registers, NULL); 340#endif 341 342/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 343static struct intc_vect vectors_irlm[] __initdata = { 344 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 345 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 346}; 347 348static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, 349 NULL, prio_registers, NULL); 350 351/* SH7751 and SH7751R both have PCI */ 352#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 353static struct intc_vect vectors_pci[] __initdata = { 354 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 355 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 356 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 357 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 358}; 359 360static struct intc_group groups_pci[] __initdata = { 361 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 362 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 363}; 364 365static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, 366 mask_registers, prio_registers, NULL); 367#endif 368 369#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 370 defined(CONFIG_CPU_SUBTYPE_SH7091) 371void __init plat_irq_setup(void) 372{ 373 /* 374 * same vectors for SH7750, SH7750S and SH7091 except for IRLM, 375 * see below.. 376 */ 377 register_intc_controller(&intc_desc); 378 register_intc_controller(&intc_desc_dma4); 379} 380#endif 381 382#if defined(CONFIG_CPU_SUBTYPE_SH7750R) 383void __init plat_irq_setup(void) 384{ 385 register_intc_controller(&intc_desc); 386 register_intc_controller(&intc_desc_dma8); 387 register_intc_controller(&intc_desc_tmu34); 388} 389#endif 390 391#if defined(CONFIG_CPU_SUBTYPE_SH7751) 392void __init plat_irq_setup(void) 393{ 394 register_intc_controller(&intc_desc); 395 register_intc_controller(&intc_desc_dma4); 396 register_intc_controller(&intc_desc_tmu34); 397 register_intc_controller(&intc_desc_pci); 398} 399#endif 400 401#if defined(CONFIG_CPU_SUBTYPE_SH7751R) 402void __init plat_irq_setup(void) 403{ 404 register_intc_controller(&intc_desc); 405 register_intc_controller(&intc_desc_dma8); 406 register_intc_controller(&intc_desc_tmu34); 407 register_intc_controller(&intc_desc_pci); 408} 409#endif 410 411#define INTC_ICR 0xffd00000UL 412#define INTC_ICR_IRLM (1<<7) 413 414void __init plat_irq_setup_pins(int mode) 415{ 416#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 417 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 418 return; 419#endif 420 421 switch (mode) { 422 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 423 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 424 register_intc_controller(&intc_desc_irlm); 425 break; 426 default: 427 BUG(); 428 } 429} 430