1/* 2 * SH7619 Setup 3 * 4 * Copyright (C) 2006 Yoshinori Sato 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11#include <linux/platform_device.h> 12#include <linux/init.h> 13#include <linux/serial.h> 14#include <linux/serial_sci.h> 15#include <linux/sh_timer.h> 16#include <linux/io.h> 17 18enum { 19 UNUSED = 0, 20 21 /* interrupt sources */ 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 23 WDT, EDMAC, CMT0, CMT1, 24 SCIF0, SCIF1, SCIF2, 25 HIF_HIFI, HIF_HIFBI, 26 DMAC0, DMAC1, DMAC2, DMAC3, 27 SIOF, 28}; 29 30static struct intc_vect vectors[] __initdata = { 31 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 32 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 33 INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81), 34 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83), 35 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85), 36 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87), 37 INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89), 38 INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91), 39 INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93), 40 INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95), 41 INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97), 42 INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99), 43 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101), 44 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105), 45 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107), 46 INTC_IRQ(SIOF, 108), 47}; 48 49static struct intc_prio_reg prio_registers[] __initdata = { 50 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 51 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 52 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } }, 53 { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } }, 54 { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } }, 55 { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, 56 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } }, 57}; 58 59static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL, 60 NULL, prio_registers, NULL); 61 62static struct plat_sci_port scif0_platform_data = { 63 .mapbase = 0xf8400000, 64 .flags = UPF_BOOT_AUTOCONF, 65 .type = PORT_SCIF, 66 .irqs = { 88, 88, 88, 88 }, 67}; 68 69static struct platform_device scif0_device = { 70 .name = "sh-sci", 71 .id = 0, 72 .dev = { 73 .platform_data = &scif0_platform_data, 74 }, 75}; 76 77static struct plat_sci_port scif1_platform_data = { 78 .mapbase = 0xf8410000, 79 .flags = UPF_BOOT_AUTOCONF, 80 .type = PORT_SCIF, 81 .irqs = { 92, 92, 92, 92 }, 82}; 83 84static struct platform_device scif1_device = { 85 .name = "sh-sci", 86 .id = 1, 87 .dev = { 88 .platform_data = &scif1_platform_data, 89 }, 90}; 91 92static struct plat_sci_port scif2_platform_data = { 93 .mapbase = 0xf8420000, 94 .flags = UPF_BOOT_AUTOCONF, 95 .type = PORT_SCIF, 96 .irqs = { 96, 96, 96, 96 }, 97}; 98 99static struct platform_device scif2_device = { 100 .name = "sh-sci", 101 .id = 2, 102 .dev = { 103 .platform_data = &scif2_platform_data, 104 }, 105}; 106 107static struct resource eth_resources[] = { 108 [0] = { 109 .start = 0xfb000000, 110 .end = 0xfb0001c8, 111 .flags = IORESOURCE_MEM, 112 }, 113 [1] = { 114 .start = 85, 115 .end = 85, 116 .flags = IORESOURCE_IRQ, 117 }, 118}; 119 120static struct platform_device eth_device = { 121 .name = "sh-eth", 122 .id = -1, 123 .dev = { 124 .platform_data = (void *)1, 125 }, 126 .num_resources = ARRAY_SIZE(eth_resources), 127 .resource = eth_resources, 128}; 129 130static struct sh_timer_config cmt0_platform_data = { 131 .channel_offset = 0x02, 132 .timer_bit = 0, 133 .clockevent_rating = 125, 134 .clocksource_rating = 0, /* disabled due to code generation issues */ 135}; 136 137static struct resource cmt0_resources[] = { 138 [0] = { 139 .start = 0xf84a0072, 140 .end = 0xf84a0077, 141 .flags = IORESOURCE_MEM, 142 }, 143 [1] = { 144 .start = 86, 145 .flags = IORESOURCE_IRQ, 146 }, 147}; 148 149static struct platform_device cmt0_device = { 150 .name = "sh_cmt", 151 .id = 0, 152 .dev = { 153 .platform_data = &cmt0_platform_data, 154 }, 155 .resource = cmt0_resources, 156 .num_resources = ARRAY_SIZE(cmt0_resources), 157}; 158 159static struct sh_timer_config cmt1_platform_data = { 160 .channel_offset = 0x08, 161 .timer_bit = 1, 162 .clockevent_rating = 125, 163 .clocksource_rating = 0, /* disabled due to code generation issues */ 164}; 165 166static struct resource cmt1_resources[] = { 167 [0] = { 168 .start = 0xf84a0078, 169 .end = 0xf84a007d, 170 .flags = IORESOURCE_MEM, 171 }, 172 [1] = { 173 .start = 87, 174 .flags = IORESOURCE_IRQ, 175 }, 176}; 177 178static struct platform_device cmt1_device = { 179 .name = "sh_cmt", 180 .id = 1, 181 .dev = { 182 .platform_data = &cmt1_platform_data, 183 }, 184 .resource = cmt1_resources, 185 .num_resources = ARRAY_SIZE(cmt1_resources), 186}; 187 188static struct platform_device *sh7619_devices[] __initdata = { 189 &scif0_device, 190 &scif1_device, 191 &scif2_device, 192 ð_device, 193 &cmt0_device, 194 &cmt1_device, 195}; 196 197static int __init sh7619_devices_setup(void) 198{ 199 return platform_add_devices(sh7619_devices, 200 ARRAY_SIZE(sh7619_devices)); 201} 202arch_initcall(sh7619_devices_setup); 203 204void __init plat_irq_setup(void) 205{ 206 register_intc_controller(&intc_desc); 207} 208 209static struct platform_device *sh7619_early_devices[] __initdata = { 210 &scif0_device, 211 &scif1_device, 212 &scif2_device, 213 &cmt0_device, 214 &cmt1_device, 215}; 216 217#define STBCR3 0xf80a0000 218 219void __init plat_early_device_setup(void) 220{ 221 /* enable CMT clock */ 222 __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3); 223 224 early_platform_add_devices(sh7619_early_devices, 225 ARRAY_SIZE(sh7619_early_devices)); 226} 227