1/* 2 * arch/sh/kernel/cpu/irq/imask.c 3 * 4 * Copyright (C) 1999, 2000 Niibe Yutaka 5 * 6 * Simple interrupt handling using IMASK of SR register. 7 * 8 */ 9/* NOTE: Will not work on level 15 */ 10#include <linux/ptrace.h> 11#include <linux/errno.h> 12#include <linux/kernel_stat.h> 13#include <linux/signal.h> 14#include <linux/sched.h> 15#include <linux/interrupt.h> 16#include <linux/init.h> 17#include <linux/bitops.h> 18#include <linux/spinlock.h> 19#include <linux/cache.h> 20#include <linux/irq.h> 21#include <linux/bitmap.h> 22#include <asm/system.h> 23#include <asm/irq.h> 24 25/* Bitmap of IRQ masked */ 26#define IMASK_PRIORITY 15 27 28static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY); 29static int interrupt_priority; 30 31static inline void set_interrupt_registers(int ip) 32{ 33 unsigned long __dummy; 34 35 asm volatile( 36#ifdef CONFIG_CPU_HAS_SR_RB 37 "ldc %2, r6_bank\n\t" 38#endif 39 "stc sr, %0\n\t" 40 "and #0xf0, %0\n\t" 41 "shlr2 %0\n\t" 42 "cmp/eq #0x3c, %0\n\t" 43 "bt/s 1f ! CLI-ed\n\t" 44 " stc sr, %0\n\t" 45 "and %1, %0\n\t" 46 "or %2, %0\n\t" 47 "ldc %0, sr\n" 48 "1:" 49 : "=&z" (__dummy) 50 : "r" (~0xf0), "r" (ip << 4) 51 : "t"); 52} 53 54static void mask_imask_irq(unsigned int irq) 55{ 56 clear_bit(irq, imask_mask); 57 if (interrupt_priority < IMASK_PRIORITY - irq) 58 interrupt_priority = IMASK_PRIORITY - irq; 59 set_interrupt_registers(interrupt_priority); 60} 61 62static void unmask_imask_irq(unsigned int irq) 63{ 64 set_bit(irq, imask_mask); 65 interrupt_priority = IMASK_PRIORITY - 66 find_first_zero_bit(imask_mask, IMASK_PRIORITY); 67 set_interrupt_registers(interrupt_priority); 68} 69 70static struct irq_chip imask_irq_chip = { 71 .name = "SR.IMASK", 72 .mask = mask_imask_irq, 73 .unmask = unmask_imask_irq, 74 .mask_ack = mask_imask_irq, 75}; 76 77void make_imask_irq(unsigned int irq) 78{ 79 set_irq_chip_and_handler_name(irq, &imask_irq_chip, 80 handle_level_irq, "level"); 81} 82