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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/mach-dreamcast/mach/
1/* include/asm-sh/dreamcast/sysasic.h
2 *
3 * Definitions for the Dreamcast System ASIC and related peripherals.
4 *
5 * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
6 * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
7 *
8 * This file is part of the LinuxDC project (www.linuxdc.org)
9 *
10 * Released under the terms of the GNU GPL v2.0.
11 *
12 */
13#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
14#define __ASM_SH_DREAMCAST_SYSASIC_H
15
16#include <asm/irq.h>
17
18/* Hardware events -
19
20   Each of these events correspond to a bit within the Event Mask Registers/
21   Event Status Registers.  Because of the virtual IRQ numbering scheme, a
22   base offset must be used when calculating the virtual IRQ that each event
23   takes.
24*/
25
26#define HW_EVENT_IRQ_BASE  48
27
28/* IRQ 13 */
29#define HW_EVENT_VSYNC     (HW_EVENT_IRQ_BASE +  5) /* VSync */
30#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
31#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
32#define HW_EVENT_G2_DMA    (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
33#define HW_EVENT_PVR2_DMA  (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
34
35/* IRQ 11 */
36#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
37#define HW_EVENT_AICA_SYS  (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
38#define HW_EVENT_EXTERNAL  (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
39
40#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
41
42/* arch/sh/boards/mach-dreamcast/irq.c */
43extern int systemasic_irq_demux(int);
44extern void systemasic_irq_init(void);
45extern void aica_time_init(void);
46
47#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */
48