1/* 2 * SH3 CPU-specific DMA definitions, used by both DMA drivers 3 * 4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10#ifndef CPU_DMA_REGISTER_H 11#define CPU_DMA_REGISTER_H 12 13#define CHCR_TS_LOW_MASK 0x18 14#define CHCR_TS_LOW_SHIFT 3 15#define CHCR_TS_HIGH_MASK 0 16#define CHCR_TS_HIGH_SHIFT 0 17 18#define DMAOR_INIT DMAOR_DME 19 20/* 21 * The SuperH DMAC supports a number of transmit sizes, we list them here, 22 * with their respective values as they appear in the CHCR registers. 23 */ 24enum { 25 XMIT_SZ_8BIT, 26 XMIT_SZ_16BIT, 27 XMIT_SZ_32BIT, 28 XMIT_SZ_128BIT, 29}; 30 31/* log2(size / 8) - used to calculate number of transfers */ 32#define TS_SHIFT { \ 33 [XMIT_SZ_8BIT] = 0, \ 34 [XMIT_SZ_16BIT] = 1, \ 35 [XMIT_SZ_32BIT] = 2, \ 36 [XMIT_SZ_128BIT] = 4, \ 37} 38 39#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) 40 41#endif 42