1/* 2 * Renesas - AP-325RXA 3 * (Compatible with Algo System ., LTD. - AP-320A) 4 * 5 * Copyright (C) 2008 Renesas Solutions Corp. 6 * Author : Yusuke Goda <goda.yuske@renesas.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13#include <linux/init.h> 14#include <linux/device.h> 15#include <linux/interrupt.h> 16#include <linux/platform_device.h> 17#include <linux/mtd/physmap.h> 18#include <linux/mtd/sh_flctl.h> 19#include <linux/delay.h> 20#include <linux/i2c.h> 21#include <linux/smsc911x.h> 22#include <linux/gpio.h> 23#include <media/ov772x.h> 24#include <media/soc_camera.h> 25#include <media/soc_camera_platform.h> 26#include <media/sh_mobile_ceu.h> 27#include <video/sh_mobile_lcdc.h> 28#include <asm/io.h> 29#include <asm/clock.h> 30#include <asm/suspend.h> 31#include <cpu/sh7723.h> 32 33static struct smsc911x_platform_config smsc911x_config = { 34 .phy_interface = PHY_INTERFACE_MODE_MII, 35 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 36 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 37 .flags = SMSC911X_USE_32BIT, 38}; 39 40static struct resource smsc9118_resources[] = { 41 [0] = { 42 .start = 0xb6080000, 43 .end = 0xb60fffff, 44 .flags = IORESOURCE_MEM, 45 }, 46 [1] = { 47 .start = 35, 48 .end = 35, 49 .flags = IORESOURCE_IRQ, 50 } 51}; 52 53static struct platform_device smsc9118_device = { 54 .name = "smsc911x", 55 .id = -1, 56 .num_resources = ARRAY_SIZE(smsc9118_resources), 57 .resource = smsc9118_resources, 58 .dev = { 59 .platform_data = &smsc911x_config, 60 }, 61}; 62 63/* 64 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF). 65 * If this area erased, this board can not boot. 66 */ 67static struct mtd_partition ap325rxa_nor_flash_partitions[] = { 68 { 69 .name = "uboot", 70 .offset = 0, 71 .size = (1 * 1024 * 1024), 72 .mask_flags = MTD_WRITEABLE, /* Read-only */ 73 }, { 74 .name = "kernel", 75 .offset = MTDPART_OFS_APPEND, 76 .size = (2 * 1024 * 1024), 77 }, { 78 .name = "free-area0", 79 .offset = MTDPART_OFS_APPEND, 80 .size = ((7 * 1024 * 1024) + (512 * 1024)), 81 }, { 82 .name = "CPLD-Data", 83 .offset = MTDPART_OFS_APPEND, 84 .mask_flags = MTD_WRITEABLE, /* Read-only */ 85 .size = (1024 * 128 * 2), 86 }, { 87 .name = "free-area1", 88 .offset = MTDPART_OFS_APPEND, 89 .size = MTDPART_SIZ_FULL, 90 }, 91}; 92 93static struct physmap_flash_data ap325rxa_nor_flash_data = { 94 .width = 2, 95 .parts = ap325rxa_nor_flash_partitions, 96 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), 97}; 98 99static struct resource ap325rxa_nor_flash_resources[] = { 100 [0] = { 101 .name = "NOR Flash", 102 .start = 0x00000000, 103 .end = 0x00ffffff, 104 .flags = IORESOURCE_MEM, 105 } 106}; 107 108static struct platform_device ap325rxa_nor_flash_device = { 109 .name = "physmap-flash", 110 .resource = ap325rxa_nor_flash_resources, 111 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), 112 .dev = { 113 .platform_data = &ap325rxa_nor_flash_data, 114 }, 115}; 116 117static struct mtd_partition nand_partition_info[] = { 118 { 119 .name = "nand_data", 120 .offset = 0, 121 .size = MTDPART_SIZ_FULL, 122 }, 123}; 124 125static struct resource nand_flash_resources[] = { 126 [0] = { 127 .start = 0xa4530000, 128 .end = 0xa45300ff, 129 .flags = IORESOURCE_MEM, 130 } 131}; 132 133static struct sh_flctl_platform_data nand_flash_data = { 134 .parts = nand_partition_info, 135 .nr_parts = ARRAY_SIZE(nand_partition_info), 136 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E, 137 .has_hwecc = 1, 138}; 139 140static struct platform_device nand_flash_device = { 141 .name = "sh_flctl", 142 .resource = nand_flash_resources, 143 .num_resources = ARRAY_SIZE(nand_flash_resources), 144 .dev = { 145 .platform_data = &nand_flash_data, 146 }, 147}; 148 149#define FPGA_LCDREG 0xB4100180 150#define FPGA_BKLREG 0xB4100212 151#define FPGA_LCDREG_VAL 0x0018 152#define PORT_MSELCRB 0xA4050182 153#define PORT_HIZCRC 0xA405015C 154#define PORT_DRVCRA 0xA405018A 155#define PORT_DRVCRB 0xA405018C 156 157static void ap320_wvga_power_on(void *board_data, struct fb_info *info) 158{ 159 msleep(100); 160 161 /* ASD AP-320/325 LCD ON */ 162 __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG); 163 164 /* backlight */ 165 gpio_set_value(GPIO_PTS3, 0); 166 __raw_writew(0x100, FPGA_BKLREG); 167} 168 169static void ap320_wvga_power_off(void *board_data) 170{ 171 /* backlight */ 172 __raw_writew(0, FPGA_BKLREG); 173 gpio_set_value(GPIO_PTS3, 1); 174 175 /* ASD AP-320/325 LCD OFF */ 176 __raw_writew(0, FPGA_LCDREG); 177} 178 179static struct sh_mobile_lcdc_info lcdc_info = { 180 .clock_source = LCDC_CLK_EXTERNAL, 181 .ch[0] = { 182 .chan = LCDC_CHAN_MAINLCD, 183 .bpp = 16, 184 .interface_type = RGB18, 185 .clock_divider = 1, 186 .lcd_cfg = { 187 .name = "LB070WV1", 188 .xres = 800, 189 .yres = 480, 190 .left_margin = 32, 191 .right_margin = 160, 192 .hsync_len = 8, 193 .upper_margin = 63, 194 .lower_margin = 80, 195 .vsync_len = 1, 196 .sync = 0, /* hsync and vsync are active low */ 197 }, 198 .lcd_size_cfg = { /* 7.0 inch */ 199 .width = 152, 200 .height = 91, 201 }, 202 .board_cfg = { 203 .display_on = ap320_wvga_power_on, 204 .display_off = ap320_wvga_power_off, 205 }, 206 } 207}; 208 209static struct resource lcdc_resources[] = { 210 [0] = { 211 .name = "LCDC", 212 .start = 0xfe940000, /* P4-only space */ 213 .end = 0xfe942fff, 214 .flags = IORESOURCE_MEM, 215 }, 216 [1] = { 217 .start = 28, 218 .flags = IORESOURCE_IRQ, 219 }, 220}; 221 222static struct platform_device lcdc_device = { 223 .name = "sh_mobile_lcdc_fb", 224 .num_resources = ARRAY_SIZE(lcdc_resources), 225 .resource = lcdc_resources, 226 .dev = { 227 .platform_data = &lcdc_info, 228 }, 229 .archdata = { 230 .hwblk_id = HWBLK_LCDC, 231 }, 232}; 233 234static void camera_power(int val) 235{ 236 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */ 237 mdelay(10); 238} 239 240#ifdef CONFIG_I2C 241/* support for the old ncm03j camera */ 242static unsigned char camera_ncm03j_magic[] = 243{ 244 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, 245 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, 246 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, 247 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, 248 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, 249 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, 250 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, 251 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, 252 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, 253 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, 254 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, 255 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, 256 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, 257 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, 258 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, 259 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, 260}; 261 262static int camera_probe(void) 263{ 264 struct i2c_adapter *a = i2c_get_adapter(0); 265 struct i2c_msg msg; 266 int ret; 267 268 if (!a) 269 return -ENODEV; 270 271 camera_power(1); 272 msg.addr = 0x6e; 273 msg.buf = camera_ncm03j_magic; 274 msg.len = 2; 275 msg.flags = 0; 276 ret = i2c_transfer(a, &msg, 1); 277 camera_power(0); 278 279 return ret; 280} 281 282static int camera_set_capture(struct soc_camera_platform_info *info, 283 int enable) 284{ 285 struct i2c_adapter *a = i2c_get_adapter(0); 286 struct i2c_msg msg; 287 int ret = 0; 288 int i; 289 290 camera_power(0); 291 if (!enable) 292 return 0; /* no disable for now */ 293 294 camera_power(1); 295 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { 296 u_int8_t buf[8]; 297 298 msg.addr = 0x6e; 299 msg.buf = buf; 300 msg.len = 2; 301 msg.flags = 0; 302 303 buf[0] = camera_ncm03j_magic[i]; 304 buf[1] = camera_ncm03j_magic[i + 1]; 305 306 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); 307 } 308 309 return ret; 310} 311 312static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev); 313static void ap325rxa_camera_del(struct soc_camera_link *icl); 314 315static struct soc_camera_platform_info camera_info = { 316 .format_name = "UYVY", 317 .format_depth = 16, 318 .format = { 319 .code = V4L2_MBUS_FMT_UYVY8_2X8, 320 .colorspace = V4L2_COLORSPACE_SMPTE170M, 321 .field = V4L2_FIELD_NONE, 322 .width = 640, 323 .height = 480, 324 }, 325 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | 326 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | 327 SOCAM_DATA_ACTIVE_HIGH, 328 .set_capture = camera_set_capture, 329}; 330 331static struct soc_camera_link camera_link = { 332 .bus_id = 0, 333 .add_device = ap325rxa_camera_add, 334 .del_device = ap325rxa_camera_del, 335 .module_name = "soc_camera_platform", 336 .priv = &camera_info, 337}; 338 339static void dummy_release(struct device *dev) 340{ 341} 342 343static struct platform_device camera_device = { 344 .name = "soc_camera_platform", 345 .dev = { 346 .platform_data = &camera_info, 347 .release = dummy_release, 348 }, 349}; 350 351static int ap325rxa_camera_add(struct soc_camera_link *icl, 352 struct device *dev) 353{ 354 if (icl != &camera_link || camera_probe() <= 0) 355 return -ENODEV; 356 357 camera_info.dev = dev; 358 359 return platform_device_register(&camera_device); 360} 361 362static void ap325rxa_camera_del(struct soc_camera_link *icl) 363{ 364 if (icl != &camera_link) 365 return; 366 367 platform_device_unregister(&camera_device); 368 memset(&camera_device.dev.kobj, 0, 369 sizeof(camera_device.dev.kobj)); 370} 371#endif /* CONFIG_I2C */ 372 373static int ov7725_power(struct device *dev, int mode) 374{ 375 camera_power(0); 376 if (mode) 377 camera_power(1); 378 379 return 0; 380} 381 382static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 383 .flags = SH_CEU_FLAG_USE_8BIT_BUS, 384}; 385 386static struct resource ceu_resources[] = { 387 [0] = { 388 .name = "CEU", 389 .start = 0xfe910000, 390 .end = 0xfe91009f, 391 .flags = IORESOURCE_MEM, 392 }, 393 [1] = { 394 .start = 52, 395 .flags = IORESOURCE_IRQ, 396 }, 397 [2] = { 398 /* place holder for contiguous memory */ 399 }, 400}; 401 402static struct platform_device ceu_device = { 403 .name = "sh_mobile_ceu", 404 .id = 0, /* "ceu0" clock */ 405 .num_resources = ARRAY_SIZE(ceu_resources), 406 .resource = ceu_resources, 407 .dev = { 408 .platform_data = &sh_mobile_ceu_info, 409 }, 410 .archdata = { 411 .hwblk_id = HWBLK_CEU, 412 }, 413}; 414 415static struct resource sdhi0_cn3_resources[] = { 416 [0] = { 417 .name = "SDHI0", 418 .start = 0x04ce0000, 419 .end = 0x04ce01ff, 420 .flags = IORESOURCE_MEM, 421 }, 422 [1] = { 423 .start = 100, 424 .flags = IORESOURCE_IRQ, 425 }, 426}; 427 428static struct platform_device sdhi0_cn3_device = { 429 .name = "sh_mobile_sdhi", 430 .id = 0, /* "sdhi0" clock */ 431 .num_resources = ARRAY_SIZE(sdhi0_cn3_resources), 432 .resource = sdhi0_cn3_resources, 433 .archdata = { 434 .hwblk_id = HWBLK_SDHI0, 435 }, 436}; 437 438static struct resource sdhi1_cn7_resources[] = { 439 [0] = { 440 .name = "SDHI1", 441 .start = 0x04cf0000, 442 .end = 0x04cf01ff, 443 .flags = IORESOURCE_MEM, 444 }, 445 [1] = { 446 .start = 23, 447 .flags = IORESOURCE_IRQ, 448 }, 449}; 450 451static struct platform_device sdhi1_cn7_device = { 452 .name = "sh_mobile_sdhi", 453 .id = 1, /* "sdhi1" clock */ 454 .num_resources = ARRAY_SIZE(sdhi1_cn7_resources), 455 .resource = sdhi1_cn7_resources, 456 .archdata = { 457 .hwblk_id = HWBLK_SDHI1, 458 }, 459}; 460 461static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { 462 { 463 I2C_BOARD_INFO("pcf8563", 0x51), 464 }, 465}; 466 467static struct i2c_board_info ap325rxa_i2c_camera[] = { 468 { 469 I2C_BOARD_INFO("ov772x", 0x21), 470 }, 471}; 472 473static struct ov772x_camera_info ov7725_info = { 474 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP | \ 475 OV772X_FLAG_8BIT, 476 .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), 477}; 478 479static struct soc_camera_link ov7725_link = { 480 .bus_id = 0, 481 .power = ov7725_power, 482 .board_info = &ap325rxa_i2c_camera[0], 483 .i2c_adapter_id = 0, 484 .module_name = "ov772x", 485 .priv = &ov7725_info, 486}; 487 488static struct platform_device ap325rxa_camera[] = { 489 { 490 .name = "soc-camera-pdrv", 491 .id = 0, 492 .dev = { 493 .platform_data = &ov7725_link, 494 }, 495 }, { 496 .name = "soc-camera-pdrv", 497 .id = 1, 498 .dev = { 499 .platform_data = &camera_link, 500 }, 501 }, 502}; 503 504static struct platform_device *ap325rxa_devices[] __initdata = { 505 &smsc9118_device, 506 &ap325rxa_nor_flash_device, 507 &lcdc_device, 508 &ceu_device, 509 &nand_flash_device, 510 &sdhi0_cn3_device, 511 &sdhi1_cn7_device, 512 &ap325rxa_camera[0], 513 &ap325rxa_camera[1], 514}; 515 516extern char ap325rxa_sdram_enter_start; 517extern char ap325rxa_sdram_enter_end; 518extern char ap325rxa_sdram_leave_start; 519extern char ap325rxa_sdram_leave_end; 520 521static int __init ap325rxa_devices_setup(void) 522{ 523 /* register board specific self-refresh code */ 524 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, 525 &ap325rxa_sdram_enter_start, 526 &ap325rxa_sdram_enter_end, 527 &ap325rxa_sdram_leave_start, 528 &ap325rxa_sdram_leave_end); 529 530 /* LD3 and LD4 LEDs */ 531 gpio_request(GPIO_PTX5, NULL); /* RUN */ 532 gpio_direction_output(GPIO_PTX5, 1); 533 gpio_export(GPIO_PTX5, 0); 534 535 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */ 536 gpio_direction_output(GPIO_PTX4, 0); 537 gpio_export(GPIO_PTX4, 0); 538 539 /* SW1 input */ 540 gpio_request(GPIO_PTF7, NULL); /* MODE */ 541 gpio_direction_input(GPIO_PTF7); 542 gpio_export(GPIO_PTF7, 0); 543 544 /* LCDC */ 545 gpio_request(GPIO_FN_LCDD15, NULL); 546 gpio_request(GPIO_FN_LCDD14, NULL); 547 gpio_request(GPIO_FN_LCDD13, NULL); 548 gpio_request(GPIO_FN_LCDD12, NULL); 549 gpio_request(GPIO_FN_LCDD11, NULL); 550 gpio_request(GPIO_FN_LCDD10, NULL); 551 gpio_request(GPIO_FN_LCDD9, NULL); 552 gpio_request(GPIO_FN_LCDD8, NULL); 553 gpio_request(GPIO_FN_LCDD7, NULL); 554 gpio_request(GPIO_FN_LCDD6, NULL); 555 gpio_request(GPIO_FN_LCDD5, NULL); 556 gpio_request(GPIO_FN_LCDD4, NULL); 557 gpio_request(GPIO_FN_LCDD3, NULL); 558 gpio_request(GPIO_FN_LCDD2, NULL); 559 gpio_request(GPIO_FN_LCDD1, NULL); 560 gpio_request(GPIO_FN_LCDD0, NULL); 561 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL); 562 gpio_request(GPIO_FN_LCDDCK, NULL); 563 gpio_request(GPIO_FN_LCDVEPWC, NULL); 564 gpio_request(GPIO_FN_LCDVCPWC, NULL); 565 gpio_request(GPIO_FN_LCDVSYN, NULL); 566 gpio_request(GPIO_FN_LCDHSYN, NULL); 567 gpio_request(GPIO_FN_LCDDISP, NULL); 568 gpio_request(GPIO_FN_LCDDON, NULL); 569 570 /* LCD backlight */ 571 gpio_request(GPIO_PTS3, NULL); 572 gpio_direction_output(GPIO_PTS3, 1); 573 574 /* CEU */ 575 gpio_request(GPIO_FN_VIO_CLK2, NULL); 576 gpio_request(GPIO_FN_VIO_VD2, NULL); 577 gpio_request(GPIO_FN_VIO_HD2, NULL); 578 gpio_request(GPIO_FN_VIO_FLD, NULL); 579 gpio_request(GPIO_FN_VIO_CKO, NULL); 580 gpio_request(GPIO_FN_VIO_D15, NULL); 581 gpio_request(GPIO_FN_VIO_D14, NULL); 582 gpio_request(GPIO_FN_VIO_D13, NULL); 583 gpio_request(GPIO_FN_VIO_D12, NULL); 584 gpio_request(GPIO_FN_VIO_D11, NULL); 585 gpio_request(GPIO_FN_VIO_D10, NULL); 586 gpio_request(GPIO_FN_VIO_D9, NULL); 587 gpio_request(GPIO_FN_VIO_D8, NULL); 588 589 gpio_request(GPIO_PTZ7, NULL); 590 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */ 591 gpio_request(GPIO_PTZ6, NULL); 592 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */ 593 gpio_request(GPIO_PTZ5, NULL); 594 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */ 595 gpio_request(GPIO_PTZ4, NULL); 596 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */ 597 598 __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); 599 600 /* FLCTL */ 601 gpio_request(GPIO_FN_FCE, NULL); 602 gpio_request(GPIO_FN_NAF7, NULL); 603 gpio_request(GPIO_FN_NAF6, NULL); 604 gpio_request(GPIO_FN_NAF5, NULL); 605 gpio_request(GPIO_FN_NAF4, NULL); 606 gpio_request(GPIO_FN_NAF3, NULL); 607 gpio_request(GPIO_FN_NAF2, NULL); 608 gpio_request(GPIO_FN_NAF1, NULL); 609 gpio_request(GPIO_FN_NAF0, NULL); 610 gpio_request(GPIO_FN_FCDE, NULL); 611 gpio_request(GPIO_FN_FOE, NULL); 612 gpio_request(GPIO_FN_FSC, NULL); 613 gpio_request(GPIO_FN_FWE, NULL); 614 gpio_request(GPIO_FN_FRB, NULL); 615 616 __raw_writew(0, PORT_HIZCRC); 617 __raw_writew(0xFFFF, PORT_DRVCRA); 618 __raw_writew(0xFFFF, PORT_DRVCRB); 619 620 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); 621 622 /* SDHI0 - CN3 - SD CARD */ 623 gpio_request(GPIO_FN_SDHI0CD_PTD, NULL); 624 gpio_request(GPIO_FN_SDHI0WP_PTD, NULL); 625 gpio_request(GPIO_FN_SDHI0D3_PTD, NULL); 626 gpio_request(GPIO_FN_SDHI0D2_PTD, NULL); 627 gpio_request(GPIO_FN_SDHI0D1_PTD, NULL); 628 gpio_request(GPIO_FN_SDHI0D0_PTD, NULL); 629 gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL); 630 gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL); 631 632 /* SDHI1 - CN7 - MICRO SD CARD */ 633 gpio_request(GPIO_FN_SDHI1CD, NULL); 634 gpio_request(GPIO_FN_SDHI1D3, NULL); 635 gpio_request(GPIO_FN_SDHI1D2, NULL); 636 gpio_request(GPIO_FN_SDHI1D1, NULL); 637 gpio_request(GPIO_FN_SDHI1D0, NULL); 638 gpio_request(GPIO_FN_SDHI1CMD, NULL); 639 gpio_request(GPIO_FN_SDHI1CLK, NULL); 640 641 i2c_register_board_info(0, ap325rxa_i2c_devices, 642 ARRAY_SIZE(ap325rxa_i2c_devices)); 643 644 return platform_add_devices(ap325rxa_devices, 645 ARRAY_SIZE(ap325rxa_devices)); 646} 647arch_initcall(ap325rxa_devices_setup); 648 649/* Return the board specific boot mode pin configuration */ 650static int ap325rxa_mode_pins(void) 651{ 652 /* MD0=0, MD1=0, MD2=0: Clock Mode 0 653 * MD3=0: 16-bit Area0 Bus Width 654 * MD5=1: Little Endian 655 * TSTMD=1, MD8=1: Test Mode Disabled 656 */ 657 return MODE_PIN5 | MODE_PIN8; 658} 659 660static struct sh_machine_vector mv_ap325rxa __initmv = { 661 .mv_name = "AP-325RXA", 662 .mv_mode_pins = ap325rxa_mode_pins, 663}; 664