1/* 2 * arch/powerpc/sysdev/uic.c 3 * 4 * IBM PowerPC 4xx Universal Interrupt Controller 5 * 6 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13#include <linux/kernel.h> 14#include <linux/init.h> 15#include <linux/errno.h> 16#include <linux/reboot.h> 17#include <linux/slab.h> 18#include <linux/stddef.h> 19#include <linux/sched.h> 20#include <linux/signal.h> 21#include <linux/sysdev.h> 22#include <linux/device.h> 23#include <linux/bootmem.h> 24#include <linux/spinlock.h> 25#include <linux/irq.h> 26#include <linux/interrupt.h> 27#include <linux/kernel_stat.h> 28#include <asm/irq.h> 29#include <asm/io.h> 30#include <asm/prom.h> 31#include <asm/dcr.h> 32 33#define NR_UIC_INTS 32 34 35#define UIC_SR 0x0 36#define UIC_ER 0x2 37#define UIC_CR 0x3 38#define UIC_PR 0x4 39#define UIC_TR 0x5 40#define UIC_MSR 0x6 41#define UIC_VR 0x7 42#define UIC_VCR 0x8 43 44#define uic_irq_to_hw(virq) (irq_map[virq].hwirq) 45 46struct uic *primary_uic; 47 48struct uic { 49 int index; 50 int dcrbase; 51 52 spinlock_t lock; 53 54 /* The remapper for this UIC */ 55 struct irq_host *irqhost; 56}; 57 58static void uic_unmask_irq(unsigned int virq) 59{ 60 struct irq_desc *desc = irq_to_desc(virq); 61 struct uic *uic = get_irq_chip_data(virq); 62 unsigned int src = uic_irq_to_hw(virq); 63 unsigned long flags; 64 u32 er, sr; 65 66 sr = 1 << (31-src); 67 spin_lock_irqsave(&uic->lock, flags); 68 /* ack level-triggered interrupts here */ 69 if (desc->status & IRQ_LEVEL) 70 mtdcr(uic->dcrbase + UIC_SR, sr); 71 er = mfdcr(uic->dcrbase + UIC_ER); 72 er |= sr; 73 mtdcr(uic->dcrbase + UIC_ER, er); 74 spin_unlock_irqrestore(&uic->lock, flags); 75} 76 77static void uic_mask_irq(unsigned int virq) 78{ 79 struct uic *uic = get_irq_chip_data(virq); 80 unsigned int src = uic_irq_to_hw(virq); 81 unsigned long flags; 82 u32 er; 83 84 spin_lock_irqsave(&uic->lock, flags); 85 er = mfdcr(uic->dcrbase + UIC_ER); 86 er &= ~(1 << (31 - src)); 87 mtdcr(uic->dcrbase + UIC_ER, er); 88 spin_unlock_irqrestore(&uic->lock, flags); 89} 90 91static void uic_ack_irq(unsigned int virq) 92{ 93 struct uic *uic = get_irq_chip_data(virq); 94 unsigned int src = uic_irq_to_hw(virq); 95 unsigned long flags; 96 97 spin_lock_irqsave(&uic->lock, flags); 98 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); 99 spin_unlock_irqrestore(&uic->lock, flags); 100} 101 102static void uic_mask_ack_irq(unsigned int virq) 103{ 104 struct irq_desc *desc = irq_to_desc(virq); 105 struct uic *uic = get_irq_chip_data(virq); 106 unsigned int src = uic_irq_to_hw(virq); 107 unsigned long flags; 108 u32 er, sr; 109 110 sr = 1 << (31-src); 111 spin_lock_irqsave(&uic->lock, flags); 112 er = mfdcr(uic->dcrbase + UIC_ER); 113 er &= ~sr; 114 mtdcr(uic->dcrbase + UIC_ER, er); 115 /* On the UIC, acking (i.e. clearing the SR bit) 116 * a level irq will have no effect if the interrupt 117 * is still asserted by the device, even if 118 * the interrupt is already masked. Therefore 119 * we only ack the egde interrupts here, while 120 * level interrupts are ack'ed after the actual 121 * isr call in the uic_unmask_irq() 122 */ 123 if (!(desc->status & IRQ_LEVEL)) 124 mtdcr(uic->dcrbase + UIC_SR, sr); 125 spin_unlock_irqrestore(&uic->lock, flags); 126} 127 128static int uic_set_irq_type(unsigned int virq, unsigned int flow_type) 129{ 130 struct uic *uic = get_irq_chip_data(virq); 131 unsigned int src = uic_irq_to_hw(virq); 132 struct irq_desc *desc = irq_to_desc(virq); 133 unsigned long flags; 134 int trigger, polarity; 135 u32 tr, pr, mask; 136 137 switch (flow_type & IRQ_TYPE_SENSE_MASK) { 138 case IRQ_TYPE_NONE: 139 uic_mask_irq(virq); 140 return 0; 141 142 case IRQ_TYPE_EDGE_RISING: 143 trigger = 1; polarity = 1; 144 break; 145 case IRQ_TYPE_EDGE_FALLING: 146 trigger = 1; polarity = 0; 147 break; 148 case IRQ_TYPE_LEVEL_HIGH: 149 trigger = 0; polarity = 1; 150 break; 151 case IRQ_TYPE_LEVEL_LOW: 152 trigger = 0; polarity = 0; 153 break; 154 default: 155 return -EINVAL; 156 } 157 158 mask = ~(1 << (31 - src)); 159 160 spin_lock_irqsave(&uic->lock, flags); 161 tr = mfdcr(uic->dcrbase + UIC_TR); 162 pr = mfdcr(uic->dcrbase + UIC_PR); 163 tr = (tr & mask) | (trigger << (31-src)); 164 pr = (pr & mask) | (polarity << (31-src)); 165 166 mtdcr(uic->dcrbase + UIC_PR, pr); 167 mtdcr(uic->dcrbase + UIC_TR, tr); 168 169 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 170 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 171 if (!trigger) 172 desc->status |= IRQ_LEVEL; 173 174 spin_unlock_irqrestore(&uic->lock, flags); 175 176 return 0; 177} 178 179static struct irq_chip uic_irq_chip = { 180 .name = "UIC", 181 .unmask = uic_unmask_irq, 182 .mask = uic_mask_irq, 183 .mask_ack = uic_mask_ack_irq, 184 .ack = uic_ack_irq, 185 .set_type = uic_set_irq_type, 186}; 187 188static int uic_host_map(struct irq_host *h, unsigned int virq, 189 irq_hw_number_t hw) 190{ 191 struct uic *uic = h->host_data; 192 193 set_irq_chip_data(virq, uic); 194 set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); 195 196 /* Set default irq type */ 197 set_irq_type(virq, IRQ_TYPE_NONE); 198 199 return 0; 200} 201 202static int uic_host_xlate(struct irq_host *h, struct device_node *ct, 203 const u32 *intspec, unsigned int intsize, 204 irq_hw_number_t *out_hwirq, unsigned int *out_type) 205 206{ 207 /* UIC intspecs must have 2 cells */ 208 BUG_ON(intsize != 2); 209 *out_hwirq = intspec[0]; 210 *out_type = intspec[1]; 211 return 0; 212} 213 214static struct irq_host_ops uic_host_ops = { 215 .map = uic_host_map, 216 .xlate = uic_host_xlate, 217}; 218 219void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) 220{ 221 struct uic *uic = get_irq_data(virq); 222 u32 msr; 223 int src; 224 int subvirq; 225 226 raw_spin_lock(&desc->lock); 227 if (desc->status & IRQ_LEVEL) 228 desc->chip->mask(virq); 229 else 230 desc->chip->mask_ack(virq); 231 raw_spin_unlock(&desc->lock); 232 233 msr = mfdcr(uic->dcrbase + UIC_MSR); 234 if (!msr) /* spurious interrupt */ 235 goto uic_irq_ret; 236 237 src = 32 - ffs(msr); 238 239 subvirq = irq_linear_revmap(uic->irqhost, src); 240 generic_handle_irq(subvirq); 241 242uic_irq_ret: 243 raw_spin_lock(&desc->lock); 244 if (desc->status & IRQ_LEVEL) 245 desc->chip->ack(virq); 246 if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) 247 desc->chip->unmask(virq); 248 raw_spin_unlock(&desc->lock); 249} 250 251static struct uic * __init uic_init_one(struct device_node *node) 252{ 253 struct uic *uic; 254 const u32 *indexp, *dcrreg; 255 int len; 256 257 BUG_ON(! of_device_is_compatible(node, "ibm,uic")); 258 259 uic = kzalloc(sizeof(*uic), GFP_KERNEL); 260 if (! uic) 261 return NULL; 262 263 spin_lock_init(&uic->lock); 264 indexp = of_get_property(node, "cell-index", &len); 265 if (!indexp || (len != sizeof(u32))) { 266 printk(KERN_ERR "uic: Device node %s has missing or invalid " 267 "cell-index property\n", node->full_name); 268 return NULL; 269 } 270 uic->index = *indexp; 271 272 dcrreg = of_get_property(node, "dcr-reg", &len); 273 if (!dcrreg || (len != 2*sizeof(u32))) { 274 printk(KERN_ERR "uic: Device node %s has missing or invalid " 275 "dcr-reg property\n", node->full_name); 276 return NULL; 277 } 278 uic->dcrbase = *dcrreg; 279 280 uic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 281 NR_UIC_INTS, &uic_host_ops, -1); 282 if (! uic->irqhost) 283 return NULL; 284 285 uic->irqhost->host_data = uic; 286 287 /* Start with all interrupts disabled, level and non-critical */ 288 mtdcr(uic->dcrbase + UIC_ER, 0); 289 mtdcr(uic->dcrbase + UIC_CR, 0); 290 mtdcr(uic->dcrbase + UIC_TR, 0); 291 /* Clear any pending interrupts, in case the firmware left some */ 292 mtdcr(uic->dcrbase + UIC_SR, 0xffffffff); 293 294 printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index, 295 NR_UIC_INTS, uic->dcrbase); 296 297 return uic; 298} 299 300void __init uic_init_tree(void) 301{ 302 struct device_node *np; 303 struct uic *uic; 304 const u32 *interrupts; 305 306 /* First locate and initialize the top-level UIC */ 307 for_each_compatible_node(np, NULL, "ibm,uic") { 308 interrupts = of_get_property(np, "interrupts", NULL); 309 if (!interrupts) 310 break; 311 } 312 313 BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the 314 * top-level interrupt controller */ 315 primary_uic = uic_init_one(np); 316 if (!primary_uic) 317 panic("Unable to initialize primary UIC %s\n", np->full_name); 318 319 irq_set_default_host(primary_uic->irqhost); 320 of_node_put(np); 321 322 /* The scan again for cascaded UICs */ 323 for_each_compatible_node(np, NULL, "ibm,uic") { 324 interrupts = of_get_property(np, "interrupts", NULL); 325 if (interrupts) { 326 /* Secondary UIC */ 327 int cascade_virq; 328 329 uic = uic_init_one(np); 330 if (! uic) 331 panic("Unable to initialize a secondary UIC %s\n", 332 np->full_name); 333 334 cascade_virq = irq_of_parse_and_map(np, 0); 335 336 set_irq_data(cascade_virq, uic); 337 set_irq_chained_handler(cascade_virq, uic_irq_cascade); 338 339 } 340 } 341} 342 343/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ 344unsigned int uic_get_irq(void) 345{ 346 u32 msr; 347 int src; 348 349 BUG_ON(! primary_uic); 350 351 msr = mfdcr(primary_uic->dcrbase + UIC_MSR); 352 src = 32 - ffs(msr); 353 354 return irq_linear_revmap(primary_uic->irqhost, src); 355} 356